DE68918775D1 - Chip-auf-Chip-Verbindungsschema für integrierte Halbleiterschaltungen. - Google Patents

Chip-auf-Chip-Verbindungsschema für integrierte Halbleiterschaltungen.

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Publication number
DE68918775D1
DE68918775D1 DE68918775T DE68918775T DE68918775D1 DE 68918775 D1 DE68918775 D1 DE 68918775D1 DE 68918775 T DE68918775 T DE 68918775T DE 68918775 T DE68918775 T DE 68918775T DE 68918775 D1 DE68918775 D1 DE 68918775D1
Authority
DE
Germany
Prior art keywords
chip
integrated circuits
semiconductor integrated
connection scheme
chip connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68918775T
Other languages
English (en)
Other versions
DE68918775T2 (de
Inventor
Greg E Blonder
Theodore Alan Fulton
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Corp filed Critical AT&T Corp
Publication of DE68918775D1 publication Critical patent/DE68918775D1/de
Application granted granted Critical
Publication of DE68918775T2 publication Critical patent/DE68918775T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147Semiconductor insulating substrates
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    • H01L23/13Mountings, e.g. non-detachable insulating substrates characterised by the shape
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE68918775T 1988-07-21 1989-07-13 Chip-auf-Chip-Verbindungsschema für integrierte Halbleiterschaltungen. Expired - Fee Related DE68918775T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/222,465 US4937653A (en) 1988-07-21 1988-07-21 Semiconductor integrated circuit chip-to-chip interconnection scheme

Publications (2)

Publication Number Publication Date
DE68918775D1 true DE68918775D1 (de) 1994-11-17
DE68918775T2 DE68918775T2 (de) 1995-02-16

Family

ID=22832332

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68918775T Expired - Fee Related DE68918775T2 (de) 1988-07-21 1989-07-13 Chip-auf-Chip-Verbindungsschema für integrierte Halbleiterschaltungen.

Country Status (4)

Country Link
US (2) US4937653A (de)
EP (1) EP0352020B1 (de)
JP (1) JPH0267742A (de)
DE (1) DE68918775T2 (de)

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US5124281A (en) * 1990-08-27 1992-06-23 At&T Bell Laboratories Method of fabricating a photonics module comprising a spherical lens
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JP3137375B2 (ja) * 1990-09-20 2001-02-19 株式会社東芝 圧接型半導体装置
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US7198969B1 (en) 1990-09-24 2007-04-03 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
US20010030370A1 (en) * 1990-09-24 2001-10-18 Khandros Igor Y. Microelectronic assembly having encapsulated wire bonding leads
US5679977A (en) * 1990-09-24 1997-10-21 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
US5134539A (en) * 1990-12-17 1992-07-28 Nchip, Inc. Multichip module having integral decoupling capacitor
US5214844A (en) * 1990-12-17 1993-06-01 Nchip, Inc. Method of assembling integrated circuits to a silicon board
US5274270A (en) * 1990-12-17 1993-12-28 Nchip, Inc. Multichip module having SiO2 insulating layer
US5262674A (en) * 1991-02-04 1993-11-16 Motorola, Inc. Chip carrier for an integrated circuit assembly
US6219908B1 (en) * 1991-06-04 2001-04-24 Micron Technology, Inc. Method and apparatus for manufacturing known good semiconductor die
US5559444A (en) * 1991-06-04 1996-09-24 Micron Technology, Inc. Method and apparatus for testing unpackaged semiconductor dice
US5716218A (en) * 1991-06-04 1998-02-10 Micron Technology, Inc. Process for manufacturing an interconnect for testing a semiconductor die
US5946553A (en) * 1991-06-04 1999-08-31 Micron Technology, Inc. Process for manufacturing a semiconductor package with bi-substrate die
US5578934A (en) * 1991-06-04 1996-11-26 Micron Technology, Inc. Method and apparatus for testing unpackaged semiconductor dice
US5541525A (en) * 1991-06-04 1996-07-30 Micron Technology, Inc. Carrier for testing an unpackaged semiconductor die
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US4937653A (en) 1990-06-26
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EP0352020B1 (de) 1994-10-12
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EP0352020A2 (de) 1990-01-24
JPH0574224B2 (de) 1993-10-18

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