JPS61172362A - ボンデイング電極構造 - Google Patents

ボンデイング電極構造

Info

Publication number
JPS61172362A
JPS61172362A JP60013848A JP1384885A JPS61172362A JP S61172362 A JPS61172362 A JP S61172362A JP 60013848 A JP60013848 A JP 60013848A JP 1384885 A JP1384885 A JP 1384885A JP S61172362 A JPS61172362 A JP S61172362A
Authority
JP
Japan
Prior art keywords
bonding
electrode
electrode structure
bondability
section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60013848A
Other languages
English (en)
Inventor
Tadashi Yasue
匡 安江
Hiroshi Nakatani
宏 中谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP60013848A priority Critical patent/JPS61172362A/ja
Publication of JPS61172362A publication Critical patent/JPS61172362A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05557—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05558—Shape in side view conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81385—Shape, e.g. interlocking features

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はボンディング電極の構造に関する。
〔従来の技術〕
従来のボンディング電極構造は、電子材料、１９８５年
、５月号、Ｐ１０７〜Ｐ１１２．早用征男：ハイデンシ
ティボンデイングへのアプローチ　などで示される様に
、被ボンデイング部分が平担となっている。
〔発明が解決しようとする問題点〕
ボンデイング工程に於いて、その高速化）；進む中で、
ボンディング時間短縮に判う、ボンダビリティ低下が問
題となりている。
〔問題点を解決する為の手段〕
本発明はこの様な問題点を解決するもので、その目的と
するところは、ボンディング部分を凹凸構造とすること
で、ボンダビリティ向上を提供することにある。
〔実施例〕
以下、本発明について実施例に基づき詳細に説明する。
一実施例は、半導体に於けるポンディングパッド電極で
あり、例えば第１〜３図に示す様に、電極形成時のフォ
トエツチング工程で、−ボンディング部分を選択的に除
去するか、又は例えば第４図の様に電極形成前にパッド
下部に８１０！ガラス等を部分的に設けることにより凹
凸とした構造である。
第１〜３図にポンディングパッドを選択的にエツチング
した場合の電極構造例、第４図にパッド下に８１０．ガ
ラスを部券“的に設けた場合の電極構造例、第５図に従
来の電極構造を示す。
〔発明の効果〕
以上述べた様に、ポンディング部分を凹凸構造としたの
で、ボンディング相互間の接触面積を増加させることが
可能であり、従来の方式で問題となっている低ボンダビ
リティを向上させる効果を有する。
【図面の簡単な説明】
第１図はポンディングパッドを選択的にエツチングした
電極構造図。 第２図は、第１図中Ｘ−Ｘ’の電極断面構造図第３図は
電極の二層形成プロセスにより一層目を選択エツチング
した電極断面構造図。 第４図は、ポンディングパッド下にＳ　ｉ　Ｏ，ガラス
等を部分的に設けた電極断面構造図。 第５図は従来の電極断面構造図。 α・・・・・・ムＬのポンディングパッド電極ｂ・・・
・・・ＡＬのポンディングパッド電極一層目Ｃ・・・・
・・ＡＬ等のポンディングパッド電極二層目ｄ・・・・
・・Ｂ　ｉ　Ｏ，ガラス等の膜ｅ・・・・・・Ｓ１０．
ガラス等の保護膜以上

Claims (1)

    【特許請求の範囲】
  1. ボンディング部分を、凹凸構造とすることを特徴とする
    ボンディング電極構造。
JP60013848A 1985-01-28 1985-01-28 ボンデイング電極構造 Pending JPS61172362A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60013848A JPS61172362A (ja) 1985-01-28 1985-01-28 ボンデイング電極構造

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60013848A JPS61172362A (ja) 1985-01-28 1985-01-28 ボンデイング電極構造

Publications (1)

Publication Number Publication Date
JPS61172362A true JPS61172362A (ja) 1986-08-04

Family

ID=11844695

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60013848A Pending JPS61172362A (ja) 1985-01-28 1985-01-28 ボンデイング電極構造

Country Status (1)

Country Link
JP (1) JPS61172362A (ja)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE35119E (en) * 1988-07-21 1995-12-12 At&T Corp. Textured metallic compression bonding
EP0693782A1 (en) * 1994-07-13 1996-01-24 United Microelectronics Corporation Method for reducing process antenna effect
US5877833A (en) * 1990-09-10 1999-03-02 U.S. Philips Corporation Interconnection structure with raised perimeter portions
US6087756A (en) * 1997-08-11 2000-07-11 Murata Manufacturing Co., Ltd. Surface acoustic wave
WO2001022491A1 (en) * 1999-09-20 2001-03-29 Telefonaktiebolaget Lm Ericsson (Publ) Semiconductive chip having a bond pad located on an active device
US6414415B1 (en) 1999-02-18 2002-07-02 Murata Manufacturing Co., Ltd. Surface acoustic wave device and method for manufacturing the same
JP2006024877A (ja) * 2004-07-06 2006-01-26 Himax Optelectronics Corp ボンディングパッドとチップ構造
FR2959868A1 (fr) * 2010-05-06 2011-11-11 St Microelectronics Crolles 2 Dispositif semi-conducteur a plots de connexion munis d'inserts
US9796583B2 (en) 2004-11-04 2017-10-24 Microchips Biotech, Inc. Compression and cold weld sealing method for an electrical via connection

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE35119E (en) * 1988-07-21 1995-12-12 At&T Corp. Textured metallic compression bonding
US5877833A (en) * 1990-09-10 1999-03-02 U.S. Philips Corporation Interconnection structure with raised perimeter portions
EP0693782A1 (en) * 1994-07-13 1996-01-24 United Microelectronics Corporation Method for reducing process antenna effect
US6087756A (en) * 1997-08-11 2000-07-11 Murata Manufacturing Co., Ltd. Surface acoustic wave
US6414415B1 (en) 1999-02-18 2002-07-02 Murata Manufacturing Co., Ltd. Surface acoustic wave device and method for manufacturing the same
WO2001022491A1 (en) * 1999-09-20 2001-03-29 Telefonaktiebolaget Lm Ericsson (Publ) Semiconductive chip having a bond pad located on an active device
JP2003510815A (ja) * 1999-09-20 2003-03-18 テレフオンアクチーボラゲット エル エム エリクソン（パブル） 能動素子上に設けられた接着パッドを備える半導体チップ
US7060525B1 (en) 1999-09-20 2006-06-13 Telefonaktiebolaget L M Ericsson (Publ) Semiconductive chip having a bond pad located on an active device
JP2006024877A (ja) * 2004-07-06 2006-01-26 Himax Optelectronics Corp ボンディングパッドとチップ構造
US9796583B2 (en) 2004-11-04 2017-10-24 Microchips Biotech, Inc. Compression and cold weld sealing method for an electrical via connection
FR2959868A1 (fr) * 2010-05-06 2011-11-11 St Microelectronics Crolles 2 Dispositif semi-conducteur a plots de connexion munis d'inserts

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