DE60331042D1 - Verfahren zur Bearbeitung von einem Nitrid-Halbleiterwafer - Google Patents

Verfahren zur Bearbeitung von einem Nitrid-Halbleiterwafer

Info

Publication number
DE60331042D1
DE60331042D1 DE60331042T DE60331042T DE60331042D1 DE 60331042 D1 DE60331042 D1 DE 60331042D1 DE 60331042 T DE60331042 T DE 60331042T DE 60331042 T DE60331042 T DE 60331042T DE 60331042 D1 DE60331042 D1 DE 60331042D1
Authority
DE
Germany
Prior art keywords
processing
semiconductor wafer
nitride semiconductor
nitride
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60331042T
Other languages
English (en)
Inventor
Masahiro Nakayama
Naoki Matsumoto
Koshi Tamamura
Masao Ikeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Sumitomo Electric Industries Ltd
Original Assignee
Sony Corp
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2003281647A external-priority patent/JP3581145B6/ja
Application filed by Sony Corp, Sumitomo Electric Industries Ltd filed Critical Sony Corp
Application granted granted Critical
Publication of DE60331042D1 publication Critical patent/DE60331042D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
    • B24B37/07—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool
    • B24B37/08—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool for double side lapping
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/38—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02024—Mirror polishing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/959—Mechanical polishing of wafer

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Mechanical Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
  • Weting (AREA)
  • Recrystallisation Techniques (AREA)
  • Led Devices (AREA)
DE60331042T 2003-05-06 2003-10-23 Verfahren zur Bearbeitung von einem Nitrid-Halbleiterwafer Expired - Lifetime DE60331042D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2003128060 2003-05-06
JP2003281647A JP3581145B6 (ja) 2003-05-06 2003-07-29 窒化物半導体基板の加工方法

Publications (1)

Publication Number Publication Date
DE60331042D1 true DE60331042D1 (de) 2010-03-11

Family

ID=32993114

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60331042T Expired - Lifetime DE60331042D1 (de) 2003-05-06 2003-10-23 Verfahren zur Bearbeitung von einem Nitrid-Halbleiterwafer

Country Status (6)

Country Link
US (4) US6875082B2 (de)
EP (1) EP1475826B1 (de)
KR (1) KR100550491B1 (de)
CN (1) CN100416868C (de)
DE (1) DE60331042D1 (de)
TW (1) TWI239045B (de)

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JP4131101B2 (ja) 2001-11-28 2008-08-13 日亜化学工業株式会社 窒化物半導体素子の製造方法
KR100550491B1 (ko) * 2003-05-06 2006-02-09 스미토모덴키고교가부시키가이샤 질화물 반도체 기판 및 질화물 반도체 기판의 가공 방법

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US20090250790A1 (en) 2009-10-08
CN1549357A (zh) 2004-11-24
EP1475826B1 (de) 2010-01-20
CN100416868C (zh) 2008-09-03
US20040221799A1 (en) 2004-11-11
KR20040095138A (ko) 2004-11-12
US7786488B2 (en) 2010-08-31
US20100279440A1 (en) 2010-11-04
US6875082B2 (en) 2005-04-05
US8008165B2 (en) 2011-08-30
TW200425286A (en) 2004-11-16
EP1475826A3 (de) 2005-04-27
US20050145879A1 (en) 2005-07-07
TWI239045B (en) 2005-09-01
US7535082B2 (en) 2009-05-19
JP3581145B1 (ja) 2004-10-27

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