DE602006009593D1 - Verfahren zum Polieren von Halbleiterscheiben - Google Patents

Verfahren zum Polieren von Halbleiterscheiben

Info

Publication number
DE602006009593D1
DE602006009593D1 DE602006009593T DE602006009593T DE602006009593D1 DE 602006009593 D1 DE602006009593 D1 DE 602006009593D1 DE 602006009593 T DE602006009593 T DE 602006009593T DE 602006009593 T DE602006009593 T DE 602006009593T DE 602006009593 D1 DE602006009593 D1 DE 602006009593D1
Authority
DE
Germany
Prior art keywords
semiconductor wafers
polishing semiconductor
polishing
wafers
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006009593T
Other languages
English (en)
Inventor
Toshinari Murai
Yukio Shibano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Chemical Co Ltd
Original Assignee
Shin Etsu Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Etsu Chemical Co Ltd filed Critical Shin Etsu Chemical Co Ltd
Publication of DE602006009593D1 publication Critical patent/DE602006009593D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/27—Work carriers
    • B24B37/28—Work carriers for double side lapping of plane surfaces
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/27—Work carriers
    • B24B37/30—Work carriers for single side lapping of plane surfaces

Landscapes

  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
DE602006009593T 2005-08-31 2006-08-31 Verfahren zum Polieren von Halbleiterscheiben Active DE602006009593D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005251026 2005-08-31

Publications (1)

Publication Number Publication Date
DE602006009593D1 true DE602006009593D1 (de) 2009-11-19

Family

ID=37104779

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006009593T Active DE602006009593D1 (de) 2005-08-31 2006-08-31 Verfahren zum Polieren von Halbleiterscheiben

Country Status (5)

Country Link
US (1) US7588481B2 (de)
EP (1) EP1759810B8 (de)
KR (1) KR101174925B1 (de)
DE (1) DE602006009593D1 (de)
TW (1) TWI424484B (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8746132B2 (en) * 2005-08-12 2014-06-10 Lawrence Equipment Inc. Heated discharge platen for dough processing system
CA2723194C (en) 2008-05-01 2017-02-14 Lawrence Equipment, Inc. Vacuum pressing platen assembly and method for adjustment
JPWO2010097902A1 (ja) * 2009-02-25 2012-08-30 セイコーインスツル株式会社 ガラス基板の研磨方法、パッケージの製造方法、圧電振動子、発振器、電子機器並びに電波時計
US8963337B2 (en) * 2010-09-29 2015-02-24 Varian Semiconductor Equipment Associates Thin wafer support assembly
US8689685B2 (en) 2010-11-04 2014-04-08 Lawrence Equipment Inc. Dough forming pressing plate with spacers
WO2012119616A1 (en) * 2011-03-10 2012-09-13 Peter Wolters Gmbh Method and device for the single-sided processing of flat workpieces
US8662313B2 (en) 2011-07-20 2014-03-04 Lawrence Equipment Inc. Systems and methods for processing comestibles
US20140127857A1 (en) * 2012-11-07 2014-05-08 Taiwan Semiconductor Manufacturing Company, Ltd. Carrier Wafers, Methods of Manufacture Thereof, and Packaging Methods
JP6434266B2 (ja) * 2013-12-17 2018-12-05 富士紡ホールディングス株式会社 ラッピング用樹脂定盤及びそれを用いたラッピング方法
CN114770365A (zh) * 2022-04-19 2022-07-22 成都贝瑞光电科技股份有限公司 一种自适应拼装双面研抛工艺
CN115841973B (zh) * 2023-02-17 2023-04-28 成都莱普科技股份有限公司 一种用于晶圆激光退火的挡光环及其制备方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58129658A (ja) 1982-01-29 1983-08-02 Nec Corp マイクロプログラム制御装置
US4512113A (en) * 1982-09-23 1985-04-23 Budinger William D Workpiece holder for polishing operation
US4466852A (en) * 1983-10-27 1984-08-21 At&T Technologies, Inc. Method and apparatus for demounting wafers
JPS62297064A (ja) 1986-06-16 1987-12-24 Rodeele Nitta Kk 半導体等のウエ−ハ保持用積層体
JPS6393562A (ja) 1986-10-09 1988-04-23 Rodeele Nitta Kk ウェハの保持方法及びその装置
JPH0691058B2 (ja) 1988-10-06 1994-11-14 信越半導体株式会社 半導体ウエーハ研磨方法
US5267418A (en) * 1992-05-27 1993-12-07 International Business Machines Corporation Confined water fixture for holding wafers undergoing chemical-mechanical polishing
JP2933488B2 (ja) * 1994-08-10 1999-08-16 日本電気株式会社 研磨方法および研磨装置
US5685766A (en) * 1995-11-30 1997-11-11 Speedfam Corporation Polishing control method
JPH11309665A (ja) 1998-04-30 1999-11-09 Toshiba Corp 酸化物単結晶基板の製造方法
JP2000071170A (ja) * 1998-08-28 2000-03-07 Nitta Ind Corp 研磨用ウエハ保持部材及びそのウエハ保持部材の研磨機定盤への脱着方法
JP3697963B2 (ja) * 1999-08-30 2005-09-21 富士電機デバイステクノロジー株式会社 研磨布および平面研磨加工方法
JP3768069B2 (ja) * 2000-05-16 2006-04-19 信越半導体株式会社 半導体ウエーハの薄型化方法
JP2005034926A (ja) * 2003-07-16 2005-02-10 Shin Etsu Chem Co Ltd ウェーハ基板の研磨方法及びウェーハ

Also Published As

Publication number Publication date
TWI424484B (zh) 2014-01-21
EP1759810B1 (de) 2009-10-07
US7588481B2 (en) 2009-09-15
EP1759810B8 (de) 2009-11-18
TW200721292A (en) 2007-06-01
US20070045232A1 (en) 2007-03-01
EP1759810A1 (de) 2007-03-07
KR101174925B1 (ko) 2012-08-17
KR20070026172A (ko) 2007-03-08

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Legal Events

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8364 No opposition during term of opposition