DE4029826C2 - - Google Patents

Info

Publication number
DE4029826C2
DE4029826C2 DE4029826A DE4029826A DE4029826C2 DE 4029826 C2 DE4029826 C2 DE 4029826C2 DE 4029826 A DE4029826 A DE 4029826A DE 4029826 A DE4029826 A DE 4029826A DE 4029826 C2 DE4029826 C2 DE 4029826C2
Authority
DE
Germany
Prior art keywords
platinum
wafer
layer
silicon body
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE4029826A
Other languages
German (de)
English (en)
Other versions
DE4029826A1 (de
Inventor
Herbert J. Sherman Oaks Calif. Us Gould
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies Americas Corp
Original Assignee
International Rectifier Corp USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Rectifier Corp USA filed Critical International Rectifier Corp USA
Publication of DE4029826A1 publication Critical patent/DE4029826A1/de
Application granted granted Critical
Publication of DE4029826C2 publication Critical patent/DE4029826C2/de
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/221Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities of killers
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/904Charge carrier lifetime control

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Weting (AREA)
  • Superconductors And Manufacturing Methods Therefor (AREA)
  • Manufacture And Refinement Of Metals (AREA)
  • Inert Electrodes (AREA)
DE4029826A 1989-09-21 1990-09-20 Platindiffusionsverfahren fuer einen halbleiterkoerper Granted DE4029826A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/410,323 US4925812A (en) 1989-09-21 1989-09-21 Platinum diffusion process

Publications (2)

Publication Number Publication Date
DE4029826A1 DE4029826A1 (de) 1991-04-04
DE4029826C2 true DE4029826C2 (enExample) 1993-09-09

Family

ID=23624227

Family Applications (1)

Application Number Title Priority Date Filing Date
DE4029826A Granted DE4029826A1 (de) 1989-09-21 1990-09-20 Platindiffusionsverfahren fuer einen halbleiterkoerper

Country Status (6)

Country Link
US (1) US4925812A (enExample)
JP (1) JP2728147B2 (enExample)
AT (1) AT398014B (enExample)
DE (1) DE4029826A1 (enExample)
GB (1) GB2236119B (enExample)
IT (1) IT1246685B (enExample)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5262336A (en) * 1986-03-21 1993-11-16 Advanced Power Technology, Inc. IGBT process to produce platinum lifetime control
JP2752184B2 (ja) * 1989-09-11 1998-05-18 株式会社東芝 電力用半導体装置
IT1247293B (it) * 1990-05-09 1994-12-12 Int Rectifier Corp Dispositivo transistore di potenza presentante una regione ultra-profonda, a maggior concentrazione
IT1244119B (it) * 1990-11-29 1994-07-05 Cons Ric Microelettronica Processo di introduzione e diffusione di ioni di platino in una fetta di silicio
US6624477B1 (en) 1992-10-09 2003-09-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
TW232751B (en) * 1992-10-09 1994-10-21 Semiconductor Energy Res Co Ltd Semiconductor device and method for forming the same
JP3637069B2 (ja) 1993-03-12 2005-04-06 株式会社半導体エネルギー研究所 半導体装置の作製方法
KR100203982B1 (ko) * 1993-03-12 1999-06-15 야마자끼 순페이 반도체장치 및 그의 제작방법
US5635426A (en) * 1993-08-26 1997-06-03 Fujitsu Limited Method of making a semiconductor device having a silicide local interconnect
DE69421606T2 (de) * 1994-03-30 2000-05-31 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno, Catania Verfahren zur Herstellung von bipolaren Transistoren mit kontrollierter Speicherzeit
US6426248B2 (en) * 2000-02-15 2002-07-30 International Rectifier Corporation Process for forming power MOSFET device in float zone, non-epitaxial silicon
US6358825B1 (en) 2000-11-21 2002-03-19 Fairchild Semiconductor Corporation Process for controlling lifetime in a P-I-N diode and for forming diode with improved lifetime control
US20020195613A1 (en) * 2001-04-02 2002-12-26 International Rectifier Corp. Low cost fast recovery diode and process of its manufacture
AU2002246316A1 (en) * 2002-04-08 2003-10-27 Council Of Scientific And Industrial Research Process for the production of neodymium-iron-boron permanent magnet alloy powder
US7749877B2 (en) * 2006-03-07 2010-07-06 Siliconix Technology C. V. Process for forming Schottky rectifier with PtNi silicide Schottky barrier
DE102007020039B4 (de) * 2007-04-27 2011-07-14 Infineon Technologies Austria Ag Verfahren zur Herstellung einer vertikal inhomogenen Platin- oder Goldverteilung in einem Halbleitersubstrat und in einem Halbleiterbauelement, derart hergestelltes Halbleitersubstrat und Halbleiterbauelement
JP6319453B2 (ja) * 2014-10-03 2018-05-09 富士電機株式会社 半導体装置および半導体装置の製造方法
CN109671625A (zh) * 2017-10-13 2019-04-23 华润微电子(重庆)有限公司 快恢复二极管的制备方法
CN112002761A (zh) * 2020-09-07 2020-11-27 深圳市美浦森半导体有限公司 一种集成frd的dmos器件的制造方法及dmos器件

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3728592A (en) * 1969-05-09 1973-04-17 Ibm Semiconductor structure having reduced carrier lifetime
US3640783A (en) * 1969-08-11 1972-02-08 Trw Semiconductors Inc Semiconductor devices with diffused platinum
US3963523A (en) * 1973-04-26 1976-06-15 Matsushita Electronics Corporation Method of manufacturing semiconductor devices
DE2735769C3 (de) * 1977-08-09 1980-03-27 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Verfahren zur Einstellung der Minoritätsladungsträgerlebensdauer in Halbleiterbauelementen aus einkristallinem Silizium
JPS54106178A (en) * 1978-02-08 1979-08-20 Mitsubishi Electric Corp Thyristor and its manufacture
US4206540A (en) * 1978-06-02 1980-06-10 International Rectifier Corporation Schottky device and method of manufacture using palladium and platinum intermetallic alloys and titanium barrier
JPS5939898B2 (ja) * 1978-09-26 1984-09-27 三菱電機株式会社 半導体装置の製造方法
JPS5553462A (en) * 1978-10-13 1980-04-18 Int Rectifier Corp Mosfet element
US4593302B1 (en) * 1980-08-18 1998-02-03 Int Rectifier Corp Process for manufacture of high power mosfet laterally distributed high carrier density beneath the gate oxide
US4322453A (en) * 1980-12-08 1982-03-30 International Business Machines Corporation Conductivity WSi2 (tungsten silicide) films by Pt preanneal layering
US4398344A (en) * 1982-03-08 1983-08-16 International Rectifier Corporation Method of manufacture of a schottky using platinum encapsulated between layers of palladium sintered into silicon surface
JPS6084881A (ja) * 1983-10-17 1985-05-14 Toshiba Corp 大電力mos fetとその製造方法
JPS618916A (ja) * 1984-06-21 1986-01-16 インタ−ナシヨナル・ビジネス・マシ−ンズ・コ−ポレ−シヨン ド−プ領域の形成方法
US4791074A (en) * 1986-08-29 1988-12-13 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor apparatus
US4855799A (en) * 1987-12-22 1989-08-08 Kabushiki Kaisha Toshiba Power MOS FET with carrier lifetime killer

Also Published As

Publication number Publication date
IT9021494A0 (it) 1990-09-17
JP2728147B2 (ja) 1998-03-18
AT398014B (de) 1994-08-25
GB9018319D0 (en) 1990-10-03
GB2236119B (en) 1994-05-25
IT1246685B (it) 1994-11-25
JPH03138926A (ja) 1991-06-13
GB2236119A (en) 1991-03-27
IT9021494A1 (it) 1992-03-17
DE4029826A1 (de) 1991-04-04
ATA192490A (de) 1993-12-15
US4925812A (en) 1990-05-15

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee