DE2615754C2 - - Google Patents
Info
- Publication number
- DE2615754C2 DE2615754C2 DE2615754A DE2615754A DE2615754C2 DE 2615754 C2 DE2615754 C2 DE 2615754C2 DE 2615754 A DE2615754 A DE 2615754A DE 2615754 A DE2615754 A DE 2615754A DE 2615754 C2 DE2615754 C2 DE 2615754C2
- Authority
- DE
- Germany
- Prior art keywords
- substrate
- silicon nitride
- mask
- openings
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
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- H10P14/61—
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- H10P32/12—
-
- H10P32/171—
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- H10P76/40—
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- H10W10/0121—
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- H10W10/13—
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- H10P14/6309—
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- H10P14/6322—
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- H10P14/6329—
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- H10P14/6334—
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- H10P14/69215—
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- H10P14/69391—
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- H10P14/69433—
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/085—Isolated-integrated
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/117—Oxidation, selective
Landscapes
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US05/568,546 US4002511A (en) | 1975-04-16 | 1975-04-16 | Method for forming masks comprising silicon nitride and novel mask structures produced thereby |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE2615754A1 DE2615754A1 (de) | 1976-10-28 |
| DE2615754C2 true DE2615754C2 (enExample) | 1987-06-04 |
Family
ID=24271733
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE19762615754 Granted DE2615754A1 (de) | 1975-04-16 | 1976-04-10 | Aus einem substrat und einer maske gebildete struktur und verfahren zu ihrer herstellung |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US4002511A (enExample) |
| JP (1) | JPS5836499B2 (enExample) |
| DE (1) | DE2615754A1 (enExample) |
| FR (1) | FR2308201A1 (enExample) |
| GB (1) | GB1517242A (enExample) |
| IT (1) | IT1058402B (enExample) |
Families Citing this family (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5246784A (en) * | 1975-10-11 | 1977-04-13 | Hitachi Ltd | Process for production of semiconductor device |
| JPS5253679A (en) * | 1975-10-29 | 1977-04-30 | Hitachi Ltd | Productin of semiconductor device |
| JPS5275989A (en) | 1975-12-22 | 1977-06-25 | Hitachi Ltd | Production of semiconductor device |
| IT1089299B (it) * | 1977-01-26 | 1985-06-18 | Mostek Corp | Procedimento per fabbricare un dispositivo semiconduttore |
| US4118250A (en) * | 1977-12-30 | 1978-10-03 | International Business Machines Corporation | Process for producing integrated circuit devices by ion implantation |
| DE2917654A1 (de) * | 1979-05-02 | 1980-11-13 | Ibm Deutschland | Anordnung und verfahren zum selektiven, elektrochemischen aetzen |
| US4462846A (en) * | 1979-10-10 | 1984-07-31 | Varshney Ramesh C | Semiconductor structure for recessed isolation oxide |
| US4272308A (en) * | 1979-10-10 | 1981-06-09 | Varshney Ramesh C | Method of forming recessed isolation oxide layers |
| US4271583A (en) * | 1980-03-10 | 1981-06-09 | Bell Telephone Laboratories, Incorporated | Fabrication of semiconductor devices having planar recessed oxide isolation region |
| JPS56140643A (en) * | 1980-04-01 | 1981-11-04 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| US4381956A (en) * | 1981-04-06 | 1983-05-03 | Motorola, Inc. | Self-aligned buried channel fabrication process |
| US4506435A (en) * | 1981-07-27 | 1985-03-26 | International Business Machines Corporation | Method for forming recessed isolated regions |
| US4454647A (en) * | 1981-08-27 | 1984-06-19 | International Business Machines Corporation | Isolation for high density integrated circuits |
| US4454646A (en) * | 1981-08-27 | 1984-06-19 | International Business Machines Corporation | Isolation for high density integrated circuits |
| US4563227A (en) * | 1981-12-08 | 1986-01-07 | Matsushita Electric Industrial Co., Ltd. | Method for manufacturing a semiconductor device |
| US4444605A (en) * | 1982-08-27 | 1984-04-24 | Texas Instruments Incorporated | Planar field oxide for semiconductor devices |
| JPS5955052A (ja) * | 1982-09-24 | 1984-03-29 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
| US4612701A (en) * | 1984-03-12 | 1986-09-23 | Harris Corporation | Method to reduce the height of the bird's head in oxide isolated processes |
| US4691222A (en) * | 1984-03-12 | 1987-09-01 | Harris Corporation | Method to reduce the height of the bird's head in oxide isolated processes |
| JPS6281727A (ja) * | 1985-10-05 | 1987-04-15 | Fujitsu Ltd | 埋込型素子分離溝の形成方法 |
| US6696726B1 (en) * | 2000-08-16 | 2004-02-24 | Fairchild Semiconductor Corporation | Vertical MOSFET with ultra-low resistance and low gate charge |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1205320A (en) * | 1967-10-28 | 1970-09-16 | Nippon Telegraph & Telephone | Improvements in or relating to the production of semiconductor devices |
| GB1255995A (en) * | 1968-03-04 | 1971-12-08 | Hitachi Ltd | Semiconductor device and method of making same |
| FR2024124A1 (enExample) * | 1968-11-25 | 1970-08-28 | Ibm | |
| US3664896A (en) * | 1969-07-28 | 1972-05-23 | David M Duncan | Deposited silicon diffusion sources |
| NL173110C (nl) * | 1971-03-17 | 1983-12-01 | Philips Nv | Werkwijze ter vervaardiging van een halfgeleiderinrichting, waarbij op een oppervlak van een halfgeleiderlichaam een uit ten minste twee deellagen van verschillend materiaal samengestelde maskeringslaag wordt aangebracht. |
| US3771218A (en) * | 1972-07-13 | 1973-11-13 | Ibm | Process for fabricating passivated transistors |
| US3966501A (en) * | 1973-03-23 | 1976-06-29 | Mitsubishi Denki Kabushiki Kaisha | Process of producing semiconductor devices |
-
1975
- 1975-04-16 US US05/568,546 patent/US4002511A/en not_active Expired - Lifetime
-
1976
- 1976-02-17 FR FR7605145A patent/FR2308201A1/fr active Granted
- 1976-03-01 GB GB8011/76A patent/GB1517242A/en not_active Expired
- 1976-03-02 JP JP51021887A patent/JPS5836499B2/ja not_active Expired
- 1976-03-12 IT IT21140/76A patent/IT1058402B/it active
- 1976-04-10 DE DE19762615754 patent/DE2615754A1/de active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| IT1058402B (it) | 1982-04-10 |
| DE2615754A1 (de) | 1976-10-28 |
| JPS5836499B2 (ja) | 1983-08-09 |
| GB1517242A (en) | 1978-07-12 |
| US4002511A (en) | 1977-01-11 |
| JPS51124381A (en) | 1976-10-29 |
| FR2308201A1 (fr) | 1976-11-12 |
| FR2308201B1 (enExample) | 1980-05-30 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8110 | Request for examination paragraph 44 | ||
| 8125 | Change of the main classification |
Ipc: H01L 21/314 |
|
| D2 | Grant after examination | ||
| 8364 | No opposition during term of opposition | ||
| 8339 | Ceased/non-payment of the annual fee |