DE3705875C2 - - Google Patents

Info

Publication number
DE3705875C2
DE3705875C2 DE3705875A DE3705875A DE3705875C2 DE 3705875 C2 DE3705875 C2 DE 3705875C2 DE 3705875 A DE3705875 A DE 3705875A DE 3705875 A DE3705875 A DE 3705875A DE 3705875 C2 DE3705875 C2 DE 3705875C2
Authority
DE
Germany
Prior art keywords
dummy
voltage
circuit
lines
bit line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE3705875A
Other languages
German (de)
English (en)
Other versions
DE3705875A1 (de
Inventor
Youichi Itami Hyogo Jp Tobita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE3705875A1 publication Critical patent/DE3705875A1/de
Application granted granted Critical
Publication of DE3705875C2 publication Critical patent/DE3705875C2/de
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4099—Dummy cell treatment; Reference voltage generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Read Only Memory (AREA)
DE19873705875 1986-02-25 1987-02-24 Halbleiterspeicherschaltung Granted DE3705875A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61039390A JPS62197990A (ja) 1986-02-25 1986-02-25 半導体記憶回路

Publications (2)

Publication Number Publication Date
DE3705875A1 DE3705875A1 (de) 1987-08-27
DE3705875C2 true DE3705875C2 (en, 2012) 1990-09-27

Family

ID=12551676

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19873705875 Granted DE3705875A1 (de) 1986-02-25 1987-02-24 Halbleiterspeicherschaltung

Country Status (4)

Country Link
US (1) US4792928A (en, 2012)
JP (1) JPS62197990A (en, 2012)
KR (1) KR900002666B1 (en, 2012)
DE (1) DE3705875A1 (en, 2012)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10216607B4 (de) * 2001-11-02 2010-01-21 Hynix Semiconductor Inc., Icheon Halbleiterspeichervorrichtung

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0682520B2 (ja) * 1987-07-31 1994-10-19 株式会社東芝 半導体メモリ
JPH0194592A (ja) * 1987-10-06 1989-04-13 Fujitsu Ltd 半導体メモリ
JPH07107798B2 (ja) * 1987-11-18 1995-11-15 三菱電機株式会社 ダイナミックランダムアクセスメモリにおけるセンスアンプ駆動装置およびセンスアンプ駆動方法
JP2691280B2 (ja) * 1988-05-12 1997-12-17 三菱電機株式会社 半導体記憶装置
US4975877A (en) * 1988-10-20 1990-12-04 Logic Devices Incorporated Static semiconductor memory with improved write recovery and column address circuitry
US5185721A (en) * 1988-10-31 1993-02-09 Texas Instruments Incorporated Charge-retaining signal boosting circuit and method
JPH02201797A (ja) * 1989-01-31 1990-08-09 Toshiba Corp 半導体メモリ装置
US5093654A (en) * 1989-05-17 1992-03-03 Eldec Corporation Thin-film electroluminescent display power supply system for providing regulated write voltages
KR940007000B1 (ko) * 1991-05-24 1994-08-03 삼성전자 주식회사 개선된 라이트 동작을 가지는 반도체 메모리 장치
US5339274A (en) * 1992-10-30 1994-08-16 International Business Machines Corporation Variable bitline precharge voltage sensing technique for DRAM structures
JPH0757475A (ja) * 1993-08-09 1995-03-03 Nec Corp 半導体メモリ集積回路装置
US5465232A (en) * 1994-07-15 1995-11-07 Micron Semiconductor, Inc. Sense circuit for tracking charge transfer through access transistors in a dynamic random access memory
DE69633774D1 (de) * 1996-03-29 2004-12-09 St Microelectronics Srl Referenzwortleitung und Datenlaufzeitwiedergabeschaltung, insbesondere für nichtflüssige Speicher mit hierarchischen Dekodern
US6626901B1 (en) * 1997-03-05 2003-09-30 The Trustees Of Columbia University In The City Of New York Electrothermal instrument for sealing and joining or cutting tissue
JP3327250B2 (ja) 1999-05-14 2002-09-24 日本電気株式会社 半導体記憶装置
US7746717B1 (en) 2007-09-07 2010-06-29 Xilinx, Inc. Desensitizing static random access memory (SRAM) to process variation
US9236102B2 (en) 2012-10-12 2016-01-12 Micron Technology, Inc. Apparatuses, circuits, and methods for biasing signal lines
US9042190B2 (en) 2013-02-25 2015-05-26 Micron Technology, Inc. Apparatuses, sense circuits, and methods for compensating for a wordline voltage increase
US9672875B2 (en) 2014-01-27 2017-06-06 Micron Technology, Inc. Methods and apparatuses for providing a program voltage responsive to a voltage determination
KR102395535B1 (ko) * 2017-11-20 2022-05-10 에스케이하이닉스 주식회사 테스트 회로 블록, 이를 포함하는 저항 변화 메모리 장치 및 저항 변화 메모리 장치의 형성방법

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3962686A (en) * 1972-05-16 1976-06-08 Nippon Electric Company Limited Memory circuit
US4247917A (en) * 1979-08-27 1981-01-27 Intel Corporation MOS Random-access memory
JPS5942399B2 (ja) * 1979-12-21 1984-10-15 株式会社日立製作所 メモリ装置
US4342102A (en) * 1980-06-18 1982-07-27 Signetics Corporation Semiconductor memory array
US4363111A (en) * 1980-10-06 1982-12-07 Heightley John D Dummy cell arrangement for an MOS memory
JPS5838873B2 (ja) * 1980-10-15 1983-08-25 富士通株式会社 センス回路
JPS601712B2 (ja) * 1980-12-04 1985-01-17 株式会社東芝 半導体記憶装置
US4393475A (en) * 1981-01-27 1983-07-12 Texas Instruments Incorporated Non-volatile semiconductor memory and the testing method for the same
JPS57127989A (en) * 1981-02-02 1982-08-09 Hitachi Ltd Mos static type ram
JPS57195387A (en) * 1981-05-27 1982-12-01 Hitachi Ltd Data lien precharging system of memory integrated circuit
JPS5812193A (ja) * 1981-07-15 1983-01-24 Toshiba Corp 半導体メモリ
JPS5856287A (ja) * 1981-09-29 1983-04-02 Nec Corp 半導体回路
JPS58111183A (ja) * 1981-12-25 1983-07-02 Hitachi Ltd ダイナミツクｒａｍ集積回路装置
US4658377A (en) * 1984-07-26 1987-04-14 Texas Instruments Incorporated Dynamic memory array with segmented bit lines

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10216607B4 (de) * 2001-11-02 2010-01-21 Hynix Semiconductor Inc., Icheon Halbleiterspeichervorrichtung

Also Published As

Publication number Publication date
KR900002666B1 (ko) 1990-04-21
JPH0568798B2 (en, 2012) 1993-09-29
US4792928A (en) 1988-12-20
DE3705875A1 (de) 1987-08-27
KR870008319A (ko) 1987-09-25
JPS62197990A (ja) 1987-09-01

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8125 Change of the main classification

Ipc: G11C 7/00

D2 Grant after examination
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee