DE3672450D1 - Verfahren zur herstellung einer halbleiteranordnung mittels einer implantationsmaske. - Google Patents

Verfahren zur herstellung einer halbleiteranordnung mittels einer implantationsmaske.

Info

Publication number
DE3672450D1
DE3672450D1 DE8686201737T DE3672450T DE3672450D1 DE 3672450 D1 DE3672450 D1 DE 3672450D1 DE 8686201737 T DE8686201737 T DE 8686201737T DE 3672450 T DE3672450 T DE 3672450T DE 3672450 D1 DE3672450 D1 DE 3672450D1
Authority
DE
Germany
Prior art keywords
producing
implantation mask
semiconductor arrangement
semiconductor
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8686201737T
Other languages
English (en)
Inventor
Hermanus Leonardus Peek
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Application granted granted Critical
Publication of DE3672450D1 publication Critical patent/DE3672450D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Element Separation (AREA)
  • Electrodes Of Semiconductors (AREA)
DE8686201737T 1985-10-10 1986-10-08 Verfahren zur herstellung einer halbleiteranordnung mittels einer implantationsmaske. Expired - Lifetime DE3672450D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL8502765A NL8502765A (nl) 1985-10-10 1985-10-10 Werkwijze ter vervaardiging van een halfgeleiderinrichting.

Publications (1)

Publication Number Publication Date
DE3672450D1 true DE3672450D1 (de) 1990-08-09

Family

ID=19846694

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686201737T Expired - Lifetime DE3672450D1 (de) 1985-10-10 1986-10-08 Verfahren zur herstellung einer halbleiteranordnung mittels einer implantationsmaske.

Country Status (6)

Country Link
US (1) US4756793A (de)
EP (1) EP0221593B1 (de)
JP (1) JPH0732144B2 (de)
CA (1) CA1252915A (de)
DE (1) DE3672450D1 (de)
NL (1) NL8502765A (de)

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US5057444A (en) * 1985-03-05 1991-10-15 Matsushita Electric Industrial Co., Ltd. Method of fabricating semiconductor device
JPS61202426A (ja) * 1985-03-05 1986-09-08 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPH0620108B2 (ja) * 1987-03-23 1994-03-16 三菱電機株式会社 半導体装置の製造方法
US5086297A (en) * 1988-06-14 1992-02-04 Dai Nippon Insatsu Kabushiki Kaisha Plasma display panel and method of forming fluorescent screen thereof
US5108938A (en) * 1989-03-21 1992-04-28 Grumman Aerospace Corporation Method of making a trench gate complimentary metal oxide semiconductor transistor
WO1990011616A1 (en) * 1989-03-21 1990-10-04 Grumman Aerospace Corporation Trench gate complimentary metal oxide semiconductor transistor
US5021355A (en) * 1989-05-22 1991-06-04 International Business Machines Corporation Method of fabricating cross-point lightly-doped drain-source trench transistor
JPH0834194B2 (ja) * 1989-06-30 1996-03-29 松下電器産業株式会社 イオン注入方法及び本方法を用いた半導体装置の製造方法
DE69220846T2 (de) * 1991-05-03 1998-02-12 Philips Electronics Nv Verfahren zur Herstellung eines Halbleiterbauelements mit Ionenimplantierung
US5391506A (en) * 1992-01-31 1995-02-21 Kawasaki Steel Corporation Manufacturing method for semiconductor devices with source/drain formed in substrate projection.
CA2097388A1 (en) * 1992-07-16 1994-01-17 Susan Nord Bohlke Topographical selective patterns
US5240875A (en) * 1992-08-12 1993-08-31 North American Philips Corporation Selective oxidation of silicon trench sidewall
US5290358A (en) * 1992-09-30 1994-03-01 International Business Machines Corporation Apparatus for directional low pressure chemical vapor deposition (DLPCVD)
TW403972B (en) * 1993-01-18 2000-09-01 Semiconductor Energy Lab Method of fabricating mis semiconductor device
US5444007A (en) * 1994-08-03 1995-08-22 Kabushiki Kaisha Toshiba Formation of trenches having different profiles
JP3155894B2 (ja) * 1994-09-29 2001-04-16 株式会社東芝 半導体装置およびその製造方法
GB9512089D0 (en) * 1995-06-14 1995-08-09 Evans Jonathan L Semiconductor device fabrication
KR0165457B1 (ko) * 1995-10-25 1999-02-01 김광호 트렌치 소자분리 방법
DE19640235C2 (de) * 1996-09-30 2001-10-25 Infineon Technologies Ag Halbleiter-Festwertspeicher mit in Grabenseitenwänden vertikal verlaufenden Transistoren und Verfahren zu seiner Herstellung
GB2323703B (en) * 1997-03-13 2002-02-13 United Microelectronics Corp Method to inhibit the formation of ion implantation induced edge defects
DE19742397C2 (de) * 1997-09-25 2000-07-06 Siemens Ag Verfahren zur Herstellung einer Halbleiterstruktur mit einer Mehrzahl von Gräben
US5915195A (en) * 1997-11-25 1999-06-22 Advanced Micro Devices, Inc. Ion implantation process to improve the gate oxide quality at the edge of a shallow trench isolation structure
US6221680B1 (en) 1998-07-31 2001-04-24 International Business Machines Corporation Patterned recess formation using acid diffusion
US6440638B2 (en) 1998-09-28 2002-08-27 International Business Machines Corp. Method and apparatus for resist planarization
US6316806B1 (en) * 1999-03-31 2001-11-13 Fairfield Semiconductor Corporation Trench transistor with a self-aligned source
DE10131704A1 (de) 2001-06-29 2003-01-16 Atmel Germany Gmbh Verfahren zur Dotierung eines Halbleiterkörpers
DE10131706B4 (de) * 2001-06-29 2005-10-06 Atmel Germany Gmbh Verfahren zur Herstellung eines DMOS-Transistors
DE10131707B4 (de) * 2001-06-29 2009-12-03 Atmel Automotive Gmbh Verfahren zur Herstellung eines DMOS-Transistors und dessen Verwendung zur Herstellung einer integrierten Schaltung
DE10131705B4 (de) 2001-06-29 2010-03-18 Atmel Automotive Gmbh Verfahren zur Herstellung eines DMOS-Transistors
KR20030002947A (ko) * 2001-07-03 2003-01-09 엘지전자 주식회사 풀칼라 유기 ｅｌ 표시소자 및 제조방법
DE10345347A1 (de) * 2003-09-19 2005-04-14 Atmel Germany Gmbh Verfahren zur Herstellung eines DMOS-Transistors mit lateralem Driftregionen-Dotierstoffprofil
JP4928947B2 (ja) * 2003-12-19 2012-05-09 サード ディメンジョン （スリーディ） セミコンダクタ インコーポレイテッド 超接合デバイスの製造方法
DE102004037153B4 (de) * 2004-07-30 2011-09-15 Infineon Technologies Ag Verfahren zum Herstellen eines Leistungshalbleiterbauteils
US20090026581A1 (en) * 2007-07-25 2009-01-29 Jin-Ha Park Flash memory device and method of manufacturing the same
DE102007035251B3 (de) * 2007-07-27 2008-08-28 X-Fab Semiconductor Foundries Ag Verfahren zur Herstellung von Isolationsgräben mit unterschiedlichen Seitenwanddotierungen
TWI501419B (zh) * 2011-08-23 2015-09-21 Lextar Electronics Corp 發光二極體與其形成方法
CN109980003B (zh) * 2017-12-27 2022-02-15 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
US10522549B2 (en) * 2018-02-17 2019-12-31 Varian Semiconductor Equipment Associates, Inc. Uniform gate dielectric for DRAM device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2341154C2 (de) * 1973-08-14 1975-06-26 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zur Herstellung einer Zweiphasen-Ladungsverschiebeanordnung
JPS51105821A (en) * 1975-03-14 1976-09-20 Fuji Photo Film Co Ltd Masukugazono keiseihoho
US4140558A (en) * 1978-03-02 1979-02-20 Bell Telephone Laboratories, Incorporated Isolation of integrated circuits utilizing selective etching and diffusion
US4335501A (en) * 1979-10-31 1982-06-22 The General Electric Company Limited Manufacture of monolithic LED arrays for electroluminescent display devices
US4254428A (en) * 1979-12-28 1981-03-03 International Business Machines Corporation Self-aligned Schottky diode structure and method of fabrication
US4584762A (en) * 1981-03-02 1986-04-29 Rockwell International Corporation Lateral transistor separated from substrate by intersecting slots filled with substrate oxide for minimal interference therefrom and method for producing same
US4611387A (en) * 1981-03-02 1986-09-16 Rockwell International Corporation Process for producing NPN type lateral transistors
US4437226A (en) * 1981-03-02 1984-03-20 Rockwell International Corporation Process for producing NPN type lateral transistor with minimal substrate operation interference
US4466178A (en) * 1981-06-25 1984-08-21 Rockwell International Corporation Method of making extremely small area PNP lateral transistor by angled implant of deep trenches followed by refilling the same with dielectrics
US4580331A (en) * 1981-07-01 1986-04-08 Rockwell International Corporation PNP-type lateral transistor with minimal substrate operation interference and method for producing same
US4534824A (en) * 1984-04-16 1985-08-13 Advanced Micro Devices, Inc. Process for forming isolation slots having immunity to surface inversion
FR2566179B1 (fr) * 1984-06-14 1986-08-22 Commissariat Energie Atomique Procede d'autopositionnement d'un oxyde de champ localise par rapport a une tranchee d'isolement
US4549927A (en) * 1984-06-29 1985-10-29 International Business Machines Corporation Method of selectively exposing the sidewalls of a trench and its use to the forming of a metal silicide substrate contact for dielectric filled deep trench isolated devices
US4702795A (en) * 1985-05-03 1987-10-27 Texas Instruments Incorporated Trench etch process

Also Published As

Publication number Publication date
US4756793A (en) 1988-07-12
CA1252915A (en) 1989-04-18
EP0221593A1 (de) 1987-05-13
JPH0732144B2 (ja) 1995-04-10
NL8502765A (nl) 1987-05-04
JPS6293930A (ja) 1987-04-30
EP0221593B1 (de) 1990-07-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PHILIPS ELECTRONICS N.V., EINDHOVEN, NL

8339 Ceased/non-payment of the annual fee