DE69220846T2 - Verfahren zur Herstellung eines Halbleiterbauelements mit Ionenimplantierung - Google Patents

Verfahren zur Herstellung eines Halbleiterbauelements mit Ionenimplantierung

Info

Publication number
DE69220846T2
DE69220846T2 DE69220846T DE69220846T DE69220846T2 DE 69220846 T2 DE69220846 T2 DE 69220846T2 DE 69220846 T DE69220846 T DE 69220846T DE 69220846 T DE69220846 T DE 69220846T DE 69220846 T2 DE69220846 T2 DE 69220846T2
Authority
DE
Germany
Prior art keywords
manufacturing
semiconductor device
ion implantation
implantation
ion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69220846T
Other languages
English (en)
Other versions
DE69220846D1 (de
Inventor
Hermanus Leonardus Peek
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Electronics NV filed Critical Philips Electronics NV
Application granted granted Critical
Publication of DE69220846D1 publication Critical patent/DE69220846D1/de
Publication of DE69220846T2 publication Critical patent/DE69220846T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66946—Charge transfer devices
    • H01L29/66954—Charge transfer devices with an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
    • Y10S438/949—Energy beam treating radiation resist on semiconductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Element Separation (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Drying Of Semiconductors (AREA)
DE69220846T 1991-05-03 1992-04-24 Verfahren zur Herstellung eines Halbleiterbauelements mit Ionenimplantierung Expired - Fee Related DE69220846T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP91201052 1991-05-03

Publications (2)

Publication Number Publication Date
DE69220846D1 DE69220846D1 (de) 1997-08-21
DE69220846T2 true DE69220846T2 (de) 1998-02-12

Family

ID=8207635

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69220846T Expired - Fee Related DE69220846T2 (de) 1991-05-03 1992-04-24 Verfahren zur Herstellung eines Halbleiterbauelements mit Ionenimplantierung

Country Status (7)

Country Link
US (1) US5306390A (de)
EP (1) EP0512607B1 (de)
JP (1) JP3242446B2 (de)
KR (1) KR100256454B1 (de)
CN (1) CN1029273C (de)
DE (1) DE69220846T2 (de)
PL (1) PL168460B1 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2611728B2 (ja) * 1993-11-02 1997-05-21 日本電気株式会社 動画像符号化復号化方式
JP3979661B2 (ja) * 1994-04-15 2007-09-19 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 半導体素子と電気的に接触する導体パターンを設けた支持バーによる装置の製造方法
US5668018A (en) * 1995-06-07 1997-09-16 International Business Machines Corporation Method for defining a region on a wall of a semiconductor structure
US6440638B2 (en) 1998-09-28 2002-08-27 International Business Machines Corp. Method and apparatus for resist planarization
US6100172A (en) * 1998-10-29 2000-08-08 International Business Machines Corporation Method for forming a horizontal surface spacer and devices formed thereby
US6096598A (en) * 1998-10-29 2000-08-01 International Business Machines Corporation Method for forming pillar memory cells and device formed thereby
US6194268B1 (en) 1998-10-30 2001-02-27 International Business Machines Corporation Printing sublithographic images using a shadow mandrel and off-axis exposure
US6150256A (en) * 1998-10-30 2000-11-21 International Business Machines Corporation Method for forming self-aligned features
TW523860B (en) * 2002-03-22 2003-03-11 Nanya Technology Corp Manufacturing method for lower electrode plate of capacitors in memory
US6780736B1 (en) * 2003-06-20 2004-08-24 International Business Machines Corporation Method for image reversal of implant resist using a single photolithography exposure and structures formed thereby
US7041560B2 (en) 2003-12-19 2006-05-09 Third Dimension (3D) Semiconductor, Inc. Method of manufacturing a superjunction device with conventional terminations
WO2005060676A2 (en) * 2003-12-19 2005-07-07 Third Dimension (3D) Semiconductor, Inc. A method for manufacturing a superjunction device with wide mesas
KR101983672B1 (ko) 2012-11-07 2019-05-30 삼성전자 주식회사 반도체 장치의 제조 방법
CN103896204A (zh) * 2012-12-25 2014-07-02 上海华虹宏力半导体制造有限公司 沟槽中的成膜工艺方法
US10854455B2 (en) * 2016-11-21 2020-12-01 Marvell Asia Pte, Ltd. Methods and apparatus for fabricating IC chips with tilted patterning

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4466180A (en) * 1981-06-25 1984-08-21 Rockwell International Corporation Method of manufacturing punch through voltage regulator diodes utilizing shaping and selective doping
US4466178A (en) * 1981-06-25 1984-08-21 Rockwell International Corporation Method of making extremely small area PNP lateral transistor by angled implant of deep trenches followed by refilling the same with dielectrics
EP0069191A1 (de) * 1981-06-25 1983-01-12 Rockwell International Corporation Komplementäre NPN- und PNP- Lateraltransistoren, die zur minimalen Beeinflussung durch mit Substratoxyd gefüllte, sich kreuzende Rillen vom Substrat getrennt sind, und Verfahren zu ihrer Herstellung
NL8502765A (nl) * 1985-10-10 1987-05-04 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting.
NL8600786A (nl) * 1986-03-27 1987-10-16 Philips Nv Ladingsgekoppelde inrichting.
US4693781A (en) * 1986-06-26 1987-09-15 Motorola, Inc. Trench formation process

Also Published As

Publication number Publication date
KR920022559A (ko) 1992-12-19
EP0512607A3 (en) 1993-09-08
KR100256454B1 (ko) 2000-05-15
PL294400A1 (en) 1992-11-16
JP3242446B2 (ja) 2001-12-25
CN1029273C (zh) 1995-07-05
EP0512607A2 (de) 1992-11-11
EP0512607B1 (de) 1997-07-16
CN1066530A (zh) 1992-11-25
US5306390A (en) 1994-04-26
JPH0620983A (ja) 1994-01-28
DE69220846D1 (de) 1997-08-21
PL168460B1 (pl) 1996-02-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: KONINKLIJKE PHILIPS ELECTRONICS N.V., EINDHOVEN, N

8339 Ceased/non-payment of the annual fee