KR920022559A - 반도체 소자 제조방법 및 이에 따라 제조된 반도체 소자 - Google Patents

반도체 소자 제조방법 및 이에 따라 제조된 반도체 소자 Download PDF

Info

Publication number
KR920022559A
KR920022559A KR1019920007368A KR920007368A KR920022559A KR 920022559 A KR920022559 A KR 920022559A KR 1019920007368 A KR1019920007368 A KR 1019920007368A KR 920007368 A KR920007368 A KR 920007368A KR 920022559 A KR920022559 A KR 920022559A
Authority
KR
South Korea
Prior art keywords
photoresist layer
semiconductor device
irradiation
providing
region
Prior art date
Application number
KR1019920007368A
Other languages
English (en)
Other versions
KR100256454B1 (ko
Inventor
레오나르두스 페크 헤르마누스
Original Assignee
프레데릭 얀 스미트
엔.브이.필립스 글로아이람펜파브리켄
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 프레데릭 얀 스미트, 엔.브이.필립스 글로아이람펜파브리켄 filed Critical 프레데릭 얀 스미트
Publication of KR920022559A publication Critical patent/KR920022559A/ko
Application granted granted Critical
Publication of KR100256454B1 publication Critical patent/KR100256454B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66946—Charge transfer devices
    • H01L29/66954—Charge transfer devices with an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
    • Y10S438/949—Energy beam treating radiation resist on semiconductor

Abstract

내용 없음.

Description

반도체 소자 제조방법 및 이에 따라 제조된 반도체 소자
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1내지 7도는 본 발명의 실시태양을 여러 공정단계로 도시한 도면.
제8도는 본 발명에 따른 방법에 의해 제조된 소자의 평면도 및 단면도.

Claims (6)

  1. 반도체 몸체의 표면에 상기 표면으로부터 상기 반도체 몸체내로 연장하는 적어도 하나의 홈을 제공하고, 마스크를 통한 이온주입에 의해 상기 홈의 일부분에 불순물로 도핑된 영역을 제공하는 반도체 소자 제조방법에 있어서, 포지티브 포토레지스트층을 상기 표면상 및 상기 홈내에 제공하고, 이온주입을 행할 영역의 포토레지스트층부분을 조사에 대해 마스킹하고 마스킹하지 않은 포토레지스트층 부분을 1차 조사한 후에 조사된 포토레지스트층 부분을 상반전처리에 의해 불용성으로 되게 하며. 이온주입을 행할 영역에서 상기 포토레지스트층에 대한 2차조사를 행한 후에 상기 1차 조사시에 마스킹되었던 상기 포토 레지스트층 부분을 현상에 의해 제거하는 것을 특징으로 하는 반도체 제조방법.
  2. 제1항에 있어서, 상기 2차 조사는 상기 1차 조사보다 조사량이 더 큰 것을 특징으로 하는 반도체 제조방법.
  3. 제1 또는 2항에 있어서, 상기 도핑된 영역은 상기 표면에 대해 90°미만의 각도로 이온주입을 행함으로써 상기 홈의 벽에 제공되는 것을 특징으로 하는 반도체 제조방법.
  4. 선행항들 중의 어느 한 항에 있어서, 상기 표면 및 상기 홈의 벽은 상기 포토레지스트층의 제공전에 절연층으로 덮혀지는 것을 특징으로 하는 반도체 소자 제조방법.
  5. 선행항들 중의 어느 한 항에 있어서, 상기 도핑된 영역은 반도체 회로요소의 일부를 구성하는 것을 특징으로 하는 방법.
  6. 선행항들 중의 어느 한 항에 따른 방법으로 제조된 반도체 소자.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920007368A 1991-05-03 1992-04-30 반도체장치 제조방법 KR100256454B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
NL91201052.7 1991-05-03
EP91201052 1991-05-03
EP91201052.7 1991-05-03

Publications (2)

Publication Number Publication Date
KR920022559A true KR920022559A (ko) 1992-12-19
KR100256454B1 KR100256454B1 (ko) 2000-05-15

Family

ID=8207635

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920007368A KR100256454B1 (ko) 1991-05-03 1992-04-30 반도체장치 제조방법

Country Status (7)

Country Link
US (1) US5306390A (ko)
EP (1) EP0512607B1 (ko)
JP (1) JP3242446B2 (ko)
KR (1) KR100256454B1 (ko)
CN (1) CN1029273C (ko)
DE (1) DE69220846T2 (ko)
PL (1) PL168460B1 (ko)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2611728B2 (ja) * 1993-11-02 1997-05-21 日本電気株式会社 動画像符号化復号化方式
KR100335546B1 (ko) * 1994-04-15 2002-10-11 코닌클리케 필립스 일렉트로닉스 엔.브이. 지지바에 기초한 반도체 디바이스 제조 방법
US5668018A (en) * 1995-06-07 1997-09-16 International Business Machines Corporation Method for defining a region on a wall of a semiconductor structure
US6440638B2 (en) 1998-09-28 2002-08-27 International Business Machines Corp. Method and apparatus for resist planarization
US6100172A (en) * 1998-10-29 2000-08-08 International Business Machines Corporation Method for forming a horizontal surface spacer and devices formed thereby
US6096598A (en) * 1998-10-29 2000-08-01 International Business Machines Corporation Method for forming pillar memory cells and device formed thereby
US6194268B1 (en) 1998-10-30 2001-02-27 International Business Machines Corporation Printing sublithographic images using a shadow mandrel and off-axis exposure
US6150256A (en) * 1998-10-30 2000-11-21 International Business Machines Corporation Method for forming self-aligned features
TW523860B (en) * 2002-03-22 2003-03-11 Nanya Technology Corp Manufacturing method for lower electrode plate of capacitors in memory
US6780736B1 (en) * 2003-06-20 2004-08-24 International Business Machines Corporation Method for image reversal of implant resist using a single photolithography exposure and structures formed thereby
KR20080100265A (ko) * 2003-12-19 2008-11-14 써드 디멘존 세미컨덕터, 인코포레이티드 종래의 종단을 갖는 수퍼 접합 장치를 제조하는 방법
WO2005060676A2 (en) * 2003-12-19 2005-07-07 Third Dimension (3D) Semiconductor, Inc. A method for manufacturing a superjunction device with wide mesas
KR101983672B1 (ko) 2012-11-07 2019-05-30 삼성전자 주식회사 반도체 장치의 제조 방법
CN103896204A (zh) * 2012-12-25 2014-07-02 上海华虹宏力半导体制造有限公司 沟槽中的成膜工艺方法
US10854455B2 (en) * 2016-11-21 2020-12-01 Marvell Asia Pte, Ltd. Methods and apparatus for fabricating IC chips with tilted patterning

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0069191A1 (en) * 1981-06-25 1983-01-12 Rockwell International Corporation Complementary NPN and PNP lateral transistors separated from substrate by intersecting slots filled with substrate oxide for minimal interference therefrom and method for producing same
US4466180A (en) * 1981-06-25 1984-08-21 Rockwell International Corporation Method of manufacturing punch through voltage regulator diodes utilizing shaping and selective doping
US4466178A (en) * 1981-06-25 1984-08-21 Rockwell International Corporation Method of making extremely small area PNP lateral transistor by angled implant of deep trenches followed by refilling the same with dielectrics
NL8502765A (nl) * 1985-10-10 1987-05-04 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting.
NL8600786A (nl) * 1986-03-27 1987-10-16 Philips Nv Ladingsgekoppelde inrichting.
US4693781A (en) * 1986-06-26 1987-09-15 Motorola, Inc. Trench formation process

Also Published As

Publication number Publication date
EP0512607A2 (en) 1992-11-11
PL294400A1 (en) 1992-11-16
CN1066530A (zh) 1992-11-25
JP3242446B2 (ja) 2001-12-25
DE69220846D1 (de) 1997-08-21
KR100256454B1 (ko) 2000-05-15
PL168460B1 (pl) 1996-02-29
EP0512607A3 (en) 1993-09-08
EP0512607B1 (en) 1997-07-16
JPH0620983A (ja) 1994-01-28
US5306390A (en) 1994-04-26
CN1029273C (zh) 1995-07-05
DE69220846T2 (de) 1998-02-12

Similar Documents

Publication Publication Date Title
KR920022559A (ko) 반도체 소자 제조방법 및 이에 따라 제조된 반도체 소자
KR920017245A (ko) 반도체장치와 그의 제조방법
KR870005476A (ko) Mos트랜지스터의 제조방법
KR890003028A (ko) 고저항 다결정 실리콘의 제조방법
SE7702443L (sv) Metod vid tillverkning av integrerade kretsar for jonimplantation i ett halvledarsubstrat
KR960024604A (ko) 이중 채널 박막트랜지스터 및 그 제조방법
KR970018187A (ko) 반도체 장치 제조방법
KR950012603A (ko) 반도체 소자 제조 방법
KR960026459A (ko) 트랜지스터 제조방법
KR910001943A (ko) 바이포울러 씨모스의 제조방법
KR960026753A (ko) 트윈(twin) 웰 제조방법
KR950012717A (ko) 반도체 소자 제조 방법
JPS56135970A (en) Semiconductor device
KR960026554A (ko) 반도체소자 제조방법
KR940016875A (ko) 반도체 소자의 고부하저항기 제조방법
KR960009015A (ko) 반도체 소자의 게이트 전극 형성방법
KR910017634A (ko) 메모리 셀 커패시터 제조방법
KR970003406A (ko) 반도체장치의 제조방법
KR920010915A (ko) 트렌치 커패시터 셀 제조방법
KR970054208A (ko) 마스크 롬의 제조방법
KR920001757A (ko) 모오스 트랜지스터의 제조방법
KR920005302A (ko) 반도체 장치의 개구형성방법
KR940016695A (ko) 반도체 소자의 콘택트홀 형성방법
KR940010387A (ko) 반도체 소자 제조방법
KR950021566A (ko) 반도체 소자의 캐패시터 제조방법

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
LAPS Lapse due to unpaid annual fee