DE3483466D1 - Verfahren zur herstellung einer halbleiteranordnung mittels einer selektiven dampfphasenanwuchstechnik. - Google Patents

Verfahren zur herstellung einer halbleiteranordnung mittels einer selektiven dampfphasenanwuchstechnik.

Info

Publication number
DE3483466D1
DE3483466D1 DE8484305652T DE3483466T DE3483466D1 DE 3483466 D1 DE3483466 D1 DE 3483466D1 DE 8484305652 T DE8484305652 T DE 8484305652T DE 3483466 T DE3483466 T DE 3483466T DE 3483466 D1 DE3483466 D1 DE 3483466D1
Authority
DE
Germany
Prior art keywords
producing
application technology
phase application
semiconductor arrangement
steam phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8484305652T
Other languages
English (en)
Inventor
Takahiko C O Patent Div Moriya
Saburo C O Patent Divis Nakada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3483466D1 publication Critical patent/DE3483466D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H01L21/28562—Selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/019—Contacts of silicides
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/02—Contacts, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/026—Deposition thru hole in mask

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE8484305652T 1983-08-30 1984-08-20 Verfahren zur herstellung einer halbleiteranordnung mittels einer selektiven dampfphasenanwuchstechnik. Expired - Lifetime DE3483466D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58158713A JPS6050920A (ja) 1983-08-30 1983-08-30 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
DE3483466D1 true DE3483466D1 (de) 1990-11-29

Family

ID=15677724

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484305652T Expired - Lifetime DE3483466D1 (de) 1983-08-30 1984-08-20 Verfahren zur herstellung einer halbleiteranordnung mittels einer selektiven dampfphasenanwuchstechnik.

Country Status (4)

Country Link
US (1) US4597167A (de)
EP (1) EP0147913B1 (de)
JP (1) JPS6050920A (de)
DE (1) DE3483466D1 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61274345A (ja) * 1985-05-29 1986-12-04 Toshiba Corp 半導体装置の製造方法
JPS6231116A (ja) * 1985-08-02 1987-02-10 Toshiba Corp 半導体装置の製造方法
GB2183090B (en) * 1985-10-07 1989-09-13 Canon Kk Method for selective formation of deposited film
US4741928A (en) * 1985-12-27 1988-05-03 General Electric Company Method for selective deposition of tungsten by chemical vapor deposition onto metal and semiconductor surfaces
US5324536A (en) * 1986-04-28 1994-06-28 Canon Kabushiki Kaisha Method of forming a multilayered structure
US4849377A (en) * 1986-05-27 1989-07-18 General Electric Company Active area planarization with self-aligned contacts
JPH0680682B2 (ja) * 1986-06-16 1994-10-12 アメリカン テレフォン アンド テレグラフ カムパニー デバイスの製造法
US4968644A (en) * 1986-06-16 1990-11-06 At&T Bell Laboratories Method for fabricating devices and devices formed thereby
FR2624304B1 (fr) * 1987-12-04 1990-05-04 Philips Nv Procede pour etablir une structure d'interconnexion electrique sur un dispositif semiconducteur au silicium
US5212400A (en) * 1988-02-18 1993-05-18 International Business Machines Corporation Method of depositing tungsten on silicon in a non-self-limiting CVD process and semiconductor device manufactured thereby
US5071788A (en) * 1988-02-18 1991-12-10 International Business Machines Corporation Method for depositing tungsten on silicon in a non-self-limiting CVD process and semiconductor device manufactured thereby
CA1308496C (en) * 1988-02-18 1992-10-06 Rajiv V. Joshi Deposition of tungsten on silicon in a non-self-limiting cvd process
GB2215126B (en) * 1988-02-19 1990-11-14 Gen Electric Co Plc Process for manufacturing a thin film transistor
US5149672A (en) * 1988-08-01 1992-09-22 Nadia Lifshitz Process for fabricating integrated circuits having shallow junctions
US5006476A (en) * 1988-09-07 1991-04-09 North American Philips Corp., Signetics Division Transistor manufacturing process using three-step base doping
US5021363A (en) * 1989-09-07 1991-06-04 Laboratories Incorporated Method of selectively producing conductive members on a semiconductor surface
US5388577A (en) * 1990-06-08 1995-02-14 Boston University Electrode array microchip
GB2253090A (en) * 1991-02-22 1992-08-26 Westinghouse Brake & Signal Electrical contacts for semiconductor devices
US5888890A (en) * 1994-08-12 1999-03-30 Lg Semicon Co., Ltd. Method of manufacturing field effect transistor

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1900119B2 (de) * 1969-01-02 1977-06-30 Siemens AG, 1000 Berlin und 8000 München Verfahren zum abscheiden hochschmelzender kontaktmetallschichten bei niedrigen temperaturen
US3801365A (en) * 1971-08-05 1974-04-02 Energy Conversion Devices Inc Method for producing an electrical device
JPS5099267A (de) * 1973-12-28 1975-08-06
JPS53114350A (en) * 1977-03-16 1978-10-05 Toshiba Corp Semiconductor and its manufacture
US4313971A (en) * 1979-05-29 1982-02-02 Rca Corporation Method of fabricating a Schottky barrier contact
JPS5776833A (en) * 1980-09-04 1982-05-14 Applied Materials Inc Heat resistant metal depositing method and product thereof
US4404235A (en) * 1981-02-23 1983-09-13 Rca Corporation Method for improving adhesion of metal film on a dielectric surface
US4343676A (en) * 1981-03-26 1982-08-10 Rca Corporation Etching a semiconductor material and automatically stopping same
US4349408A (en) * 1981-03-26 1982-09-14 Rca Corporation Method of depositing a refractory metal on a semiconductor substrate
US4517225A (en) * 1983-05-02 1985-05-14 Signetics Corporation Method for manufacturing an electrical interconnection by selective tungsten deposition
US4532702A (en) * 1983-11-04 1985-08-06 Westinghouse Electric Corp. Method of forming conductive interconnection between vertically spaced levels in VLSI devices

Also Published As

Publication number Publication date
US4597167A (en) 1986-07-01
JPS6050920A (ja) 1985-03-22
EP0147913A2 (de) 1985-07-10
EP0147913B1 (de) 1990-10-24
EP0147913A3 (en) 1987-10-14

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8320 Willingness to grant licences declared (paragraph 23)