DE3606406A1 - Konfigurierbares logikelement - Google Patents
Konfigurierbares logikelementInfo
- Publication number
- DE3606406A1 DE3606406A1 DE19863606406 DE3606406A DE3606406A1 DE 3606406 A1 DE3606406 A1 DE 3606406A1 DE 19863606406 DE19863606406 DE 19863606406 DE 3606406 A DE3606406 A DE 3606406A DE 3606406 A1 DE3606406 A1 DE 3606406A1
- Authority
- DE
- Germany
- Prior art keywords
- signals
- configurable
- input
- binary
- logic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000006870 function Effects 0.000 claims description 71
- 230000000295 complement effect Effects 0.000 claims description 4
- 230000001419 dependent effect Effects 0.000 claims 1
- 230000003068 static effect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000000630 rising effect Effects 0.000 description 4
- 101100452680 Arabidopsis thaliana INVC gene Proteins 0.000 description 3
- 101000998711 Homo sapiens Inversin Proteins 0.000 description 2
- 102100033257 Inversin Human genes 0.000 description 2
- 241000030538 Thecla Species 0.000 description 2
- 238000001208 nuclear magnetic resonance pulse sequence Methods 0.000 description 2
- 229930091051 Arenine Natural products 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
- G11C19/282—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements with charge storage in a depletion layer, i.e. charge coupled devices [CCD]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
- H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
- H03K19/1736—Controllable logic circuits by wiring, e.g. uncommitted logic arrays in which the wiring can be modified
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
- H03K5/1534—Transition or edge detectors
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Nonlinear Science (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/706,429 US4706216A (en) | 1985-02-27 | 1985-02-27 | Configurable logic element |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3606406A1 true DE3606406A1 (de) | 1986-08-28 |
Family
ID=24837522
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE19863606406 Granted DE3606406A1 (de) | 1985-02-27 | 1986-02-27 | Konfigurierbares logikelement |
DE3645224A Expired - Lifetime DE3645224C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1985-02-27 | 1986-02-27 | |
DE3645221A Expired - Lifetime DE3645221C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1985-02-27 | 1986-02-27 |
Family Applications After (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE3645224A Expired - Lifetime DE3645224C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1985-02-27 | 1986-02-27 | |
DE3645221A Expired - Lifetime DE3645221C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1985-02-27 | 1986-02-27 |
Country Status (5)
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0324640A3 (en) * | 1988-01-14 | 1991-08-28 | Kawasaki Steel Corporation | Programmable logic device |
EP0420390A3 (en) * | 1989-09-29 | 1991-09-04 | Sgs-Thomson Microelectronics, Inc. (A Delaware Corp.) | Configuration memory for programmable logic device |
EP0476159A1 (en) * | 1990-09-15 | 1992-03-25 | International Business Machines Corporation | Programmable neural logic device |
EP0433757A3 (en) * | 1989-12-19 | 1992-08-26 | Bull Hn Information Systems Inc. | Edge triggered d-type flip-flop scan latch cell with recirculation capability |
DE4327660A1 (de) * | 1992-08-20 | 1994-02-24 | Mitsubishi Electric Corp | Vorrichtung zum Herstellen einer und Herstellungsverfahren für eine integrierte Halbleiterschaltungsvorrichtung und elektronische Schaltungsvorrichtung |
DE9417335U1 (de) * | 1994-10-28 | 1994-12-15 | Bäuerle, Karin, 75181 Pforzheim | Koppelbaustein |
US5999086A (en) * | 1996-09-27 | 1999-12-07 | Siemens Aktiengesellschaft | Circuit arrangement with combinatorial blocks arranged between registers |
US6516334B1 (en) | 1996-09-27 | 2003-02-04 | Siemens Aktiengesellschaft | Circuit arrangement with combinatorial blocks arranged between registers |
Families Citing this family (402)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5151623A (en) * | 1985-03-29 | 1992-09-29 | Advanced Micro Devices, Inc. | Programmable logic device with multiple, flexible asynchronous programmable logic blocks interconnected by a high speed switch matrix |
US5225719A (en) * | 1985-03-29 | 1993-07-06 | Advanced Micro Devices, Inc. | Family of multiple segmented programmable logic blocks interconnected by a high speed centralized switch matrix |
DE3683477D1 (de) * | 1985-07-12 | 1992-02-27 | Anamartic Ltd | Scheibenbereichsschaltungsintegrierter speicher. |
JP2565497B2 (ja) * | 1985-09-11 | 1996-12-18 | ピルキントン マイクロ−エレクトロニクス リミテツド | 半導体集積回路 |
GB2184268B (en) * | 1985-12-13 | 1989-11-22 | Anamartic Ltd | Fault tolerant memory system |
GB8621357D0 (en) * | 1986-09-04 | 1986-10-15 | Mcallister R I | Hinged barrier semiconductor integrated circuits |
US5367208A (en) | 1986-09-19 | 1994-11-22 | Actel Corporation | Reconfigurable programmable interconnect architecture |
US5187393A (en) * | 1986-09-19 | 1993-02-16 | Actel Corporation | Reconfigurable programmable interconnect architecture |
US5477165A (en) * | 1986-09-19 | 1995-12-19 | Actel Corporation | Programmable logic module and architecture for field programmable gate array device |
US5172014A (en) * | 1986-09-19 | 1992-12-15 | Actel Corporation | Programmable interconnect architecture |
US5451887A (en) * | 1986-09-19 | 1995-09-19 | Actel Corporation | Programmable logic module and architecture for field programmable gate array device |
US4983959A (en) * | 1986-10-01 | 1991-01-08 | Texas Instruments Incorporated | Logic output macrocell |
IT1206265B (it) * | 1987-02-27 | 1989-04-14 | Texas Instruments Italia Spa | Complesso di memoria ram a doppia porta con organizzazione variabile a misura di utente |
JP2567463B2 (ja) * | 1987-10-02 | 1996-12-25 | 川崎製鉄株式会社 | プロブラマブル入出力回路 |
US5068603A (en) * | 1987-10-07 | 1991-11-26 | Xilinx, Inc. | Structure and method for producing mask-programmed integrated circuits which are pin compatible substitutes for memory-configured logic arrays |
JPH0646707B2 (ja) * | 1988-06-30 | 1994-06-15 | 川崎製鉄株式会社 | プログラマブル論理素子 |
EP0317287B1 (en) * | 1987-11-20 | 1992-11-11 | Kawasaki Steel Corporation | Programmable logic device |
JPH01171321A (ja) * | 1987-12-25 | 1989-07-06 | Kawasaki Steel Corp | プログラマブル論理要素 |
US4864161A (en) * | 1988-05-05 | 1989-09-05 | Altera Corporation | Multifunction flip-flop-type circuit |
US5452231A (en) * | 1988-10-05 | 1995-09-19 | Quickturn Design Systems, Inc. | Hierarchically connected reconfigurable logic assembly |
ATE131643T1 (de) * | 1988-10-05 | 1995-12-15 | Quickturn Systems Inc | Verfahren zur verwendung einer elektronisch wiederkonfigurierbaren gatterfeld-logik und dadurch hergestelltes gerät |
US5109353A (en) * | 1988-12-02 | 1992-04-28 | Quickturn Systems, Incorporated | Apparatus for emulation of electronic hardware system |
US4984192A (en) * | 1988-12-02 | 1991-01-08 | Ultrasystems Defense Inc. | Programmable state machines connectable in a reconfiguration switching network for performing real-time data processing |
US5329470A (en) * | 1988-12-02 | 1994-07-12 | Quickturn Systems, Inc. | Reconfigurable hardware emulation system |
GB8828828D0 (en) | 1988-12-09 | 1989-01-18 | Pilkington Micro Electronics | Semiconductor integrated circuit |
IT1225638B (it) * | 1988-12-28 | 1990-11-22 | Sgs Thomson Microelectronics | Dispositivo logico integrato come una rete di maglie di memorie distribuite |
JPH02222217A (ja) * | 1989-02-22 | 1990-09-05 | Toshiba Corp | プログラマブル論理回路 |
GB8906145D0 (en) * | 1989-03-17 | 1989-05-04 | Algotronix Ltd | Configurable cellular array |
US4940909A (en) * | 1989-05-12 | 1990-07-10 | Plus Logic, Inc. | Configuration control circuit for programmable logic devices |
US5343406A (en) * | 1989-07-28 | 1994-08-30 | Xilinx, Inc. | Distributed memory architecture for a configurable logic array and method for using distributed memory |
US5212652A (en) * | 1989-08-15 | 1993-05-18 | Advanced Micro Devices, Inc. | Programmable gate array with improved interconnect structure |
US5255203A (en) * | 1989-08-15 | 1993-10-19 | Advanced Micro Devices, Inc. | Interconnect structure for programmable logic device |
US5644496A (en) * | 1989-08-15 | 1997-07-01 | Advanced Micro Devices, Inc. | Programmable logic device with internal time-constant multiplexing of signals from external interconnect buses |
US5260881A (en) * | 1989-10-30 | 1993-11-09 | Advanced Micro Devices, Inc. | Programmable gate array with improved configurable logic block |
US5231588A (en) * | 1989-08-15 | 1993-07-27 | Advanced Micro Devices, Inc. | Programmable gate array with logic cells having symmetrical input/output structures |
US5185706A (en) * | 1989-08-15 | 1993-02-09 | Advanced Micro Devices, Inc. | Programmable gate array with logic cells having configurable output enable |
US5233539A (en) * | 1989-08-15 | 1993-08-03 | Advanced Micro Devices, Inc. | Programmable gate array with improved interconnect structure, input/output structure and configurable logic block |
JPH0654873B2 (ja) * | 1989-09-04 | 1994-07-20 | 株式会社東芝 | プログラマブル型論理装置 |
US5377124A (en) * | 1989-09-20 | 1994-12-27 | Aptix Corporation | Field programmable printed circuit board |
US5400262A (en) * | 1989-09-20 | 1995-03-21 | Aptix Corporation | Universal interconnect matrix array |
US5140193A (en) * | 1990-03-27 | 1992-08-18 | Xilinx, Inc. | Programmable connector for programmable logic device |
US5295090A (en) * | 1992-05-10 | 1994-03-15 | Xilinx, Inc. | Logic structure and circuit for fast carry |
CA2037142C (en) * | 1990-05-10 | 1996-05-07 | Hung-Cheng Hsieh | Logic structure and circuit for fast carry |
US5267187A (en) * | 1990-05-10 | 1993-11-30 | Xilinx Inc | Logic structure and circuit for fast carry |
US5198705A (en) * | 1990-05-11 | 1993-03-30 | Actel Corporation | Logic module with configurable combinational and sequential blocks |
US5055718A (en) * | 1990-05-11 | 1991-10-08 | Actel Corporation | Logic module with configurable combinational and sequential blocks |
US5363319A (en) * | 1990-09-29 | 1994-11-08 | Kabushiki Kaisha Toshiba | Logic simulator |
EP0481703B1 (en) * | 1990-10-15 | 2003-09-17 | Aptix Corporation | Interconnect substrate having integrated circuit for programmable interconnection and sample testing |
US5321704A (en) * | 1991-01-16 | 1994-06-14 | Xilinx, Inc. | Error detection structure and method using partial polynomial check |
US5107146A (en) * | 1991-02-13 | 1992-04-21 | Actel Corporation | Mixed mode analog/digital programmable interconnect architecture |
US5416367A (en) * | 1991-03-06 | 1995-05-16 | Quicklogic Corporation | Programmable application specific integrated circuit and logic cell therefor |
US5220213A (en) * | 1991-03-06 | 1993-06-15 | Quicklogic Corporation | Programmable application specific integrated circuit and logic cell therefor |
US5122685A (en) * | 1991-03-06 | 1992-06-16 | Quicklogic Corporation | Programmable application specific integrated circuit and logic cell therefor |
US5322812A (en) * | 1991-03-20 | 1994-06-21 | Crosspoint Solutions, Inc. | Improved method of fabricating antifuses in an integrated circuit device and resulting structure |
US5255221A (en) * | 1991-04-02 | 1993-10-19 | At&T Bell Laboratories | Fully configurable versatile field programmable function element |
DE69227144T2 (de) * | 1991-05-10 | 1999-03-18 | Kabushiki Kaisha Toshiba, Kawasaki, Kanagawa | Programmierbare logische Einheit |
US5338984A (en) * | 1991-08-29 | 1994-08-16 | National Semiconductor Corp. | Local and express diagonal busses in a configurable logic array |
US6759870B2 (en) | 1991-09-03 | 2004-07-06 | Altera Corporation | Programmable logic array integrated circuits |
US5260611A (en) * | 1991-09-03 | 1993-11-09 | Altera Corporation | Programmable logic array having local and long distance conductors |
US5436575A (en) * | 1991-09-03 | 1995-07-25 | Altera Corporation | Programmable logic array integrated circuits |
US5260610A (en) * | 1991-09-03 | 1993-11-09 | Altera Corporation | Programmable logic element interconnections for programmable logic array integrated circuits |
US5550782A (en) * | 1991-09-03 | 1996-08-27 | Altera Corporation | Programmable logic array integrated circuits |
US20020130681A1 (en) | 1991-09-03 | 2002-09-19 | Cliff Richard G. | Programmable logic array integrated circuits |
US5633830A (en) * | 1995-11-08 | 1997-05-27 | Altera Corporation | Random access memory block circuitry for programmable logic array integrated circuit devices |
US5883850A (en) * | 1991-09-03 | 1999-03-16 | Altera Corporation | Programmable logic array integrated circuits |
US5371422A (en) * | 1991-09-03 | 1994-12-06 | Altera Corporation | Programmable logic device having multiplexers and demultiplexers randomly connected to global conductors for interconnections between logic elements |
WO1993006559A1 (en) * | 1991-09-23 | 1993-04-01 | Aptix Corporation | Universal interconnect matrix array |
US5513124A (en) * | 1991-10-30 | 1996-04-30 | Xilinx, Inc. | Logic placement using positionally asymmetrical partitioning method |
DE9114200U1 (de) * | 1991-11-14 | 1993-03-18 | Siemens AG, 8000 München | Zeitrelais mit integrierter Signalverarbeitung |
US5258668A (en) * | 1992-05-08 | 1993-11-02 | Altera Corporation | Programmable logic array integrated circuits with cascade connections between logic modules |
USRE35977E (en) * | 1992-05-08 | 1998-12-01 | Altera Corporation | Look up table implementation of fast carry arithmetic and exclusive-or operations |
US5274581A (en) * | 1992-05-08 | 1993-12-28 | Altera Corporation | Look up table implementation of fast carry for adders and counters |
US5254886A (en) * | 1992-06-19 | 1993-10-19 | Actel Corporation | Clock distribution scheme for user-programmable logic array architecture |
US5331226A (en) * | 1992-07-23 | 1994-07-19 | Xilinx, Inc. | Logic cell for field programmable gate array having optional input inverters |
US5365125A (en) * | 1992-07-23 | 1994-11-15 | Xilinx, Inc. | Logic cell for field programmable gate array having optional internal feedback and optional cascade |
US5646547A (en) * | 1994-04-28 | 1997-07-08 | Xilinx, Inc. | Logic cell which can be configured as a latch without static one's problem |
US5386154A (en) * | 1992-07-23 | 1995-01-31 | Xilinx, Inc. | Compact logic cell for field programmable gate array chip |
US5304871A (en) * | 1992-07-24 | 1994-04-19 | Actel Corporation | Programmable interconnect architecture employing leaky programmable elements |
DE4224804C1 (de) * | 1992-07-27 | 1994-01-13 | Siemens Ag | Programmierbare logische Schaltungsanordnung |
DE4224805A1 (de) * | 1992-07-27 | 1994-02-03 | Siemens Ag | Konfigurierbare Logikzelle |
JPH08501911A (ja) * | 1992-07-29 | 1996-02-27 | ザイリンクス, インコーポレイテッド | オプションの入力インバータを具備するフィールドプログラマブルゲートアレイ用ロジックセル |
CA2091860A1 (en) * | 1992-07-29 | 1994-01-30 | F. Erich Goetting | Configuration control unit for programming a field programmable gate array and reading array status |
US5317698A (en) * | 1992-08-18 | 1994-05-31 | Actel Corporation | FPGA architecture including direct logic function circuit to I/O interconnections |
JP3462534B2 (ja) * | 1992-08-28 | 2003-11-05 | テキサス インスツルメンツ インコーポレイテツド | プログラマブル論理回路および方法 |
US5425036A (en) * | 1992-09-18 | 1995-06-13 | Quickturn Design Systems, Inc. | Method and apparatus for debugging reconfigurable emulation systems |
US5329179A (en) * | 1992-10-05 | 1994-07-12 | Lattice Semiconductor Corporation | Arrangement for parallel programming of in-system programmable IC logical devices |
JPH06125067A (ja) * | 1992-10-12 | 1994-05-06 | Mitsubishi Electric Corp | 半導体集積回路及びその設計方法 |
GB9223226D0 (en) * | 1992-11-05 | 1992-12-16 | Algotronix Ltd | Improved configurable cellular array (cal ii) |
US5434514A (en) * | 1992-11-19 | 1995-07-18 | Altera Corporation | Programmable logic devices with spare circuits for replacement of defects |
US5414377A (en) * | 1992-12-21 | 1995-05-09 | Xilinx, Inc. | Logic block with look-up table for configuration and memory |
GB9303084D0 (en) * | 1993-02-16 | 1993-03-31 | Inmos Ltd | Programmable logic circuit |
US5317212A (en) * | 1993-03-19 | 1994-05-31 | Wahlstrom Sven E | Dynamic control of configurable logic |
US5311080A (en) * | 1993-03-26 | 1994-05-10 | At&T Bell Laboratories | Field programmable gate array with direct input/output connection |
US5483178A (en) * | 1993-03-29 | 1996-01-09 | Altera Corporation | Programmable logic device with logic block outputs coupled to adjacent logic block output multiplexers |
US5809281A (en) * | 1993-03-30 | 1998-09-15 | Altera Corporation | Field programmable gate array with high speed SRAM based configurable function block configurable as high performance logic or block of SRAM |
US5432467A (en) * | 1993-05-07 | 1995-07-11 | Altera Corporation | Programmable logic device with low power voltage level translator |
US5381058A (en) * | 1993-05-21 | 1995-01-10 | At&T Corp. | FPGA having PFU with programmable output driver inputs |
SG46393A1 (en) * | 1993-05-28 | 1998-02-20 | Univ California | Field programmable logic device with dynamic interconnections to a dynamic logic core |
IL109921A (en) * | 1993-06-24 | 1997-09-30 | Quickturn Design Systems | Method and apparatus for configuring memory circuits |
US5399922A (en) * | 1993-07-02 | 1995-03-21 | Altera Corporation | Macrocell comprised of two look-up tables and two flip-flops |
JP3176482B2 (ja) * | 1993-07-07 | 2001-06-18 | 富士通株式会社 | 論理シミュレーション装置 |
US5444394A (en) * | 1993-07-08 | 1995-08-22 | Altera Corporation | PLD with selective inputs from local and global conductors |
GB2280293B (en) * | 1993-07-19 | 1997-12-10 | Hewlett Packard Co | Architecture for programmable logic |
US6460131B1 (en) | 1993-08-03 | 2002-10-01 | Xilinx Inc. | FPGA input output buffer with registered tristate enable |
US5457410A (en) * | 1993-08-03 | 1995-10-10 | Btr, Inc. | Architecture and interconnect scheme for programmable logic circuits |
WO1995004402A1 (en) * | 1993-08-03 | 1995-02-09 | Xilinx, Inc. | Microprocessor-based fpga |
US5410194A (en) * | 1993-08-11 | 1995-04-25 | Xilinx, Inc. | Asynchronous or synchronous load multifunction flip-flop |
US5523705A (en) * | 1993-08-24 | 1996-06-04 | Intel Corporation | Apparatus and method for selecting and buffering inputs of programmable logic devices |
US5506517A (en) * | 1993-09-01 | 1996-04-09 | Lattice Semiconductor Corporation | Output enable structure and method for a programmable logic device |
US5629886A (en) * | 1993-09-02 | 1997-05-13 | Xilinx, Inc. | Method and structure for providing fast propagation of a carry signal in a field programmable gate array |
US5898319A (en) * | 1993-09-02 | 1999-04-27 | Xilinx, Inc. | Method and structure for providing fast conditional sum in a field programmable gate array |
US6154053A (en) * | 1993-09-02 | 2000-11-28 | Xilinx, Inc. | Look-ahead carry structure with homogeneous CLB structure and pitch larger than CLB pitch |
US5481206A (en) * | 1993-09-02 | 1996-01-02 | Xilinx, Inc. | Circuit for fast carry and logic |
US6288570B1 (en) | 1993-09-02 | 2001-09-11 | Xilinx, Inc. | Logic structure and circuit for fast carry |
US5349250A (en) * | 1993-09-02 | 1994-09-20 | Xilinx, Inc. | Logic structure and circuit for fast carry |
US5546018A (en) * | 1993-09-02 | 1996-08-13 | Xilinx, Inc. | Fast carry structure with synchronous input |
EP0734573B1 (en) * | 1993-12-13 | 2002-04-03 | Lattice Semiconductor Corporation | Application specific modules in a programmable logic device |
US5742179A (en) * | 1994-01-27 | 1998-04-21 | Dyna Logic Corporation | High speed programmable logic architecture |
US5504440A (en) * | 1994-01-27 | 1996-04-02 | Dyna Logic Corporation | High speed programmable logic architecture |
US5614844A (en) * | 1994-01-27 | 1997-03-25 | Dyna Logic Corporation | High speed programmable logic architecture |
US5680583A (en) * | 1994-02-16 | 1997-10-21 | Arkos Design, Inc. | Method and apparatus for a trace buffer in an emulation system |
US5369314A (en) * | 1994-02-22 | 1994-11-29 | Altera Corporation | Programmable logic device with redundant circuitry |
US5581200A (en) * | 1994-03-04 | 1996-12-03 | Gudger; Keith H. | Stored and combinational logic function generator without dedicated storage elements |
US5805834A (en) * | 1994-03-30 | 1998-09-08 | Zilog, Inc. | Hot reconfigurable parallel bus bridging circuit |
US5682107A (en) * | 1994-04-01 | 1997-10-28 | Xilinx, Inc. | FPGA architecture with repeatable tiles including routing matrices and logic matrices |
US5781756A (en) * | 1994-04-01 | 1998-07-14 | Xilinx, Inc. | Programmable logic device with partially configurable memory cells and a method for configuration |
US5430687A (en) * | 1994-04-01 | 1995-07-04 | Xilinx, Inc. | Programmable logic device including a parallel input device for loading memory cells |
US5550843A (en) * | 1994-04-01 | 1996-08-27 | Xilinx, Inc. | Programmable scan chain testing structure and method |
US5504439A (en) * | 1994-04-01 | 1996-04-02 | Xilinx, Inc. | I/O interface cell for use with optional pad |
US5453706A (en) * | 1994-04-01 | 1995-09-26 | Xilinx, Inc. | Field programmable gate array providing contention free configuration and reconfiguration |
US6294928B1 (en) | 1996-04-05 | 2001-09-25 | Altera Corporation | Programmable logic device with highly routable interconnect |
US6181162B1 (en) | 1994-04-10 | 2001-01-30 | Altera Corporation | Programmable logic device with highly routable interconnect |
US5802540A (en) * | 1995-11-08 | 1998-09-01 | Altera Corporation | Programming and verification address generation for random access memory blocks in programmable logic array integrated circuit devices |
US5617573A (en) * | 1994-05-23 | 1997-04-01 | Xilinx, Inc. | State splitting for level reduction |
US5442306A (en) * | 1994-09-09 | 1995-08-15 | At&T Corp. | Field programmable gate array using look-up tables, multiplexers and decoders |
US5450022A (en) * | 1994-10-07 | 1995-09-12 | Xilinx Inc. | Structure and method for configuration of a field programmable gate array |
US5606266A (en) * | 1994-11-04 | 1997-02-25 | Altera Corporation | Programmable logic array integrated circuits with enhanced output routing |
US5815726A (en) * | 1994-11-04 | 1998-09-29 | Altera Corporation | Coarse-grained look-up table architecture |
US5581199A (en) * | 1995-01-04 | 1996-12-03 | Xilinx, Inc. | Interconnect architecture for field programmable gate array using variable length conductors |
US6181158B1 (en) * | 1995-01-20 | 2001-01-30 | Xilinx, Inc. | Configuration logic to eliminate signal contention during reconfiguration |
US5592105A (en) * | 1995-01-20 | 1997-01-07 | Xilinx, Inc. | Configuration logic to eliminate signal contention during reconfiguration |
US5742180A (en) * | 1995-02-10 | 1998-04-21 | Massachusetts Institute Of Technology | Dynamically programmable gate array with multiple contexts |
US5537057A (en) * | 1995-02-14 | 1996-07-16 | Altera Corporation | Programmable logic array device with grouped logic regions and three types of conductors |
US5581198A (en) * | 1995-02-24 | 1996-12-03 | Xilinx, Inc. | Shadow DRAM for programmable logic devices |
US5847577A (en) * | 1995-02-24 | 1998-12-08 | Xilinx, Inc. | DRAM memory cell for programmable logic devices |
US5757207A (en) * | 1995-03-22 | 1998-05-26 | Altera Corporation | Programmable logic array integrated circuit incorporating a first-in first-out memory |
US6049223A (en) | 1995-03-22 | 2000-04-11 | Altera Corporation | Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory |
GB2290895A (en) * | 1995-04-10 | 1996-01-10 | Memory Corp Plc | Shift register with comparator |
WO1996034346A1 (en) * | 1995-04-28 | 1996-10-31 | Xilinx, Inc. | Microprocessor with distributed registers accessible by programmable logic device |
US5625301A (en) * | 1995-05-18 | 1997-04-29 | Actel Corporation | Flexible FPGA input/output architecture |
US5646546A (en) * | 1995-06-02 | 1997-07-08 | International Business Machines Corporation | Programmable logic cell having configurable gates and multiplexers |
US5751165A (en) * | 1995-08-18 | 1998-05-12 | Chip Express (Israel) Ltd. | High speed customizable logic array device |
US5784313A (en) * | 1995-08-18 | 1998-07-21 | Xilinx, Inc. | Programmable logic device including configuration data or user data memory slices |
US5821773A (en) * | 1995-09-06 | 1998-10-13 | Altera Corporation | Look-up table based logic element with complete permutability of the inputs to the secondary signals |
US5777489A (en) | 1995-10-13 | 1998-07-07 | Mentor Graphics Corporation | Field programmable gate array with integrated debugging facilities |
US5592102A (en) * | 1995-10-19 | 1997-01-07 | Altera Corporation | Means and apparatus to minimize the effects of silicon processing defects in programmable logic devices |
US5712806A (en) * | 1995-10-30 | 1998-01-27 | International Business Machines Corporation | Optimized multiplexer structure for emulation systems |
US5943242A (en) | 1995-11-17 | 1999-08-24 | Pact Gmbh | Dynamically reconfigurable data processing system |
US5650734A (en) * | 1995-12-11 | 1997-07-22 | Altera Corporation | Programming programmable transistor devices using state machines |
US7266725B2 (en) | 2001-09-03 | 2007-09-04 | Pact Xpp Technologies Ag | Method for debugging reconfigurable architectures |
IL116792A (en) * | 1996-01-16 | 2000-01-31 | Chip Express Israel Ltd | Customizable integrated circuit device |
US5744980A (en) * | 1996-02-16 | 1998-04-28 | Actel Corporation | Flexible, high-performance static RAM architecture for field-programmable gate arrays |
US5726484A (en) * | 1996-03-06 | 1998-03-10 | Xilinx, Inc. | Multilayer amorphous silicon antifuse |
US5726584A (en) * | 1996-03-18 | 1998-03-10 | Xilinx, Inc. | Virtual high density programmable integrated circuit having addressable shared memory cells |
US5869979A (en) | 1996-04-05 | 1999-02-09 | Altera Corporation | Technique for preconditioning I/Os during reconfiguration |
US6107822A (en) | 1996-04-09 | 2000-08-22 | Altera Corporation | Logic element for a programmable logic integrated circuit |
US5977791A (en) | 1996-04-15 | 1999-11-02 | Altera Corporation | Embedded memory block with FIFO mode for programmable logic device |
US5894565A (en) * | 1996-05-20 | 1999-04-13 | Atmel Corporation | Field programmable gate array with distributed RAM and increased cell utilization |
JPH09320284A (ja) * | 1996-05-31 | 1997-12-12 | Nec Corp | 半導体集積回路およびその端子状態設定方法 |
US5952847A (en) * | 1996-06-25 | 1999-09-14 | Actel Corporation | Multiple logic family compatible output driver |
US6624658B2 (en) * | 1999-02-04 | 2003-09-23 | Advantage Logic, Inc. | Method and apparatus for universal program controlled bus architecture |
US6034547A (en) | 1996-09-04 | 2000-03-07 | Advantage Logic, Inc. | Method and apparatus for universal program controlled bus |
US5781032A (en) * | 1996-09-09 | 1998-07-14 | International Business Machines Corporation | Programmable inverter circuit used in a programmable logic cell |
US5805477A (en) * | 1996-09-26 | 1998-09-08 | Hewlett-Packard Company | Arithmetic cell for field programmable devices |
US5825202A (en) * | 1996-09-26 | 1998-10-20 | Xilinx, Inc. | Integrated circuit with field programmable and application specific logic areas |
US5841967A (en) * | 1996-10-17 | 1998-11-24 | Quickturn Design Systems, Inc. | Method and apparatus for design verification using emulation and simulation |
US5760611A (en) * | 1996-10-25 | 1998-06-02 | International Business Machines Corporation | Function generator for programmable gate array |
US5883526A (en) * | 1997-04-17 | 1999-03-16 | Altera Corporation | Hierarchical interconnect for programmable logic devices |
US6005410A (en) * | 1996-12-05 | 1999-12-21 | International Business Machines Corporation | Interconnect structure between heterogeneous core regions in a programmable array |
DE19651075A1 (de) | 1996-12-09 | 1998-06-10 | Pact Inf Tech Gmbh | Einheit zur Verarbeitung von numerischen und logischen Operationen, zum Einsatz in Prozessoren (CPU's), Mehrrechnersystemen, Datenflußprozessoren (DFP's), digitalen Signal Prozessoren (DSP's) oder dergleichen |
DE19654595A1 (de) | 1996-12-20 | 1998-07-02 | Pact Inf Tech Gmbh | I0- und Speicherbussystem für DFPs sowie Bausteinen mit zwei- oder mehrdimensionaler programmierbaren Zellstrukturen |
DE19654593A1 (de) | 1996-12-20 | 1998-07-02 | Pact Inf Tech Gmbh | Umkonfigurierungs-Verfahren für programmierbare Bausteine zur Laufzeit |
US6338106B1 (en) | 1996-12-20 | 2002-01-08 | Pact Gmbh | I/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures |
EP1329816B1 (de) | 1996-12-27 | 2011-06-22 | Richter, Thomas | Verfahren zum selbständigen dynamischen Umladen von Datenflussprozessoren (DFPs) sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen (FPGAs, DPGAs, o.dgl.) |
DE19654846A1 (de) * | 1996-12-27 | 1998-07-09 | Pact Inf Tech Gmbh | Verfahren zum selbständigen dynamischen Umladen von Datenflußprozessoren (DFPs) sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen (FPGAs, DPGAs, o. dgl.) |
US6133751A (en) | 1998-08-05 | 2000-10-17 | Xilinx, Inc. | Programmable delay element |
US5841296A (en) * | 1997-01-21 | 1998-11-24 | Xilinx, Inc. | Programmable delay element |
US6029236A (en) * | 1997-01-28 | 2000-02-22 | Altera Corporation | Field programmable gate array with high speed SRAM based configurable function block configurable as high performance logic or block of SRAM |
US5936426A (en) * | 1997-02-03 | 1999-08-10 | Actel Corporation | Logic function module for field programmable array |
DE19704044A1 (de) * | 1997-02-04 | 1998-08-13 | Pact Inf Tech Gmbh | Verfahren zur automatischen Adressgenerierung von Bausteinen innerhalb Clustern aus einer Vielzahl dieser Bausteine |
US6091258A (en) * | 1997-02-05 | 2000-07-18 | Altera Corporation | Redundancy circuitry for logic circuits |
US6034536A (en) * | 1997-02-05 | 2000-03-07 | Altera Corporation | Redundancy circuitry for logic circuits |
DE19704728A1 (de) | 1997-02-08 | 1998-08-13 | Pact Inf Tech Gmbh | Verfahren zur Selbstsynchronisation von konfigurierbaren Elementen eines programmierbaren Bausteines |
US6542998B1 (en) | 1997-02-08 | 2003-04-01 | Pact Gmbh | Method of self-synchronization of configurable elements of a programmable module |
DE19704742A1 (de) * | 1997-02-11 | 1998-09-24 | Pact Inf Tech Gmbh | Internes Bussystem für DFPs, sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen, zur Bewältigung großer Datenmengen mit hohem Vernetzungsaufwand |
US6201410B1 (en) | 1997-02-26 | 2001-03-13 | Xilinx, Inc. | Wide logic gate implemented in an FPGA configurable logic element |
US5889411A (en) * | 1997-02-26 | 1999-03-30 | Xilinx, Inc. | FPGA having logic element carry chains capable of generating wide XOR functions |
US5920202A (en) * | 1997-02-26 | 1999-07-06 | Xilinx, Inc. | Configurable logic element with ability to evaluate five and six input functions |
US6204689B1 (en) | 1997-02-26 | 2001-03-20 | Xilinx, Inc. | Input/output interconnect circuit for FPGAs |
US5963050A (en) | 1997-02-26 | 1999-10-05 | Xilinx, Inc. | Configurable logic element with fast feedback paths |
US5942913A (en) * | 1997-03-20 | 1999-08-24 | Xilinx, Inc. | FPGA repeatable interconnect structure with bidirectional and unidirectional interconnect lines |
US5914616A (en) * | 1997-02-26 | 1999-06-22 | Xilinx, Inc. | FPGA repeatable interconnect structure with hierarchical interconnect lines |
US6014038A (en) * | 1997-03-21 | 2000-01-11 | Lightspeed Semiconductor Corporation | Function block architecture for gate array |
US6026230A (en) * | 1997-05-02 | 2000-02-15 | Axis Systems, Inc. | Memory simulation system and method |
US6009256A (en) * | 1997-05-02 | 1999-12-28 | Axis Systems, Inc. | Simulation/emulation system and method |
US6389379B1 (en) | 1997-05-02 | 2002-05-14 | Axis Systems, Inc. | Converification system and method |
US6421251B1 (en) | 1997-05-02 | 2002-07-16 | Axis Systems Inc | Array board interconnect system and method |
US6134516A (en) * | 1997-05-02 | 2000-10-17 | Axis Systems, Inc. | Simulation server system and method |
US6321366B1 (en) | 1997-05-02 | 2001-11-20 | Axis Systems, Inc. | Timing-insensitive glitch-free logic system and method |
US6249143B1 (en) | 1997-05-23 | 2001-06-19 | Altera Corporation | Programmable logic array integrated circuit with distributed random access memory array |
DE69802927T2 (de) | 1997-05-23 | 2002-08-08 | Altera Corp. ( A Delaware Corporation), San Jose | Redundanzschaltung für programmierbare logikanordnung mit verschachtelten eingangsschaltkreisen |
US5960191A (en) * | 1997-05-30 | 1999-09-28 | Quickturn Design Systems, Inc. | Emulation system with time-multiplexed interconnect |
US6006321A (en) * | 1997-06-13 | 1999-12-21 | Malleable Technologies, Inc. | Programmable logic datapath that may be used in a field programmable device |
US5970240A (en) * | 1997-06-25 | 1999-10-19 | Quickturn Design Systems, Inc. | Method and apparatus for configurable memory emulation |
US6128215A (en) * | 1997-08-19 | 2000-10-03 | Altera Corporation | Static random access memory circuits |
US9092595B2 (en) | 1997-10-08 | 2015-07-28 | Pact Xpp Technologies Ag | Multiprocessor having associated RAM units |
US8686549B2 (en) | 2001-09-03 | 2014-04-01 | Martin Vorbach | Reconfigurable elements |
US6072332A (en) * | 1997-10-14 | 2000-06-06 | Altera Corporation | Variable depth memories for programmable logic devices |
US6191611B1 (en) | 1997-10-16 | 2001-02-20 | Altera Corporation | Driver circuitry for programmable logic devices with hierarchical interconnection resources |
US6157210A (en) * | 1997-10-16 | 2000-12-05 | Altera Corporation | Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits |
US6185724B1 (en) | 1997-12-02 | 2001-02-06 | Xilinx, Inc. | Template-based simulated annealing move-set that improves FPGA architectural feature utilization |
US6069490A (en) * | 1997-12-02 | 2000-05-30 | Xilinx, Inc. | Routing architecture using a direct connect routing mesh |
US6611932B2 (en) | 1997-12-05 | 2003-08-26 | Lightspeed Semiconductor Corporation | Method and apparatus for controlling and observing data in a logic block-based ASIC |
US6223313B1 (en) | 1997-12-05 | 2001-04-24 | Lightspeed Semiconductor Corporation | Method and apparatus for controlling and observing data in a logic block-based asic |
US6172519B1 (en) * | 1997-12-18 | 2001-01-09 | Xilinx, Inc. | Bus-hold circuit having a defined state during set-up of an in-system programmable device |
DE19861088A1 (de) | 1997-12-22 | 2000-02-10 | Pact Inf Tech Gmbh | Verfahren zur Reparatur von integrierten Schaltkreisen |
DE19807872A1 (de) | 1998-02-25 | 1999-08-26 | Pact Inf Tech Gmbh | Verfahren zur Verwaltung von Konfigurationsdaten in Datenflußprozessoren sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstruktur (FPGAs, DPGAs, o. dgl. |
US6177808B1 (en) * | 1998-04-30 | 2001-01-23 | Compaq Computer Corporation | Integration of bidirectional switches with programmable logic |
US6467017B1 (en) | 1998-06-23 | 2002-10-15 | Altera Corporation | Programmable logic device having embedded dual-port random access memory configurable as single-port memory |
US6201404B1 (en) | 1998-07-14 | 2001-03-13 | Altera Corporation | Programmable logic device with redundant circuitry |
US6184707B1 (en) | 1998-10-07 | 2001-02-06 | Altera Corporation | Look-up table based logic element with complete permutability of the inputs to the secondary signals |
KR100301809B1 (ko) * | 1998-11-24 | 2001-09-06 | 김영환 | 데이터 입출력 버퍼 제어회로_ |
US6150838A (en) | 1999-02-25 | 2000-11-21 | Xilinx, Inc. | FPGA configurable logic block with multi-purpose logic/memory circuit |
US6400180B2 (en) * | 1999-02-25 | 2002-06-04 | Xilinix, Inc. | Configurable lookup table for programmable logic devices |
US6236229B1 (en) | 1999-05-13 | 2001-05-22 | Easic Corporation | Integrated circuits which employ look up tables to provide highly efficient logic cells and logic functionalities |
US6331733B1 (en) | 1999-08-10 | 2001-12-18 | Easic Corporation | Semiconductor device |
US6245634B1 (en) | 1999-10-28 | 2001-06-12 | Easic Corporation | Method for design and manufacture of semiconductors |
US6697387B1 (en) * | 1999-06-07 | 2004-02-24 | Micron Technology, Inc. | Apparatus for multiplexing signals through I/O pins |
DE10081643D2 (de) | 1999-06-10 | 2002-05-29 | Pact Inf Tech Gmbh | Sequenz-Partitionierung auf Zellstrukturen |
US20040225865A1 (en) * | 1999-09-03 | 2004-11-11 | Cox Richard D. | Integrated database indexing system |
US6947882B1 (en) * | 1999-09-24 | 2005-09-20 | Mentor Graphics Corporation | Regionally time multiplexed emulation system |
US6756811B2 (en) * | 2000-03-10 | 2004-06-29 | Easic Corporation | Customizable and programmable cell array |
US6331790B1 (en) | 2000-03-10 | 2001-12-18 | Easic Corporation | Customizable and programmable cell array |
EP1342158B1 (de) | 2000-06-13 | 2010-08-04 | Richter, Thomas | Pipeline ct-protokolle und -kommunikation |
ATE437476T1 (de) | 2000-10-06 | 2009-08-15 | Pact Xpp Technologies Ag | Zellenanordnung mit segmentierter zwischenzellstruktur |
US8058899B2 (en) | 2000-10-06 | 2011-11-15 | Martin Vorbach | Logic cell array and bus system |
US7484081B1 (en) | 2000-10-10 | 2009-01-27 | Altera Corporation | Method and apparatus for protecting designs in SRAM-based programmable logic devices |
US6507212B1 (en) | 2000-11-02 | 2003-01-14 | Lattice Semiconductor Corporation | Wide input programmable logic system and method |
US6990555B2 (en) | 2001-01-09 | 2006-01-24 | Pact Xpp Technologies Ag | Method of hierarchical caching of configuration data having dataflow processors and modules having two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.) |
US7210129B2 (en) | 2001-08-16 | 2007-04-24 | Pact Xpp Technologies Ag | Method for translating programs for reconfigurable architectures |
US9250908B2 (en) | 2001-03-05 | 2016-02-02 | Pact Xpp Technologies Ag | Multi-processor bus and cache interconnection system |
US9436631B2 (en) | 2001-03-05 | 2016-09-06 | Pact Xpp Technologies Ag | Chip including memory element storing higher level memory data on a page by page basis |
US9037807B2 (en) | 2001-03-05 | 2015-05-19 | Pact Xpp Technologies Ag | Processor arrangement on a chip including data processing, memory, and interface elements |
US7844796B2 (en) | 2001-03-05 | 2010-11-30 | Martin Vorbach | Data processing device and method |
US9552047B2 (en) | 2001-03-05 | 2017-01-24 | Pact Xpp Technologies Ag | Multiprocessor having runtime adjustable clock and clock dependent power supply |
US9141390B2 (en) | 2001-03-05 | 2015-09-22 | Pact Xpp Technologies Ag | Method of processing data with an array of data processors according to application ID |
WO2005045692A2 (en) | 2003-08-28 | 2005-05-19 | Pact Xpp Technologies Ag | Data processing device and method |
US7444531B2 (en) | 2001-03-05 | 2008-10-28 | Pact Xpp Technologies Ag | Methods and devices for treating and processing data |
US7581076B2 (en) | 2001-03-05 | 2009-08-25 | Pact Xpp Technologies Ag | Methods and devices for treating and/or processing data |
US6836839B2 (en) | 2001-03-22 | 2004-12-28 | Quicksilver Technology, Inc. | Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements |
US7400668B2 (en) | 2001-03-22 | 2008-07-15 | Qst Holdings, Llc | Method and system for implementing a system acquisition function for use with a communication device |
US7752419B1 (en) | 2001-03-22 | 2010-07-06 | Qst Holdings, Llc | Method and system for managing hardware resources to implement system functions using an adaptive computing architecture |
US7962716B2 (en) | 2001-03-22 | 2011-06-14 | Qst Holdings, Inc. | Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements |
US7624204B2 (en) * | 2001-03-22 | 2009-11-24 | Nvidia Corporation | Input/output controller node in an adaptable computing environment |
US7433909B2 (en) * | 2002-06-25 | 2008-10-07 | Nvidia Corporation | Processing architecture for a reconfigurable arithmetic node |
US6720796B1 (en) | 2001-05-06 | 2004-04-13 | Altera Corporation | Multiple size memories in a programmable logic device |
US6605962B2 (en) | 2001-05-06 | 2003-08-12 | Altera Corporation | PLD architecture for flexible placement of IP function blocks |
US6577678B2 (en) | 2001-05-08 | 2003-06-10 | Quicksilver Technology | Method and system for reconfigurable channel coding |
US7076595B1 (en) * | 2001-05-18 | 2006-07-11 | Xilinx, Inc. | Programmable logic device including programmable interface core and central processing unit |
EP2224330B1 (de) | 2001-06-20 | 2012-05-09 | Krass, Maren | Verfahren und gerät zum partitionieren von grossen rechnerprogrammen |
US10031733B2 (en) | 2001-06-20 | 2018-07-24 | Scientia Sol Mentis Ag | Method for processing data |
JP3580785B2 (ja) | 2001-06-29 | 2004-10-27 | 株式会社半導体理工学研究センター | ルックアップテーブル、ルックアップテーブルを備えるプログラマブル論理回路装置、および、ルックアップテーブルの構成方法 |
US20030020082A1 (en) * | 2001-07-25 | 2003-01-30 | Motorola, Inc. | Structure and method for fabricating semiconductor structures and devices for optical switching |
US7996827B2 (en) | 2001-08-16 | 2011-08-09 | Martin Vorbach | Method for the translation of programs for reconfigurable architectures |
US7434191B2 (en) | 2001-09-03 | 2008-10-07 | Pact Xpp Technologies Ag | Router |
US8686475B2 (en) | 2001-09-19 | 2014-04-01 | Pact Xpp Technologies Ag | Reconfigurable elements |
US6798239B2 (en) * | 2001-09-28 | 2004-09-28 | Xilinx, Inc. | Programmable gate array having interconnecting logic to support embedded fixed logic circuitry |
US6781407B2 (en) | 2002-01-09 | 2004-08-24 | Xilinx, Inc. | FPGA and embedded circuitry initialization and processing |
US7420392B2 (en) * | 2001-09-28 | 2008-09-02 | Xilinx, Inc. | Programmable gate array and embedded circuitry initialization and processing |
US6696856B1 (en) | 2001-10-30 | 2004-02-24 | Lightspeed Semiconductor Corporation | Function block architecture with variable drive strengths |
US6489806B1 (en) * | 2001-11-14 | 2002-12-03 | Lattice Semiconductor Corporation | Zero-power logic cell for use in programmable logic devices |
US6996758B1 (en) | 2001-11-16 | 2006-02-07 | Xilinx, Inc. | Apparatus for testing an interconnecting logic fabric |
US6983405B1 (en) | 2001-11-16 | 2006-01-03 | Xilinx, Inc., | Method and apparatus for testing circuitry embedded within a field programmable gate array |
US6886092B1 (en) * | 2001-11-19 | 2005-04-26 | Xilinx, Inc. | Custom code processing in PGA by providing instructions from fixed logic processor portion to programmable dedicated processor portion |
US6986021B2 (en) * | 2001-11-30 | 2006-01-10 | Quick Silver Technology, Inc. | Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements |
US8412915B2 (en) | 2001-11-30 | 2013-04-02 | Altera Corporation | Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements |
US7602740B2 (en) | 2001-12-10 | 2009-10-13 | Qst Holdings, Inc. | System for adapting device standards after manufacture |
US7215701B2 (en) | 2001-12-12 | 2007-05-08 | Sharad Sambhwani | Low I/O bandwidth method and system for implementing detection and identification of scrambling codes |
US20030108012A1 (en) * | 2001-12-12 | 2003-06-12 | Quicksilver Technology, Inc. | Method and system for detecting and identifying scrambling codes |
US7577822B2 (en) | 2001-12-14 | 2009-08-18 | Pact Xpp Technologies Ag | Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization |
US7403981B2 (en) * | 2002-01-04 | 2008-07-22 | Quicksilver Technology, Inc. | Apparatus and method for adaptive multimedia reception and transmission in communication environments |
DE10392560D2 (de) | 2002-01-19 | 2005-05-12 | Pact Xpp Technologies Ag | Reconfigurierbarer Prozessor |
US6820248B1 (en) | 2002-02-14 | 2004-11-16 | Xilinx, Inc. | Method and apparatus for routing interconnects to devices with dissimilar pitches |
EP1514193B1 (de) | 2002-02-18 | 2008-07-23 | PACT XPP Technologies AG | Bussysteme und rekonfigurationsverfahren |
US6754882B1 (en) * | 2002-02-22 | 2004-06-22 | Xilinx, Inc. | Method and system for creating a customized support package for an FPGA-based system-on-chip (SoC) |
US6976160B1 (en) | 2002-02-22 | 2005-12-13 | Xilinx, Inc. | Method and system for controlling default values of flip-flops in PGA/ASIC-based designs |
US7007121B1 (en) | 2002-02-27 | 2006-02-28 | Xilinx, Inc. | Method and apparatus for synchronized buses |
US6934922B1 (en) | 2002-02-27 | 2005-08-23 | Xilinx, Inc. | Timing performance analysis |
US7111217B1 (en) | 2002-02-28 | 2006-09-19 | Xilinx, Inc. | Method and system for flexibly nesting JTAG TAP controllers for FPGA-based system-on-chip (SoC) |
US6839874B1 (en) | 2002-02-28 | 2005-01-04 | Xilinx, Inc. | Method and apparatus for testing an embedded device |
US7187709B1 (en) | 2002-03-01 | 2007-03-06 | Xilinx, Inc. | High speed configurable transceiver architecture |
US7111220B1 (en) | 2002-03-01 | 2006-09-19 | Xilinx, Inc. | Network physical layer with embedded multi-standard CRC generator |
US7088767B1 (en) | 2002-03-01 | 2006-08-08 | Xilinx, Inc. | Method and apparatus for operating a transceiver in different data rates |
US6961919B1 (en) | 2002-03-04 | 2005-11-01 | Xilinx, Inc. | Method of designing integrated circuit having both configurable and fixed logic circuitry |
US9170812B2 (en) | 2002-03-21 | 2015-10-27 | Pact Xpp Technologies Ag | Data processing system having integrated pipelined array data processor |
US8914590B2 (en) | 2002-08-07 | 2014-12-16 | Pact Xpp Technologies Ag | Data processing method and device |
US7493375B2 (en) | 2002-04-29 | 2009-02-17 | Qst Holding, Llc | Storage and delivery of device features |
US6777977B1 (en) * | 2002-05-01 | 2004-08-17 | Actel Corporation | Three input field programmable gate array logic circuit configurable as a three input look up table, a D-latch or a D flip-flop |
US6774667B1 (en) | 2002-05-09 | 2004-08-10 | Actel Corporation | Method and apparatus for a flexible chargepump scheme for field-programmable gate arrays |
US7660984B1 (en) | 2003-05-13 | 2010-02-09 | Quicksilver Technology | Method and system for achieving individualized protected space in an operating system |
US7328414B1 (en) | 2003-05-13 | 2008-02-05 | Qst Holdings, Llc | Method and system for creating and programming an adaptive computing engine |
US6973405B1 (en) | 2002-05-22 | 2005-12-06 | Xilinx, Inc. | Programmable interactive verification agent |
US7378867B1 (en) | 2002-06-04 | 2008-05-27 | Actel Corporation | Field-programmable gate array low voltage differential signaling driver utilizing two complimentary output buffers |
US6891394B1 (en) | 2002-06-04 | 2005-05-10 | Actel Corporation | Field-programmable gate array low voltage differential signaling driver utilizing two complimentary output buffers |
US6970012B2 (en) * | 2002-06-10 | 2005-11-29 | Xilinx, Inc. | Programmable logic device having heterogeneous programmable logic blocks |
US6772405B1 (en) | 2002-06-13 | 2004-08-03 | Xilinx, Inc. | Insertable block tile for interconnecting to a device embedded in an integrated circuit |
US6844757B2 (en) | 2002-06-28 | 2005-01-18 | Lattice Semiconductor Corp. | Converting bits to vectors in a programmable logic device |
US7129744B2 (en) * | 2003-10-23 | 2006-10-31 | Viciciv Technology | Programmable interconnect structures |
US7673273B2 (en) | 2002-07-08 | 2010-03-02 | Tier Logic, Inc. | MPGA products based on a prototype FPGA |
US20040004251A1 (en) * | 2002-07-08 | 2004-01-08 | Madurawe Raminda U. | Insulated-gate field-effect thin film transistors |
US7112994B2 (en) | 2002-07-08 | 2006-09-26 | Viciciv Technology | Three dimensional integrated circuits |
US7312109B2 (en) * | 2002-07-08 | 2007-12-25 | Viciciv, Inc. | Methods for fabricating fuse programmable three dimensional integrated circuits |
US6992503B2 (en) | 2002-07-08 | 2006-01-31 | Viciciv Technology | Programmable devices with convertibility to customizable devices |
US7085973B1 (en) | 2002-07-09 | 2006-08-01 | Xilinx, Inc. | Testing address lines of a memory controller |
US7657861B2 (en) | 2002-08-07 | 2010-02-02 | Pact Xpp Technologies Ag | Method and device for processing data |
WO2005010632A2 (en) * | 2003-06-17 | 2005-02-03 | Pact Xpp Technologies Ag | Data processing device and method |
WO2004021176A2 (de) | 2002-08-07 | 2004-03-11 | Pact Xpp Technologies Ag | Verfahren und vorrichtung zur datenverarbeitung |
US6765427B1 (en) | 2002-08-08 | 2004-07-20 | Actel Corporation | Method and apparatus for bootstrapping a programmable antifuse circuit |
US8108656B2 (en) | 2002-08-29 | 2012-01-31 | Qst Holdings, Llc | Task definition for specifying resource requirements |
US7043511B1 (en) | 2002-08-30 | 2006-05-09 | Lattice Semiconductor Corporation | Performing conditional operations in a programmable logic device |
US7434080B1 (en) | 2002-09-03 | 2008-10-07 | Actel Corporation | Apparatus for interfacing and testing a phase locked loop in a field programmable gate array |
US7099426B1 (en) | 2002-09-03 | 2006-08-29 | Xilinx, Inc. | Flexible channel bonding and clock correction operations on a multi-block data path |
JP4388895B2 (ja) | 2002-09-06 | 2009-12-24 | ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト | リコンフィギュアラブルなシーケンサ構造 |
US7092865B1 (en) | 2002-09-10 | 2006-08-15 | Xilinx, Inc. | Method and apparatus for timing modeling |
US6803787B1 (en) | 2002-09-25 | 2004-10-12 | Lattice Semiconductor Corp. | State machine in a programmable logic device |
US6750674B1 (en) | 2002-10-02 | 2004-06-15 | Actel Corporation | Carry chain for use between logic modules in a field programmable gate array |
US7812458B2 (en) * | 2007-11-19 | 2010-10-12 | Tier Logic, Inc. | Pad invariant FPGA and ASIC devices |
US6885218B1 (en) | 2002-10-08 | 2005-04-26 | Actel Corporation | Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA |
US7269814B1 (en) | 2002-10-08 | 2007-09-11 | Actel Corporation | Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA |
US8643162B2 (en) | 2007-11-19 | 2014-02-04 | Raminda Udaya Madurawe | Pads and pin-outs in three dimensional integrated circuits |
US7042756B2 (en) * | 2002-10-18 | 2006-05-09 | Viciciv Technology | Configurable storage device |
US7084666B2 (en) * | 2002-10-21 | 2006-08-01 | Viciciv Technology | Programmable interconnect structures |
US6937064B1 (en) * | 2002-10-24 | 2005-08-30 | Altera Corporation | Versatile logic element and logic array block |
US7937591B1 (en) | 2002-10-25 | 2011-05-03 | Qst Holdings, Llc | Method and system for providing a device which can be adapted on an ongoing basis |
US8276135B2 (en) * | 2002-11-07 | 2012-09-25 | Qst Holdings Llc | Profiling of software and circuit designs utilizing data operation analyses |
US6727726B1 (en) | 2002-11-12 | 2004-04-27 | Actel Corporation | Field programmable gate array architecture including a buffer module and a method of distributing buffer modules in a field programmable gate array |
US7225301B2 (en) | 2002-11-22 | 2007-05-29 | Quicksilver Technologies | External memory controller node |
US7111110B1 (en) * | 2002-12-10 | 2006-09-19 | Altera Corporation | Versatile RAM for programmable logic device |
US6946871B1 (en) | 2002-12-18 | 2005-09-20 | Actel Corporation | Multi-level routing architecture in a field programmable gate array having transmitters and receivers |
US7385420B1 (en) | 2002-12-27 | 2008-06-10 | Actel Corporation | Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks |
US6891396B1 (en) | 2002-12-27 | 2005-05-10 | Actel Corporation | Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks |
US7255437B2 (en) * | 2003-10-09 | 2007-08-14 | Howell Thomas A | Eyeglasses with activity monitoring |
US6825690B1 (en) | 2003-05-28 | 2004-11-30 | Actel Corporation | Clock tree network in a field programmable gate array |
US7375553B1 (en) | 2003-05-28 | 2008-05-20 | Actel Corporation | Clock tree network in a field programmable gate array |
US6838902B1 (en) * | 2003-05-28 | 2005-01-04 | Actel Corporation | Synchronous first-in/first-out block memory for a field programmable gate array |
US6867615B1 (en) | 2003-05-30 | 2005-03-15 | Actel Corporation | Dedicated input/output first in/first out module for a field programmable gate array |
US7385419B1 (en) * | 2003-05-30 | 2008-06-10 | Actel Corporation | Dedicated input/output first in/first out module for a field programmable gate array |
US7609297B2 (en) | 2003-06-25 | 2009-10-27 | Qst Holdings, Inc. | Configurable hardware based digital imaging apparatus |
US7693703B2 (en) * | 2003-08-01 | 2010-04-06 | Mentor Graphics Corporation | Configuration of reconfigurable interconnect portions |
US7421014B2 (en) * | 2003-09-11 | 2008-09-02 | Xilinx, Inc. | Channel bonding of a plurality of multi-gigabit transceivers |
US7019557B2 (en) * | 2003-12-24 | 2006-03-28 | Viciciv Technology | Look-up table based logic macro-cells |
US7176716B2 (en) * | 2003-12-24 | 2007-02-13 | Viciciv Technology | Look-up table structure with embedded carry logic |
US7317264B2 (en) * | 2003-11-25 | 2008-01-08 | Eaton Corporation | Method and apparatus to independently control contactors in a multiple contactor configuration |
US7030651B2 (en) * | 2003-12-04 | 2006-04-18 | Viciciv Technology | Programmable structured arrays |
US7336097B2 (en) * | 2003-12-24 | 2008-02-26 | Viciciv, Inc. | Look-up table structure with embedded carry logic |
US7176713B2 (en) * | 2004-01-05 | 2007-02-13 | Viciciv Technology | Integrated circuits with RAM and ROM fabrication options |
KR100564611B1 (ko) * | 2004-02-14 | 2006-03-29 | 삼성전자주식회사 | 하드 디스크 드라이브의 완충 구조체 |
US7030652B1 (en) | 2004-04-23 | 2006-04-18 | Altera Corporation | LUT-based logic element with support for Shannon decomposition and associated method |
US7489164B2 (en) * | 2004-05-17 | 2009-02-10 | Raminda Udaya Madurawe | Multi-port memory devices |
US8612772B1 (en) | 2004-09-10 | 2013-12-17 | Altera Corporation | Security core using soft key |
US8566616B1 (en) | 2004-09-10 | 2013-10-22 | Altera Corporation | Method and apparatus for protecting designs in SRAM-based programmable logic devices and the like |
DE102005048525A1 (de) * | 2005-10-07 | 2007-04-12 | Micronas Gmbh | Schaltungsarchitektur für eine integrierte Schaltung |
JP2009524134A (ja) | 2006-01-18 | 2009-06-25 | ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト | ハードウェア定義方法 |
US7486111B2 (en) * | 2006-03-08 | 2009-02-03 | Tier Logic, Inc. | Programmable logic devices comprising time multiplexed programmable interconnect |
US7555424B2 (en) | 2006-03-16 | 2009-06-30 | Quickturn Design Systems, Inc. | Method and apparatus for rewinding emulated memory circuits |
US8067970B2 (en) * | 2006-03-31 | 2011-11-29 | Masleid Robert P | Multi-write memory circuit with a data input and a clock input |
US20080024165A1 (en) * | 2006-07-28 | 2008-01-31 | Raminda Udaya Madurawe | Configurable embedded multi-port memory |
US20080182021A1 (en) * | 2007-01-31 | 2008-07-31 | Simka Harsono S | Continuous ultra-thin copper film formed using a low thermal budget |
US7508231B2 (en) | 2007-03-09 | 2009-03-24 | Altera Corporation | Programmable logic device having redundancy with logic element granularity |
US7456653B2 (en) * | 2007-03-09 | 2008-11-25 | Altera Corporation | Programmable logic device having logic array block interconnect lines that can interconnect logic elements in different logic blocks |
US7536615B1 (en) | 2007-03-26 | 2009-05-19 | Lattice Semiconductor Corporation | Logic analyzer systems and methods for programmable logic devices |
US7743296B1 (en) | 2007-03-26 | 2010-06-22 | Lattice Semiconductor Corporation | Logic analyzer systems and methods for programmable logic devices |
US7635988B2 (en) * | 2007-11-19 | 2009-12-22 | Tier Logic, Inc. | Multi-port thin-film memory devices |
US20090128189A1 (en) * | 2007-11-19 | 2009-05-21 | Raminda Udaya Madurawe | Three dimensional programmable devices |
US7602213B2 (en) * | 2007-12-26 | 2009-10-13 | Tier Logic, Inc. | Using programmable latch to implement logic |
US7573293B2 (en) * | 2007-12-26 | 2009-08-11 | Tier Logic, Inc. | Programmable logic based latches and shift registers |
US7795913B2 (en) * | 2007-12-26 | 2010-09-14 | Tier Logic | Programmable latch based multiplier |
US7573294B2 (en) * | 2007-12-26 | 2009-08-11 | Tier Logic, Inc. | Programmable logic based latches and shift registers |
US7735045B1 (en) * | 2008-03-12 | 2010-06-08 | Xilinx, Inc. | Method and apparatus for mapping flip-flop logic onto shift register logic |
US20100272811A1 (en) * | 2008-07-23 | 2010-10-28 | Alkermes,Inc. | Complex of trospium and pharmaceutical compositions thereof |
US8230375B2 (en) | 2008-09-14 | 2012-07-24 | Raminda Udaya Madurawe | Automated metal pattern generation for integrated circuits |
US8661394B1 (en) | 2008-09-24 | 2014-02-25 | Iowa State University Research Foundation, Inc. | Depth-optimal mapping of logic chains in reconfigurable fabrics |
US8438522B1 (en) | 2008-09-24 | 2013-05-07 | Iowa State University Research Foundation, Inc. | Logic element architecture for generic logic chains in programmable devices |
US8159266B1 (en) | 2010-11-16 | 2012-04-17 | Raminda Udaya Madurawe | Metal configurable integrated circuits |
US8159265B1 (en) | 2010-11-16 | 2012-04-17 | Raminda Udaya Madurawe | Memory for metal configurable integrated circuits |
US8159268B1 (en) | 2010-11-16 | 2012-04-17 | Raminda Udaya Madurawe | Interconnect structures for metal configurable integrated circuits |
US8959010B1 (en) | 2011-12-08 | 2015-02-17 | Cadence Design Systems, Inc. | Emulation system with improved reliability of interconnect and a method for programming such interconnect |
US8743735B1 (en) | 2012-01-18 | 2014-06-03 | Cadence Design Systems, Inc. | Emulation system for verifying a network device |
CN102611431B (zh) * | 2012-03-08 | 2014-12-24 | 无锡华大国奇科技有限公司 | 带组合逻辑通路的寄存器 |
US8595683B1 (en) | 2012-04-12 | 2013-11-26 | Cadence Design Systems, Inc. | Generating user clocks for a prototyping environment |
US10425082B2 (en) | 2015-10-27 | 2019-09-24 | Andapt, Inc. | Adaptive analog blocks with digital wrappers integrated onto programmable fabric |
US20230153597A1 (en) * | 2021-11-18 | 2023-05-18 | Analog Intelligent Design Inc. | Design and fabrication methods of runtime self-tuning analog integrated circuits using machine learning |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0031431B1 (en) * | 1979-12-26 | 1984-03-07 | International Business Machines Corporation | Programmable sequential logic array mechanism |
GB2138188A (en) | 1983-04-14 | 1984-10-17 | Control Data Corp | Soft programmable logic array |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4911432A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * | 1972-05-30 | 1974-01-31 | ||
US3967251A (en) * | 1975-04-17 | 1976-06-29 | Xerox Corporation | User variable computer memory module |
-
1985
- 1985-02-27 US US06/706,429 patent/US4706216A/en not_active Expired - Lifetime
-
1986
- 1986-02-14 JP JP61030608A patent/JPS61224520A/ja active Granted
- 1986-02-26 GB GB8604761A patent/GB2171546B/en not_active Expired
- 1986-02-26 CA CA000502720A patent/CA1255364A/en not_active Expired
- 1986-02-27 DE DE19863606406 patent/DE3606406A1/de active Granted
- 1986-02-27 DE DE3645224A patent/DE3645224C2/de not_active Expired - Lifetime
- 1986-02-27 DE DE3645221A patent/DE3645221C2/de not_active Expired - Lifetime
- 1986-03-28 US US06/845,287 patent/US4758985A/en not_active Expired - Lifetime
-
1991
- 1991-10-09 JP JP3290528A patent/JPH0645912A/ja active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0031431B1 (en) * | 1979-12-26 | 1984-03-07 | International Business Machines Corporation | Programmable sequential logic array mechanism |
GB2138188A (en) | 1983-04-14 | 1984-10-17 | Control Data Corp | Soft programmable logic array |
Non-Patent Citations (3)
Title |
---|
Elektronik, H. 23, 1982, S. 73-74 |
Tietze, Schenk: Halbleiterschaltungstechnik, 6. Aufl., Springer-Verlag Berlin u.a., 1983, S. 264-268 |
TIETZE, SCHENK: Halbleiterschaltungstechnik, 6.Aufl., Springer-Verlag 1983, S.264-268 * |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0324640A3 (en) * | 1988-01-14 | 1991-08-28 | Kawasaki Steel Corporation | Programmable logic device |
EP0420390A3 (en) * | 1989-09-29 | 1991-09-04 | Sgs-Thomson Microelectronics, Inc. (A Delaware Corp.) | Configuration memory for programmable logic device |
EP0433757A3 (en) * | 1989-12-19 | 1992-08-26 | Bull Hn Information Systems Inc. | Edge triggered d-type flip-flop scan latch cell with recirculation capability |
EP0476159A1 (en) * | 1990-09-15 | 1992-03-25 | International Business Machines Corporation | Programmable neural logic device |
US5218245A (en) * | 1990-09-15 | 1993-06-08 | International Business Machines Corporation | Programmable neural logic device |
DE4327660A1 (de) * | 1992-08-20 | 1994-02-24 | Mitsubishi Electric Corp | Vorrichtung zum Herstellen einer und Herstellungsverfahren für eine integrierte Halbleiterschaltungsvorrichtung und elektronische Schaltungsvorrichtung |
US5384275A (en) * | 1992-08-20 | 1995-01-24 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a semiconductor integrated circuit device, and an electronic circuit device |
DE9417335U1 (de) * | 1994-10-28 | 1994-12-15 | Bäuerle, Karin, 75181 Pforzheim | Koppelbaustein |
US5999086A (en) * | 1996-09-27 | 1999-12-07 | Siemens Aktiengesellschaft | Circuit arrangement with combinatorial blocks arranged between registers |
US6516334B1 (en) | 1996-09-27 | 2003-02-04 | Siemens Aktiengesellschaft | Circuit arrangement with combinatorial blocks arranged between registers |
Also Published As
Publication number | Publication date |
---|---|
DE3645221C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1992-04-23 |
JPS61224520A (ja) | 1986-10-06 |
GB2171546B (en) | 1989-10-18 |
US4706216A (en) | 1987-11-10 |
GB2171546A (en) | 1986-08-28 |
CA1255364A (en) | 1989-06-06 |
GB8604761D0 (en) | 1986-04-03 |
US4758985A (en) | 1988-07-19 |
JPH0446488B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1992-07-30 |
JPH0645912A (ja) | 1994-02-18 |
DE3645224C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1992-02-20 |
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