GB2290895A

GB2290895A - Shift register with comparator

Info

Publication number: GB2290895A
Application number: GB9507370A
Authority: GB
Inventors: Alexander Roger Deas
Original assignee: Memory Corp PLC
Current assignee: Memory Corp PLC
Priority date: 1995-04-10
Filing date: 1995-04-10
Publication date: 1996-01-10
Also published as: WO1996032677A1; TW279985B; GB9507370D0

Abstract

A storage register for use with a circuit for intercepting and replacing faulty cells where the storage register comprises a shift register with a latch structure to enable it to store data and present it to a comparator circuit. The shift register comprising a first stage and a second stage inverter circuit such that on application of the hold controlling signal the integrity of the data at the output of the second stage inverter is retained. An output transistor stage is controlled by the ADDR data bit and its complement ADDR and functions as the comparator and is equivalent to an Exclusive OR function. <IMAGE>

Description

Improved Shift Register with Comparator The present invention relates to the field of shift registers for use in partial memory engines.

The present invention is applicable in particular, though not exclusively, to electronic circuits combining shift registers with comparators.

ShiR registers are designed for enabling the movement of a sequence of data bits. As a result, they are suited to applications requiring the storage of data in registers for comparison with incoming data. One such application is in partial memory engines. In a partial memory engine (PME) there is usually a non-volatile store to retain data relating to faulty memory locations. On power-up of the device the controller within the PME loads the data from the non-volatile store into a register. The register presents the data to a comparator which compares the bits of the incoming address with the data stored in the register (which was downloaded from the non-volatile store). If there is a match between the data stored and the incoming address then the comparator output enables additional logic to substitute for the faulty location or locations.

The present invention relates to an improved storage and comparison circuit in a PME which performs the same function as previous storage and comparison circuits but with a reduced gate count; that is, it uses fewer gates.

The present invention provides a storage register for use in a partial memory engine where the storage register comprises a shift register with a latch structure to enable it to store data and present it to some comparator means.

The present invention also provides for each cell in the storage register having an efficient structure comprising: a first stage and a second stage inverter circuit, input controlling transistors before each inverter circuit, and a hold controlling transistor between the output of the second stage inverter and the input of the first stage inverter, such that on application of the hold controlling signal the integrity of the data at the output of the second stage inverter is retained.

The present invention may be used as a comparator circuit where the storage register is combined with an Exclusive OR logical circuit to compare incoming data with data stored on the storage register. The Exclusive OR logical circuit may also be combined with a shit register cell on a bit level, where the comparator circuit uses both the data stored in the shift register and the logical complement ofthe data which is also stored in the register to compare with the incoming data and the logical complement ofthe incoming data, thus producing an Exclusive OR logical function.

The advantages of the present invention include the reduced amount of silicon real estate necessary to perform the function of a storage and comparison circuit. This gives rise to the further advantage of being able to cope with more errors on each integrated circuit than with the previous circuit.

A number of different methods have been used in the past to perform the store and compare function within a partial memory engine system. To explain how the previous methods worked and to describe the present invention more fully, reference will now be made by way of example to Figures 1, 2, 3, 4, 5, and 6, where: Figure 1 shows a standard (prior art) embodiment ofpart of a PME; Figure 2 shows a block diagram ofpart of a PME using the present invention; Figure 3 shows a standard (prior art) shift register with a latching function; Figure 4 shows a conventional (prior art) Exclusive NOR logic gate; Figure 5 shows an improved shift register with a latching function; and Figure 6 shows a detailed drawing ofthe improved shift register / comparator.

Figure 1 shows a standard circuit for downloading data from a non-volatile store. An address counter increments an address which is used to access data in the non-volatile store.

The address counter is also connected to an address decoder which is used to access the particular register that will store the address which will be downloaded from the nonvolatile store. A control block is used to download the address from the non-volatile store to the register and then increment the counter. The process continues until all of the data has been downloaded. A comparator (which usually consists of a an Exclusive OR logic gate) compares the contents of each register (each stored address) with the incoming address. If the incoming address matches the contents of any one of the registers then the output ofthe comparator indicates that a match has occurred.

Figure 2 shows a block diagram of part of a PME using the present invention. There is a counter to access the correct location in the non-volatile store. The counter is driven by a clock, which also goes to a shift register. The data relating to each address stored in the non-volatile store is downloaded to the shift register in a serial manner (controlled by the clock) and held by the shift register. The data relating to each address is presented to the input of a comparator which compares the stored data with the bits ofthe incoming address.

In Figure 3 a standard master/slave shift register arrangement with the necessary means to retain data is shown. This arrangement uses four inverters and four transistors, and is wellknown in the art.

Figure 4 shows a conventional exclusive NOR logic gate. The exclusive NOR arrangement uses two inverters and eight transistors.

The arrangement of Figure 5 is a simplified version of Figure 3, but it works in exactly the same way. The circuit of Figure 5 only uses two inverters and three transistors, thus representing a saving of two inverters and one transistor compared with the conventional shift register of Figure 3. Two of the inputs (4)1 and 42) are used to clock the data through the shift register. The third input, the HOLD input, is used to retain the data value stored.

A first stage inverter produces the logical complement of the data input, the second stage inverter restores the data to its correct value. The HOLD signal controls a transistor which connects the output of the second stage inverter to the input of the first stage inverter.

When the HOLD signal is active the effect ofthe arrangement is that the output stage of the second inverter is continually restored to its 11l level.

Any saving in the number of logic gates which are used in a shift register is potentially very important because in applications such as PME systems the basic shift register cell is replicated hundreds or perhaps even thousands of times. By reducing the number of gates in the basic building block the cumulated total saving may be enormous.

The arrangement of Figure 6 is a combination of the improved shift register of Figure 5 and an Exclusive OR logic function. The resulting circuit operates as a storage and comparison circuit.

In Figures 3 and 5, 4)1 and 4)2 are two-phase, non-overlapping clock signals.

In the circuit of Figure 6, CKl and CK2 are the equivalent of 4)1 and 4)2 respectively in Figures 3 and 5. The input to the shift register is SDI, which is the value of the address or data stored. In this embodiment of the invention addresses are being stored. The HOLD input is used to ensure that the contents of the shift register are continually refreshed: while the HOLD input is active the output ofthe final inverter drives the input to the first inverter.

This ensures that data integrity is retained. Thus for operation as part of a PME system it is essential that the HOLD input is active at all times. The ADDR input refers to the incoming data or address bit which is to be compared with the contents of the shift register. In this embodiment no comparison as such is performed. This is because the ADDR data bit and its logical complement ADDR (bar) are used to control the output transistors. If ADDR is active then the logical complement of SDI is sent to the output; if the logical complement of ADDR is active then SDI is sent to the output of the system. This is equivalent to an Exclusive OR logical function. The circuit requires both ADDR and its logical complement to be presented to the comparator. Despite the extra bits due to the need for ADDR (bar), however, the circuit still uses fewer gates than the standard circuit represented by the block diagram of Figure 1.

It will be appreciated that various modifications may be made to the above described embodiments within the scope ofthe present invention.

Claims

Claims:

1 A storage register for use in a partial memory engine characterised in that the storage register comprises a shift register with a latch structure to enable it to store data and present it to some comparator means.

2 A storage register according to claim 1, where each cell in that register has an efficient structure comprising: a first stage and a second stage inverter circuit, input controlling transistors before each inverter circuit, and a hold controlling transistor between the output ofthe second stage inverter and the input of the first stage inverter, such that on application of the hold controlling signal the integrity ofthe data at the output ofthe second stage inverter is retained.

3 A comparator circuit where the storage register of any preceding claim is combined with an Exclusive OR logical circuit to compare incoming data with data stored on the storage register.

4 A comparator circuit according to claim 3, where the Exclusive OR logical circuit is combined with a shift register cell on a bit level, characterised in that the comparator circuit uses both the data stored in the shift register and the logical complement of the data which is also stored in the register to compare with the incoming data and the logical complement ofthe incoming data, thus producing an Exclusive OR logical function.