IT1206265B - Complesso di memoria ram a doppia porta con organizzazione variabile a misura di utente - Google Patents

Complesso di memoria ram a doppia porta con organizzazione variabile a misura di utente

Info

Publication number
IT1206265B
IT1206265B IT8747682A IT4768287A IT1206265B IT 1206265 B IT1206265 B IT 1206265B IT 8747682 A IT8747682 A IT 8747682A IT 4768287 A IT4768287 A IT 4768287A IT 1206265 B IT1206265 B IT 1206265B
Authority
IT
Italy
Prior art keywords
user
ram memory
double door
based variable
memory complex
Prior art date
Application number
IT8747682A
Other languages
English (en)
Other versions
IT8747682A0 (it
Inventor
Gelsomini Tito
Fiorentino Pasqualino
Original Assignee
Texas Instruments Italia Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Italia Spa filed Critical Texas Instruments Italia Spa
Priority to IT8747682A priority Critical patent/IT1206265B/it
Publication of IT8747682A0 publication Critical patent/IT8747682A0/it
Priority to US07/148,457 priority patent/US4893280A/en
Priority to JP63044093A priority patent/JP2625141B2/ja
Application granted granted Critical
Publication of IT1206265B publication Critical patent/IT1206265B/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
IT8747682A 1987-02-27 1987-02-27 Complesso di memoria ram a doppia porta con organizzazione variabile a misura di utente IT1206265B (it)

Priority Applications (3)

Application Number Priority Date Filing Date Title
IT8747682A IT1206265B (it) 1987-02-27 1987-02-27 Complesso di memoria ram a doppia porta con organizzazione variabile a misura di utente
US07/148,457 US4893280A (en) 1987-02-27 1988-01-26 Dual port random access memory having variably customized organization of memory bit units
JP63044093A JP2625141B2 (ja) 1987-02-27 1988-02-26 デュアルポートｒａｍメモリ装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8747682A IT1206265B (it) 1987-02-27 1987-02-27 Complesso di memoria ram a doppia porta con organizzazione variabile a misura di utente

Publications (2)

Publication Number Publication Date
IT8747682A0 IT8747682A0 (it) 1987-02-27
IT1206265B true IT1206265B (it) 1989-04-14

Family

ID=11261876

Family Applications (1)

Application Number Title Priority Date Filing Date
IT8747682A IT1206265B (it) 1987-02-27 1987-02-27 Complesso di memoria ram a doppia porta con organizzazione variabile a misura di utente

Country Status (3)

Country Link
US (1) US4893280A (it)
JP (1) JP2625141B2 (it)
IT (1) IT1206265B (it)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5146572A (en) * 1980-11-17 1992-09-08 International Business Machines Corporation Multiple data format interface
JPH02292647A (ja) * 1989-05-02 1990-12-04 Toshiba Corp 半導体記憶装置
EP0407697A1 (en) * 1989-07-10 1991-01-16 Seiko Epson Corporation Memory apparatus
US5105425A (en) * 1989-12-29 1992-04-14 Westinghouse Electric Corp. Adaptive or fault tolerant full wafer nonvolatile memory
US5142540A (en) * 1990-03-13 1992-08-25 Glasser Lance A Multipart memory apparatus with error detection
US5355335A (en) * 1991-06-25 1994-10-11 Fujitsu Limited Semiconductor memory device having a plurality of writing and reading ports for decreasing hardware amount
US5422998A (en) * 1993-11-15 1995-06-06 Margolin; Jed Video memory with flash fill
JPH08212132A (ja) * 1995-02-07 1996-08-20 Mitsubishi Electric Corp 記憶装置
US6020760A (en) * 1997-07-16 2000-02-01 Altera Corporation I/O buffer circuit with pin multiplexing
US6034857A (en) * 1997-07-16 2000-03-07 Altera Corporation Input/output buffer with overcurrent protection circuit
US6011744A (en) * 1997-07-16 2000-01-04 Altera Corporation Programmable logic device with multi-port memory
US5991208A (en) * 1998-05-22 1999-11-23 International Business Machines Corporation Write multiplexer apparatus and method for multiple write port programmable memory
US5991224A (en) * 1998-05-22 1999-11-23 International Business Machines Corporation Global wire management apparatus and method for a multiple-port random access memory
US6882562B2 (en) * 2001-11-01 2005-04-19 Agilent Technologies, Inc. Method and apparatus for providing pseudo 2-port RAM functionality using a 1-port memory cell
US10318904B2 (en) 2016-05-06 2019-06-11 General Electric Company Computing system to control the use of physical state attainment of assets to meet temporal performance criteria

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4541076A (en) * 1982-05-13 1985-09-10 Storage Technology Corporation Dual port CMOS random access memory
US4706216A (en) * 1985-02-27 1987-11-10 Xilinx, Inc. Configurable logic element

Also Published As

Publication number Publication date
US4893280A (en) 1990-01-09
IT8747682A0 (it) 1987-02-27
JPS63308784A (ja) 1988-12-16
JP2625141B2 (ja) 1997-07-02

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Legal Events

Date Code Title Description
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19960119