DE19750884B4 - Halbleiterspeichervorrichtung - Google Patents

Halbleiterspeichervorrichtung Download PDF

Info

Publication number
DE19750884B4
DE19750884B4 DE19750884A DE19750884A DE19750884B4 DE 19750884 B4 DE19750884 B4 DE 19750884B4 DE 19750884 A DE19750884 A DE 19750884A DE 19750884 A DE19750884 A DE 19750884A DE 19750884 B4 DE19750884 B4 DE 19750884B4
Authority
DE
Germany
Prior art keywords
bit lines
data
circuit
sense amplifier
bit line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE19750884A
Other languages
German (de)
English (en)
Other versions
DE19750884A1 (de
Inventor
Yoshihiro Kawasaki Takemae
Masao Kawasaki Taguchi
Masao Kawasaki Nakano
Hirohiko Kawasaki Mochizuki
Hiroyoshi Kawasaki Tomita
Yasurou Kawasaki Matsuzaki
Tadao Kawasaki Aikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Socionext Inc
Original Assignee
Fujitsu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Semiconductor Ltd filed Critical Fujitsu Semiconductor Ltd
Publication of DE19750884A1 publication Critical patent/DE19750884A1/de
Application granted granted Critical
Publication of DE19750884B4 publication Critical patent/DE19750884B4/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)
DE19750884A 1996-12-25 1997-11-18 Halbleiterspeichervorrichtung Expired - Lifetime DE19750884B4 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP34603296 1996-12-25
JPP8-346032 1996-12-25
JP14231097A JP4154006B2 (ja) 1996-12-25 1997-05-30 半導体記憶装置
JPP9-142310 1997-05-30

Publications (2)

Publication Number Publication Date
DE19750884A1 DE19750884A1 (de) 1998-07-09
DE19750884B4 true DE19750884B4 (de) 2010-01-21

Family

ID=26474362

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19750884A Expired - Lifetime DE19750884B4 (de) 1996-12-25 1997-11-18 Halbleiterspeichervorrichtung

Country Status (6)

Country Link
US (1) US6154405A (ko)
JP (1) JP4154006B2 (ko)
KR (1) KR100286500B1 (ko)
DE (1) DE19750884B4 (ko)
GB (1) GB2320778B (ko)
TW (1) TW344896B (ko)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6016390A (en) * 1998-01-29 2000-01-18 Artisan Components, Inc. Method and apparatus for eliminating bitline voltage offsets in memory devices
KR100732287B1 (ko) * 1999-04-08 2007-06-25 주식회사 하이닉스반도체 패킷 명령어 구동형 반도체 메모리 장치
JP5034133B2 (ja) * 2000-02-29 2012-09-26 富士通セミコンダクター株式会社 半導体記憶装置
US7007187B1 (en) * 2000-06-30 2006-02-28 Intel Corporation Method and apparatus for an integrated circuit having flexible-ratio frequency domain cross-overs
JP2002063788A (ja) * 2000-08-21 2002-02-28 Fujitsu Ltd 半導体記憶装置
KR100403612B1 (ko) * 2000-11-08 2003-11-01 삼성전자주식회사 비트라인 프리차아지 시간(ｔＲＰ)을 개선하는 메모리 셀어레이 구조를 갖는 반도체 메모리 장치 및 그 개선 방법
JP4329919B2 (ja) * 2001-03-13 2009-09-09 Ｏｋｉセミコンダクタ株式会社 半導体メモリおよび半導体メモリの駆動方法
KR100600056B1 (ko) * 2004-10-30 2006-07-13 주식회사 하이닉스반도체 저 전압용 반도체 메모리 장치
US7764540B2 (en) * 2006-03-01 2010-07-27 Renesas Technology Corp. Semiconductor memory device
US20090296514A1 (en) * 2008-05-29 2009-12-03 Chih-Hui Yeh Method for accessing a memory chip
JP2011023079A (ja) * 2009-07-17 2011-02-03 Renesas Electronics Corp 半導体装置及びデータの読み出し方法
KR20140028542A (ko) * 2012-08-29 2014-03-10 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그 동작 방법
WO2015170220A1 (en) * 2014-05-09 2015-11-12 Semiconductor Energy Laboratory Co., Ltd. Memory device and electronic device
US10325648B2 (en) 2016-12-14 2019-06-18 Qualcomm Incorporated Write driver scheme for bit-writable memories

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5339274A (en) * 1992-10-30 1994-08-16 International Business Machines Corporation Variable bitline precharge voltage sensing technique for DRAM structures
US5539696A (en) * 1994-01-31 1996-07-23 Patel; Vipul C. Method and apparatus for writing data in a synchronous memory having column independent sections and a method and apparatus for performing write mask operations

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5873095A (ja) * 1981-10-23 1983-05-02 Toshiba Corp ダイナミツク型メモリ装置
JPS59120597U (ja) * 1983-01-31 1984-08-14 カ−ル事務器株式会社 パンチ
JPS5963091A (ja) * 1982-09-30 1984-04-10 Fujitsu Ltd スタテイツクメモリ回路
JPH0664907B2 (ja) * 1985-06-26 1994-08-22 株式会社日立製作所 ダイナミツク型ｒａｍ
JP3057747B2 (ja) * 1990-11-01 2000-07-04 日本電気株式会社 半導体メモリ装置
JP3160316B2 (ja) * 1991-07-25 2001-04-25 株式会社東芝 不揮発性半導体記憶装置
CA2097308A1 (en) * 1991-10-01 1993-04-02 Terrie Frane Memory write protection method and apparatus
US5406516A (en) * 1992-01-17 1995-04-11 Sharp Kabushiki Kaisha Semiconductor memory device
JP3072871B2 (ja) * 1992-03-19 2000-08-07 株式会社東芝 半導体メモリ装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5339274A (en) * 1992-10-30 1994-08-16 International Business Machines Corporation Variable bitline precharge voltage sensing technique for DRAM structures
US5539696A (en) * 1994-01-31 1996-07-23 Patel; Vipul C. Method and apparatus for writing data in a synchronous memory having column independent sections and a method and apparatus for performing write mask operations

Also Published As

Publication number Publication date
JPH10241368A (ja) 1998-09-11
GB9718939D0 (en) 1997-11-12
KR19980063480A (ko) 1998-10-07
JP4154006B2 (ja) 2008-09-24
TW344896B (en) 1998-11-11
GB2320778A (en) 1998-07-01
GB2320778B (en) 2001-06-27
US6154405A (en) 2000-11-28
DE19750884A1 (de) 1998-07-09
KR100286500B1 (ko) 2001-04-16

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8127 New person/name/address of the applicant

Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP

8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP

8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE

R082 Change of representative

Representative=s name: REICHERT & LINDNER PARTNERSCHAFT PATENTANWAELT, DE

R081 Change of applicant/patentee

Owner name: SOCIONEXT INC., YOKOHAMA-SHI, JP

Free format text: FORMER OWNER: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP

Effective date: 20150512

R082 Change of representative

Representative=s name: REICHERT & LINDNER PARTNERSCHAFT PATENTANWAELT, DE

Effective date: 20150512

R071 Expiry of right