DE3687533T2 - Statische halbleiterspeicheranordnung. - Google Patents

Statische halbleiterspeicheranordnung.

Info

Publication number
DE3687533T2
DE3687533T2 DE8686103993T DE3687533T DE3687533T2 DE 3687533 T2 DE3687533 T2 DE 3687533T2 DE 8686103993 T DE8686103993 T DE 8686103993T DE 3687533 T DE3687533 T DE 3687533T DE 3687533 T2 DE3687533 T2 DE 3687533T2
Authority
DE
Germany
Prior art keywords
semiconductor memory
memory arrangement
static semiconductor
static
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8686103993T
Other languages
English (en)
Other versions
DE3687533D1 (de
Inventor
Takayuki Ohtani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP60066901A external-priority patent/JPS61227288A/ja
Priority claimed from JP60197129A external-priority patent/JPH0750554B2/ja
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3687533D1 publication Critical patent/DE3687533D1/de
Publication of DE3687533T2 publication Critical patent/DE3687533T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
DE8686103993T 1985-03-30 1986-03-24 Statische halbleiterspeicheranordnung. Expired - Lifetime DE3687533T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP60066901A JPS61227288A (ja) 1985-03-30 1985-03-30 半導体記憶装置
JP60197129A JPH0750554B2 (ja) 1985-09-06 1985-09-06 スタテイツク型メモリ

Publications (2)

Publication Number Publication Date
DE3687533D1 DE3687533D1 (de) 1993-03-04
DE3687533T2 true DE3687533T2 (de) 1993-06-09

Family

ID=26408108

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686103993T Expired - Lifetime DE3687533T2 (de) 1985-03-30 1986-03-24 Statische halbleiterspeicheranordnung.

Country Status (3)

Country Link
US (1) US4730279A (de)
EP (1) EP0196586B1 (de)
DE (1) DE3687533T2 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6026043A (en) * 1997-09-16 2000-02-15 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device with reduced power consumption and stable operation in data holding state

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS639097A (ja) * 1986-06-30 1988-01-14 Sony Corp スタテイツクｒａｍ
US4961168A (en) * 1987-02-24 1990-10-02 Texas Instruments Incorporated Bipolar-CMOS static random access memory device with bit line bias control
DE3874455T2 (de) * 1987-07-29 1993-04-08 Toshiba Kawasaki Kk Nichtfluechtiger halbleiterspeicher.
JPH0682520B2 (ja) * 1987-07-31 1994-10-19 株式会社東芝 半導体メモリ
JPS6446288A (en) * 1987-08-13 1989-02-20 Toshiba Corp Semiconductor memory device
US4875196A (en) * 1987-09-08 1989-10-17 Sharp Microelectronic Technology, Inc. Method of operating data buffer apparatus
GB2213009B (en) * 1987-11-27 1992-02-05 Sony Corp Memories having bit line loads controlled by p-channel mis transistors
JPH0821234B2 (ja) * 1988-01-14 1996-03-04 三菱電機株式会社 ダイナミック型半導体記憶装置およびその制御方法
US4866674A (en) * 1988-02-16 1989-09-12 Texas Instruments Incorporated Bitline pull-up circuit for a BiCMOS read/write memory
US5046052A (en) * 1988-06-01 1991-09-03 Sony Corporation Internal low voltage transformation circuit of static random access memory
US4975877A (en) * 1988-10-20 1990-12-04 Logic Devices Incorporated Static semiconductor memory with improved write recovery and column address circuitry
US5193076A (en) * 1988-12-22 1993-03-09 Texas Instruments Incorporated Control of sense amplifier latch timing
JPH07105160B2 (ja) * 1989-05-20 1995-11-13 東芝マイクロエレクトロニクス株式会社 半導体記憶装置
US4969125A (en) * 1989-06-23 1990-11-06 International Business Machines Corporation Asynchronous segmented precharge architecture
DE69023456T2 (de) * 1989-10-30 1996-06-20 Ibm Bitdekodierungsschema für Speichermatrizen.
US5022010A (en) * 1989-10-30 1991-06-04 International Business Machines Corporation Word decoder for a memory array
JP2892757B2 (ja) * 1990-03-23 1999-05-17 三菱電機株式会社 半導体集積回路装置
WO1991018394A1 (en) * 1990-05-17 1991-11-28 International Business Machines Corporation Read/write/restore circuit for memory arrays
JP2596180B2 (ja) * 1990-05-28 1997-04-02 日本電気株式会社 半導体集積メモリ回路
US5173877A (en) * 1990-12-10 1992-12-22 Motorola, Inc. BICMOS combined bit line load and write gate for a memory
US5257227A (en) * 1991-01-11 1993-10-26 International Business Machines Corp. Bipolar FET read-write circuit for memory
JP3210355B2 (ja) * 1991-03-04 2001-09-17 株式会社東芝 不揮発性半導体記憶装置
JP2785540B2 (ja) * 1991-09-30 1998-08-13 松下電器産業株式会社 半導体メモリの読み出し回路
KR930020442A (ko) * 1992-03-13 1993-10-19 김광호 데이타의 고속 액세스가 이루어지는 비트라인 제어회로
JPH087573A (ja) * 1994-06-14 1996-01-12 Mitsubishi Electric Corp 半導体記憶装置と、そのデータの読出および書込方法
JP3606951B2 (ja) * 1995-06-26 2005-01-05 株式会社ルネサステクノロジ 半導体記憶装置
CN1202530C (zh) * 1998-04-01 2005-05-18 三菱电机株式会社 在低电源电压下高速动作的静态型半导体存储装置
US6608786B2 (en) * 2001-03-30 2003-08-19 Intel Corporation Apparatus and method for a memory storage cell leakage cancellation scheme
KR100615596B1 (ko) * 2004-12-22 2006-08-25 삼성전자주식회사 반도체 장치
JP5763004B2 (ja) * 2012-03-26 2015-08-12 株式会社東芝 不揮発性半導体記憶装置
US9842631B2 (en) * 2012-12-14 2017-12-12 Nvidia Corporation Mitigating external influences on long signal lines

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6027113B2 (ja) * 1980-02-13 1985-06-27 日本電気株式会社 プリチャ−ジ装置
JPS5836504B2 (ja) * 1980-02-22 1983-08-09 富士通株式会社 半導体記憶装置
JPS592997B2 (ja) * 1980-05-22 1984-01-21 富士通株式会社 スタテイツクメモリ
US4355377A (en) * 1980-06-30 1982-10-19 Inmos Corporation Asynchronously equillibrated and pre-charged static ram
US4494221A (en) * 1982-03-03 1985-01-15 Inmos Corporation Bit line precharging and equilibrating circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6026043A (en) * 1997-09-16 2000-02-15 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device with reduced power consumption and stable operation in data holding state
DE19815887C2 (de) * 1997-09-16 2000-04-27 Mitsubishi Electric Corp Halbleiterspeichereinrichtung mit einem Normalbetriebsmodus und einem Eigenauffrischungsmodus und einem reduzierten Stromverbrauch und stabilen Betrieb in einem Datenhaltezustand
US6185144B1 (en) 1997-09-16 2001-02-06 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device with reduced power consumption and stable operation in data holding state

Also Published As

Publication number Publication date
EP0196586B1 (de) 1993-01-20
US4730279A (en) 1988-03-08
EP0196586A3 (en) 1989-07-05
DE3687533D1 (de) 1993-03-04
EP0196586A2 (de) 1986-10-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)