JPS59120597U - パンチ - Google Patents
パンチInfo
- Publication number
- JPS59120597U JPS59120597U JP1983012987U JP1298783U JPS59120597U JP S59120597 U JPS59120597 U JP S59120597U JP 1983012987 U JP1983012987 U JP 1983012987U JP 1298783 U JP1298783 U JP 1298783U JP S59120597 U JPS59120597 U JP S59120597U
- Authority
- JP
- Japan
- Prior art keywords
- base
- punch
- lever
- rod blade
- rod
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
Landscapes
- Engineering & Computer Science (AREA)
- Databases & Information Systems (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Perforating, Stamping-Out Or Severing By Means Other Than Cutting (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
め要約のデータは記録されません。
Description
第１図は本考案の一実施例の斜視図、第２図は第１図の
ものを右方から見た中央断面図、第３図は第１図および
第２図のものを分解状態で示した斜視図である。 １・・−、！、２・・・レバー、７・・田ツド刃、９・
・・溝、１０・・・ロッド刃保持プレート、１１・・・
孔。 。
ものを右方から見た中央断面図、第３図は第１図および
第２図のものを分解状態で示した斜視図である。 １・・−、！、２・・・レバー、７・・田ツド刃、９・
・・溝、１０・・・ロッド刃保持プレート、１１・・・
孔。 。
Claims (1)
- 基台に対して回動自在にレバーを枢着し、該レバーに上
端を支持したロッド刃を基台に設けた孔に貫通させるこ
とにより、基台上に載置した紙葉に穿孔するようにした
パンチにおいて、ロッド刃を複数個設けると共に、該ロ
ッド刃の上部に周状の溝を形成し、一方、前記レバー側
には前記ロッド刃の上部を挿通し、前記溝の部分で把持
する孔を設けたことを特徴とするパンチ。
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1983012987U JPS59120597U (ja) | 1983-01-31 | 1983-01-31 | パンチ |
| US06/573,641 US4558434A (en) | 1983-01-31 | 1984-01-25 | Semiconductor memory device |
| US06/757,949 US4594927A (en) | 1982-09-27 | 1985-07-23 | Punch having improved cutter attachment means |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1983012987U JPS59120597U (ja) | 1983-01-31 | 1983-01-31 | パンチ |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59120597U true JPS59120597U (ja) | 1984-08-14 |
Family
ID=11820552
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1983012987U Pending JPS59120597U (ja) | 1982-09-27 | 1983-01-31 | パンチ |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US4558434A (ja) |
| JP (1) | JPS59120597U (ja) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4825409A (en) * | 1985-05-13 | 1989-04-25 | Wang Laboratories, Inc. | NMOS data storage cell for clocked shift register applications |
| JPS6240698A (ja) * | 1985-08-16 | 1987-02-21 | Fujitsu Ltd | 半導体記憶装置 |
| JPS62165794A (ja) * | 1986-01-17 | 1987-07-22 | Toshiba Corp | 連想記憶用メモリセル |
| US6112287A (en) * | 1993-03-01 | 2000-08-29 | Busless Computers Sarl | Shared memory multiprocessor system using a set of serial links as processors-memory switch |
| JP3068389B2 (ja) * | 1993-09-29 | 2000-07-24 | 日本電気株式会社 | 半導体記憶装置 |
| JP4154006B2 (ja) * | 1996-12-25 | 2008-09-24 | 富士通株式会社 | 半導体記憶装置 |
| US5796665A (en) * | 1997-10-17 | 1998-08-18 | Vanguard International Semiconductor Corporation | Semiconductor memory device with improved read signal generation of data lines and assisted precharge to mid-level |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5951075B2 (ja) * | 1980-03-31 | 1984-12-12 | 富士通株式会社 | 半導体記憶装置 |
-
1983
- 1983-01-31 JP JP1983012987U patent/JPS59120597U/ja active Pending
-
1984
- 1984-01-25 US US06/573,641 patent/US4558434A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US4558434A (en) | 1985-12-10 |
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