DE1918054A1 - Verfahren zur Herstellung von Halbleiter-Bauelementen - Google Patents

Verfahren zur Herstellung von Halbleiter-Bauelementen

Info

Publication number
DE1918054A1
DE1918054A1 DE19691918054 DE1918054A DE1918054A1 DE 1918054 A1 DE1918054 A1 DE 1918054A1 DE 19691918054 DE19691918054 DE 19691918054 DE 1918054 A DE1918054 A DE 1918054A DE 1918054 A1 DE1918054 A1 DE 1918054A1
Authority
DE
Germany
Prior art keywords
base
emitter
semiconductor
window
zones
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19691918054
Other languages
German (de)
English (en)
Inventor
Jean-Pierre Pestie
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel Lucent SAS
Original Assignee
Compagnie Generale dElectricite SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Compagnie Generale dElectricite SA filed Critical Compagnie Generale dElectricite SA
Publication of DE1918054A1 publication Critical patent/DE1918054A1/de
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/106—Masks, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/145—Shaped junctions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/151—Simultaneous diffusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/173—Washed emitter

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
DE19691918054 1968-04-10 1969-04-09 Verfahren zur Herstellung von Halbleiter-Bauelementen Pending DE1918054A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR147642 1968-04-10
FR151075A FR95067E (fr) 1968-04-10 1968-05-08 Procédé de fabrication de dispositifs semi-conducteurs.

Publications (1)

Publication Number Publication Date
DE1918054A1 true DE1918054A1 (de) 1969-10-23

Family

ID=26181939

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19691918054 Pending DE1918054A1 (de) 1968-04-10 1969-04-09 Verfahren zur Herstellung von Halbleiter-Bauelementen

Country Status (7)

Country Link
US (1) US3635772A (en, 2012)
BE (1) BE730645A (en, 2012)
CH (1) CH499205A (en, 2012)
DE (1) DE1918054A1 (en, 2012)
FR (2) FR1569872A (en, 2012)
GB (1) GB1218676A (en, 2012)
NL (1) NL6904936A (en, 2012)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2425756A1 (de) * 1973-05-29 1975-01-09 Texas Instruments Inc Verfahren zur selektiven maskierung einer substratoberflaeche waehrend der herstellung einer halbleitervorrichtung
DE2453528A1 (de) * 1973-12-26 1975-07-10 Ibm Maskierungsverfahren
DE2453134A1 (de) * 1974-11-08 1976-05-13 Itt Ind Gmbh Deutsche Planardiffusionsverfahren
DE3334153A1 (de) * 1982-09-24 1984-03-29 Hitachi, Ltd., Tokyo Verfahren zur herstellung einer halbleitereinrichtung

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE759583A (fr) * 1970-02-20 1971-04-30 Rca Corp Transistor de puissance pour micro-ondes
JPS543479A (en) * 1977-06-09 1979-01-11 Toshiba Corp Semiconductor device and its manufacture
JPS6410951B2 (en, 2012) * 1979-12-28 1989-02-22 Intaanashonaru Bijinesu Mashiinzu Corp
JPS60175453A (ja) * 1984-02-20 1985-09-09 Matsushita Electronics Corp トランジスタの製造方法
US4883767A (en) * 1986-12-05 1989-11-28 General Electric Company Method of fabricating self aligned semiconductor devices
US5010034A (en) * 1989-03-07 1991-04-23 National Semiconductor Corporation CMOS and bipolar fabrication process using selective epitaxial growth scalable to below 0.5 micron
US6399465B1 (en) * 2000-02-24 2002-06-04 United Microelectronics Corp. Method for forming a triple well structure

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3342650A (en) * 1964-02-10 1967-09-19 Hitachi Ltd Method of making semiconductor devices by double masking

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2425756A1 (de) * 1973-05-29 1975-01-09 Texas Instruments Inc Verfahren zur selektiven maskierung einer substratoberflaeche waehrend der herstellung einer halbleitervorrichtung
DE2425756C2 (de) * 1973-05-29 1987-01-29 Texas Instruments Inc., Dallas, Tex. Verfahren zur Herstellung einer Halbleitervorrichtung
DE2453528A1 (de) * 1973-12-26 1975-07-10 Ibm Maskierungsverfahren
DE2453134A1 (de) * 1974-11-08 1976-05-13 Itt Ind Gmbh Deutsche Planardiffusionsverfahren
DE3334153A1 (de) * 1982-09-24 1984-03-29 Hitachi, Ltd., Tokyo Verfahren zur herstellung einer halbleitereinrichtung

Also Published As

Publication number Publication date
CH499205A (fr) 1970-11-15
US3635772A (en) 1972-01-18
NL6904936A (en, 2012) 1969-10-14
FR1569872A (en, 2012) 1969-06-06
GB1218676A (en) 1971-01-06
BE730645A (en, 2012) 1969-09-29
FR95067E (fr) 1970-06-19

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