DE2425756C2 - - Google Patents

Info

Publication number
DE2425756C2
DE2425756C2 DE2425756A DE2425756A DE2425756C2 DE 2425756 C2 DE2425756 C2 DE 2425756C2 DE 2425756 A DE2425756 A DE 2425756A DE 2425756 A DE2425756 A DE 2425756A DE 2425756 C2 DE2425756 C2 DE 2425756C2
Authority
DE
Germany
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2425756A
Other versions
DE2425756A1 (de
Inventor
William Clayton Lewisville Tex. Us Robinette Jun.
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of DE2425756A1 publication Critical patent/DE2425756A1/de
Application granted granted Critical
Publication of DE2425756C2 publication Critical patent/DE2425756C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/043—Dual dielectric
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/106—Masks, special

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)
  • Weting (AREA)
  • Drying Of Semiconductors (AREA)
DE19742425756 1973-05-29 1974-05-28 Verfahren zur selektiven maskierung einer substratoberflaeche waehrend der herstellung einer halbleitervorrichtung Granted DE2425756A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US364981A US3860461A (en) 1973-05-29 1973-05-29 Method for fabricating semiconductor devices utilizing composite masking

Publications (2)

Publication Number Publication Date
DE2425756A1 DE2425756A1 (de) 1975-01-09
DE2425756C2 true DE2425756C2 (de) 1987-01-29

Family

ID=23436984

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19742425756 Granted DE2425756A1 (de) 1973-05-29 1974-05-28 Verfahren zur selektiven maskierung einer substratoberflaeche waehrend der herstellung einer halbleitervorrichtung

Country Status (5)

Country Link
US (1) US3860461A (de)
JP (1) JPS5830739B2 (de)
DE (1) DE2425756A1 (de)
FR (1) FR2232082B1 (de)
GB (1) GB1470804A (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2514466B2 (de) * 1975-04-03 1977-04-21 Ibm Deutschland Gmbh, 7000 Stuttgart Integrierte halbleiterschaltung
US4068217A (en) * 1975-06-30 1978-01-10 International Business Machines Corporation Ultimate density non-volatile cross-point semiconductor memory array
GB1548520A (en) * 1976-08-27 1979-07-18 Tokyo Shibaura Electric Co Method of manufacturing a semiconductor device
US5503959A (en) * 1991-10-31 1996-04-02 Intel Corporation Lithographic technique for patterning a semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1918054A1 (de) * 1968-04-10 1969-10-23 Comp Generale Electricite Verfahren zur Herstellung von Halbleiter-Bauelementen
DE1949174A1 (de) * 1968-10-02 1970-05-14 Hitachi Ltd Halbleiterelement mit einer Isolierschicht,die eine Raumladung induzierende Ionen enthaelt,sowie Verfahren zur Herstellung eines solchen Elements
DE2134385A1 (de) * 1970-07-10 1972-02-03 Motorola Inc Maskier verfahren für Halbleiteranordnungen

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1614435B2 (de) * 1967-02-23 1979-05-23 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zum Herstellen von aus Germanium bestehenden, doppeldiffundierten Halbleiteranordnungen

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1918054A1 (de) * 1968-04-10 1969-10-23 Comp Generale Electricite Verfahren zur Herstellung von Halbleiter-Bauelementen
DE1949174A1 (de) * 1968-10-02 1970-05-14 Hitachi Ltd Halbleiterelement mit einer Isolierschicht,die eine Raumladung induzierende Ionen enthaelt,sowie Verfahren zur Herstellung eines solchen Elements
DE2134385A1 (de) * 1970-07-10 1972-02-03 Motorola Inc Maskier verfahren für Halbleiteranordnungen

Also Published As

Publication number Publication date
JPS5022578A (de) 1975-03-11
FR2232082A1 (de) 1974-12-27
FR2232082B1 (de) 1979-02-16
DE2425756A1 (de) 1975-01-09
GB1470804A (en) 1977-04-21
US3860461A (en) 1975-01-14
JPS5830739B2 (ja) 1983-07-01

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Legal Events

Date Code Title Description
8110 Request for examination paragraph 44
8125 Change of the main classification
8181 Inventor (new situation)

Free format text: ROBINETTE JUN., WILLIAM CLAYTON, LEWISVILLE, TEX., US

D2 Grant after examination
8364 No opposition during term of opposition