DE69029618T2 - Verfahren zur Herstellung nichtflüchtiger Halbleiterspeicher - Google Patents

Verfahren zur Herstellung nichtflüchtiger Halbleiterspeicher

Info

Publication number
DE69029618T2
DE69029618T2 DE69029618T DE69029618T DE69029618T2 DE 69029618 T2 DE69029618 T2 DE 69029618T2 DE 69029618 T DE69029618 T DE 69029618T DE 69029618 T DE69029618 T DE 69029618T DE 69029618 T2 DE69029618 T2 DE 69029618T2
Authority
DE
Germany
Prior art keywords
production
volatile semiconductor
semiconductor memories
memories
volatile
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69029618T
Other languages
English (en)
Other versions
DE69029618D1 (de
Inventor
Yoichi Ohshima
Seiichi Mori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE69029618D1 publication Critical patent/DE69029618D1/de
Publication of DE69029618T2 publication Critical patent/DE69029618T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
DE69029618T 1989-08-11 1990-08-10 Verfahren zur Herstellung nichtflüchtiger Halbleiterspeicher Expired - Fee Related DE69029618T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1208806A JPH0783066B2 (ja) 1989-08-11 1989-08-11 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE69029618D1 DE69029618D1 (de) 1997-02-20
DE69029618T2 true DE69029618T2 (de) 1997-05-28

Family

ID=16562431

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69029618T Expired - Fee Related DE69029618T2 (de) 1989-08-11 1990-08-10 Verfahren zur Herstellung nichtflüchtiger Halbleiterspeicher

Country Status (5)

Country Link
US (1) US5019527A (de)
EP (1) EP0412558B1 (de)
JP (1) JPH0783066B2 (de)
KR (1) KR930007754B1 (de)
DE (1) DE69029618T2 (de)

Families Citing this family (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03196662A (ja) * 1989-12-26 1991-08-28 Nec Corp 半導体集積回路の配線構造およびその製造方法
US5371031A (en) * 1990-08-01 1994-12-06 Texas Instruments Incorporated Method of making EEPROM array with buried N+ windows and with separate erasing and programming regions
US5264718A (en) * 1991-06-28 1993-11-23 Texas Instruments Incorporated EEPROM cell array with tight erase distribution
US5270240A (en) * 1991-07-10 1993-12-14 Micron Semiconductor, Inc. Four poly EPROM process and structure comprising a conductive source line structure and self-aligned polycrystalline silicon digit lines
US5149665A (en) * 1991-07-10 1992-09-22 Micron Technology, Inc. Conductive source line for high density programmable read-only memory applications
JP3181357B2 (ja) * 1991-08-19 2001-07-03 株式会社東芝 半導体薄膜の形成方法および半導体装置の製造方法
EP0528690B1 (de) * 1991-08-21 1998-07-15 STMicroelectronics, Inc. Kontaktausrichtung für Festwertspeicher
US5264384A (en) * 1991-08-30 1993-11-23 Texas Instruments Incorporated Method of making a non-volatile memory cell
EP0540276B1 (de) * 1991-10-31 1997-09-24 STMicroelectronics, Inc. Herstellungsverfahren eines selbstjustierenden Kontakts
US5210047A (en) * 1991-12-12 1993-05-11 Woo Been Jon K Process for fabricating a flash EPROM having reduced cell size
ATE168500T1 (de) * 1992-04-29 1998-08-15 Siemens Ag Verfahren zur herstellung eines kontaktlochs zu einem dotierten bereich
JP2774734B2 (ja) * 1992-05-26 1998-07-09 株式会社東芝 半導体記憶装置およびその製造方法
EP0573728B1 (de) * 1992-06-01 1996-01-03 STMicroelectronics S.r.l. Verfahren zur Herstellung hochintegrierter kontaktloser EPROM's
US5350706A (en) * 1992-09-30 1994-09-27 Texas Instruments Incorporated CMOS memory cell array
JP2925416B2 (ja) * 1992-11-09 1999-07-28 株式会社東芝 半導体集積回路装置の製造方法
US5297082A (en) * 1992-11-12 1994-03-22 Micron Semiconductor, Inc. Shallow trench source eprom cell
JP2982580B2 (ja) * 1993-10-07 1999-11-22 日本電気株式会社 不揮発性半導体装置の製造方法
US5298447A (en) * 1993-07-22 1994-03-29 United Microelectronics Corporation Method of fabricating a flash memory cell
KR970007819B1 (en) * 1993-10-21 1997-05-17 Hyundai Electronics Ind Contact forming method of semiconductor device
JP2974561B2 (ja) * 1993-11-08 1999-11-10 株式会社東芝 半導体記憶装置及びその製造方法
US5589412A (en) * 1993-12-16 1996-12-31 National Semiconductor Corporation Method of making increased-density flash EPROM that utilizes a series of planarized, self-aligned, intermediate strips of conductive material to contact the drain regions
US5470773A (en) * 1994-04-25 1995-11-28 Advanced Micro Devices, Inc. Method protecting a stacked gate edge in a semiconductor device from self aligned source (SAS) etch
JP2687894B2 (ja) * 1994-09-26 1997-12-08 日本電気株式会社 半導体記憶装置の製造方法
JP2601226B2 (ja) * 1994-11-11 1997-04-16 日本電気株式会社 不揮発性半導体記憶装置のメモリセルの形成方法
US5880499A (en) * 1994-11-11 1999-03-09 Nec Corporation Memory cell of a nonvolatile semiconductor device
US5639681A (en) * 1995-01-17 1997-06-17 Intel Corporation Process for eliminating effect of polysilicon stringers in semiconductor devices
US5534451A (en) * 1995-04-27 1996-07-09 Taiwan Semiconductor Manufacturing Company Method for fabricating a reduced area metal contact to a thin polysilicon layer contact structure having low ohmic resistance
JPH0982924A (ja) * 1995-09-14 1997-03-28 Toshiba Corp 半導体記憶装置の製造方法
JP3431367B2 (ja) * 1995-10-03 2003-07-28 東芝マイクロエレクトロニクス株式会社 不揮発性半導体記憶装置の製造方法
KR100224701B1 (ko) * 1996-07-16 1999-10-15 윤종용 불휘발성 메모리장치 및 그 제조방법
JP3548834B2 (ja) * 1996-09-04 2004-07-28 沖電気工業株式会社 不揮発性半導体メモリの製造方法
US5858839A (en) * 1996-11-20 1999-01-12 Texas Instruments Incorporated Method of making EPROM cell array using n-tank as common source
KR100223769B1 (ko) * 1996-12-24 1999-10-15 김영환 메모리 소자의 유전막 형성 방법
JP3641103B2 (ja) * 1997-06-27 2005-04-20 株式会社東芝 不揮発性半導体メモリ装置の製造方法
US6127222A (en) * 1997-12-16 2000-10-03 Advanced Micro Devices, Inc. Non-self-aligned side channel implants for flash memory cells
US6103602A (en) * 1997-12-17 2000-08-15 Advanced Micro Devices, Inc. Method and system for providing a drain side pocket implant
DE19756601A1 (de) * 1997-12-18 1999-07-01 Siemens Ag Verfahren zum Herstellen eines Speicherzellen-Arrays
US6576521B1 (en) * 1998-04-07 2003-06-10 Agere Systems Inc. Method of forming semiconductor device with LDD structure
US6660585B1 (en) * 2000-03-21 2003-12-09 Aplus Flash Technology, Inc. Stacked gate flash memory cell with reduced disturb conditions
JP4149644B2 (ja) * 2000-08-11 2008-09-10 株式会社東芝 不揮発性半導体記憶装置
US6790765B1 (en) * 2003-11-25 2004-09-14 Nanya Technology Corporation Method for forming contact
CN101515569B (zh) * 2008-02-19 2011-08-03 和舰科技(苏州)有限公司 一种集成电路晶片结构及其制造方法
JP5139464B2 (ja) * 2010-03-30 2013-02-06 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
US20140015031A1 (en) * 2012-07-12 2014-01-16 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and Method for Memory Device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5645068A (en) * 1979-09-21 1981-04-24 Hitachi Ltd Manufacture of semiconductor
JPS614240A (ja) * 1984-06-18 1986-01-10 Toshiba Corp 半導体装置の製造方法
US4728617A (en) * 1986-11-04 1988-03-01 Intel Corporation Method of fabricating a MOSFET with graded source and drain regions
FR2618011B1 (fr) * 1987-07-10 1992-09-18 Commissariat Energie Atomique Procede de fabrication d'une cellule de memoire
JPS6437852A (en) * 1987-08-04 1989-02-08 Mitsubishi Electric Corp Manufacture of semiconductor device
US4868138A (en) * 1988-03-23 1989-09-19 Sgs-Thomson Microelectronics, Inc. Method for forming a self-aligned source/drain contact for an MOS transistor
DE68915508T2 (de) * 1988-10-25 1994-12-15 Matsushita Electronics Corp Verfahren zur Herstellung einer nicht-flüchtigen Speicheranordnung.

Also Published As

Publication number Publication date
JPH0783066B2 (ja) 1995-09-06
EP0412558B1 (de) 1997-01-08
KR910005464A (ko) 1991-03-30
KR930007754B1 (ko) 1993-08-18
DE69029618D1 (de) 1997-02-20
JPH0372681A (ja) 1991-03-27
EP0412558A3 (en) 1992-08-05
US5019527A (en) 1991-05-28
EP0412558A2 (de) 1991-02-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee