DE112014003246B4 - Hochvolt-Feldeffekttransistor mit mehreren implantierten Schichten und Verfahren zu seiner Herstellung - Google Patents
Hochvolt-Feldeffekttransistor mit mehreren implantierten Schichten und Verfahren zu seiner Herstellung Download PDFInfo
- Publication number
- DE112014003246B4 DE112014003246B4 DE112014003246.8T DE112014003246T DE112014003246B4 DE 112014003246 B4 DE112014003246 B4 DE 112014003246B4 DE 112014003246 T DE112014003246 T DE 112014003246T DE 112014003246 B4 DE112014003246 B4 DE 112014003246B4
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- oxide layer
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- region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
- H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/109—Reduced surface field [RESURF] PN junction structures
- H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
- H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
- H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
- H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
- H10P30/212—Through-implantation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
- H10P30/222—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/01—Manufacture or treatment
- H10D62/051—Forming charge compensation regions, e.g. superjunctions
- H10D62/054—Forming charge compensation regions, e.g. superjunctions by high energy implantations in bulk semiconductor bodies, e.g. forming pillars
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/111—Field plates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
- H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Crystallography & Structural Chemistry (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/941,119 US9660053B2 (en) | 2013-07-12 | 2013-07-12 | High-voltage field-effect transistor having multiple implanted layers |
| US13/941,119 | 2013-07-12 | ||
| PCT/US2014/044769 WO2015006074A1 (en) | 2013-07-12 | 2014-06-28 | High-voltage field-effect transistor having multiple implanted layers |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE112014003246T5 DE112014003246T5 (de) | 2016-04-07 |
| DE112014003246B4 true DE112014003246B4 (de) | 2025-04-03 |
Family
ID=52276454
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE112014003246.8T Active DE112014003246B4 (de) | 2013-07-12 | 2014-06-28 | Hochvolt-Feldeffekttransistor mit mehreren implantierten Schichten und Verfahren zu seiner Herstellung |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US9660053B2 (https=) |
| JP (1) | JP6490679B2 (https=) |
| KR (1) | KR102283496B1 (https=) |
| CN (1) | CN105378934B (https=) |
| DE (1) | DE112014003246B4 (https=) |
| WO (1) | WO2015006074A1 (https=) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11355580B2 (en) * | 2019-10-18 | 2022-06-07 | Semiconductor Components Industries, Llc | Lateral DMOS device with step-profiled RESURF and drift structures |
| CN113130632B (zh) * | 2019-12-31 | 2022-08-12 | 无锡华润上华科技有限公司 | 横向扩散金属氧化物半导体器件及其制备方法 |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4454648A (en) | 1982-03-08 | 1984-06-19 | Mcdonnell Douglas Corporation | Method of making integrated MNOS and CMOS devices in a bulk silicon wafer |
| US5270226A (en) | 1989-04-03 | 1993-12-14 | Matsushita Electric Industrial Co., Ltd. | Manufacturing method for LDDFETS using oblique ion implantion technique |
| US6429077B1 (en) | 1999-12-02 | 2002-08-06 | United Microelectronics Corp. | Method of forming a lateral diffused metal-oxide semiconductor transistor |
| US6773997B2 (en) | 2001-07-31 | 2004-08-10 | Semiconductor Components Industries, L.L.C. | Method for manufacturing a high voltage MOSFET semiconductor device with enhanced charge controllability |
| US7008865B2 (en) | 2001-12-03 | 2006-03-07 | Matsushita Electric Industrial Co., Ltd. | Method of manufacturing a semiconductor device having a high breakdown voltage and low on-resistance |
Family Cites Families (68)
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| JPS5638867A (en) | 1979-09-07 | 1981-04-14 | Hitachi Ltd | Insulated gate type field effect transistor |
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| JP2009515332A (ja) | 2005-11-02 | 2009-04-09 | エヌエックスピー ビー ヴィ | 半導体デバイスの製造方法 |
| KR20100064556A (ko) | 2008-12-05 | 2010-06-15 | 주식회사 동부하이텍 | 반도체 소자 및 그 제조 방법 |
| US8362557B2 (en) * | 2009-12-02 | 2013-01-29 | Fairchild Semiconductor Corporation | Stepped-source LDMOS architecture |
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-
2013
- 2013-07-12 US US13/941,119 patent/US9660053B2/en active Active
-
2014
- 2014-06-28 CN CN201480039829.0A patent/CN105378934B/zh active Active
- 2014-06-28 WO PCT/US2014/044769 patent/WO2015006074A1/en not_active Ceased
- 2014-06-28 DE DE112014003246.8T patent/DE112014003246B4/de active Active
- 2014-06-28 KR KR1020167000416A patent/KR102283496B1/ko active Active
- 2014-06-28 JP JP2016525370A patent/JP6490679B2/ja active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4454648A (en) | 1982-03-08 | 1984-06-19 | Mcdonnell Douglas Corporation | Method of making integrated MNOS and CMOS devices in a bulk silicon wafer |
| US5270226A (en) | 1989-04-03 | 1993-12-14 | Matsushita Electric Industrial Co., Ltd. | Manufacturing method for LDDFETS using oblique ion implantion technique |
| US6429077B1 (en) | 1999-12-02 | 2002-08-06 | United Microelectronics Corp. | Method of forming a lateral diffused metal-oxide semiconductor transistor |
| US6773997B2 (en) | 2001-07-31 | 2004-08-10 | Semiconductor Components Industries, L.L.C. | Method for manufacturing a high voltage MOSFET semiconductor device with enhanced charge controllability |
| US7008865B2 (en) | 2001-12-03 | 2006-03-07 | Matsushita Electric Industrial Co., Ltd. | Method of manufacturing a semiconductor device having a high breakdown voltage and low on-resistance |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2016526804A (ja) | 2016-09-05 |
| US9660053B2 (en) | 2017-05-23 |
| WO2015006074A1 (en) | 2015-01-15 |
| CN105378934B (zh) | 2018-12-11 |
| JP6490679B2 (ja) | 2019-03-27 |
| KR102283496B1 (ko) | 2021-07-29 |
| CN105378934A (zh) | 2016-03-02 |
| US20150014770A1 (en) | 2015-01-15 |
| DE112014003246T5 (de) | 2016-04-07 |
| KR20160030171A (ko) | 2016-03-16 |
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| Date | Code | Title | Description |
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| R012 | Request for examination validly filed | ||
| R016 | Response to examination communication | ||
| R079 | Amendment of ipc main class |
Free format text: PREVIOUS MAIN CLASS: H01L0029780000 Ipc: H10D0030600000 |
|
| R079 | Amendment of ipc main class |
Free format text: PREVIOUS MAIN CLASS: H10D0030600000 Ipc: H10D0030010000 |
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