DE112004002641B4 - Verfahren zur Herstellung eines verformten FinFET-Kanals - Google Patents

Verfahren zur Herstellung eines verformten FinFET-Kanals Download PDF

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Publication number
DE112004002641B4
DE112004002641B4 DE112004002641T DE112004002641T DE112004002641B4 DE 112004002641 B4 DE112004002641 B4 DE 112004002641B4 DE 112004002641 T DE112004002641 T DE 112004002641T DE 112004002641 T DE112004002641 T DE 112004002641T DE 112004002641 B4 DE112004002641 B4 DE 112004002641B4
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DE
Germany
Prior art keywords
layer
semiconductor layer
strain
trench
deformed
Prior art date
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Expired - Lifetime
Application number
DE112004002641T
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German (de)
English (en)
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DE112004002641T5 (de
Inventor
Qi San Jose Xiang
James N. Pan
Jung-Suk Stanford Goo
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GlobalFoundries US Inc
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Advanced Micro Devices Inc
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Publication of DE112004002641T5 publication Critical patent/DE112004002641T5/de
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions

Landscapes

  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE112004002641T 2004-01-12 2004-12-21 Verfahren zur Herstellung eines verformten FinFET-Kanals Expired - Lifetime DE112004002641B4 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/755,763 2004-01-12
US10/755,763 US7138302B2 (en) 2004-01-12 2004-01-12 Method of fabricating an integrated circuit channel region
PCT/US2004/043106 WO2005071728A1 (en) 2004-01-12 2004-12-21 Method of fabricating a strained finfet channel

Publications (2)

Publication Number Publication Date
DE112004002641T5 DE112004002641T5 (de) 2006-12-14
DE112004002641B4 true DE112004002641B4 (de) 2009-01-02

Family

ID=34739641

Family Applications (2)

Application Number Title Priority Date Filing Date
DE112004002641T Expired - Lifetime DE112004002641B4 (de) 2004-01-12 2004-12-21 Verfahren zur Herstellung eines verformten FinFET-Kanals
DE602004006782T Expired - Lifetime DE602004006782T2 (de) 2004-01-12 2004-12-21 Verfahren zur herstellung eines verformten finfet-kanals

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE602004006782T Expired - Lifetime DE602004006782T2 (de) 2004-01-12 2004-12-21 Verfahren zur herstellung eines verformten finfet-kanals

Country Status (8)

Country Link
US (1) US7138302B2 (https=)
EP (1) EP1723668B1 (https=)
JP (1) JP2007518272A (https=)
KR (1) KR101065049B1 (https=)
CN (1) CN100477126C (https=)
DE (2) DE112004002641B4 (https=)
TW (1) TWI360197B (https=)
WO (1) WO2005071728A1 (https=)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7074623B2 (en) * 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
KR100618852B1 (ko) 2004-07-27 2006-09-01 삼성전자주식회사 높은 동작 전류를 갖는 반도체 소자
US7393733B2 (en) 2004-12-01 2008-07-01 Amberwave Systems Corporation Methods of forming hybrid fin field-effect transistor structures
US7271448B2 (en) * 2005-02-14 2007-09-18 Taiwan Semiconductor Manufacturing Co., Ltd. Multiple gate field effect transistor structure
US8324660B2 (en) 2005-05-17 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US9153645B2 (en) 2005-05-17 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US7777250B2 (en) 2006-03-24 2010-08-17 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures and related methods for device fabrication
US7365401B2 (en) * 2006-03-28 2008-04-29 International Business Machines Corporation Dual-plane complementary metal oxide semiconductor
US8173551B2 (en) 2006-09-07 2012-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Defect reduction using aspect ratio trapping
US7875958B2 (en) 2006-09-27 2011-01-25 Taiwan Semiconductor Manufacturing Company, Ltd. Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures
US7799592B2 (en) 2006-09-27 2010-09-21 Taiwan Semiconductor Manufacturing Company, Ltd. Tri-gate field-effect transistors formed by aspect ratio trapping
US20080187018A1 (en) 2006-10-19 2008-08-07 Amberwave Systems Corporation Distributed feedback lasers formed via aspect ratio trapping
US7772048B2 (en) * 2007-02-23 2010-08-10 Freescale Semiconductor, Inc. Forming semiconductor fins using a sacrificial fin
US8304805B2 (en) 2009-01-09 2012-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor diodes fabricated by aspect ratio trapping with coalesced films
US8237151B2 (en) 2009-01-09 2012-08-07 Taiwan Semiconductor Manufacturing Company, Ltd. Diode-based devices and methods for making the same
US9508890B2 (en) 2007-04-09 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Photovoltaics on silicon
US7825328B2 (en) 2007-04-09 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Nitride-based multi-junction solar cell modules and methods for making the same
US8329541B2 (en) 2007-06-15 2012-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. InP-based transistor fabrication
WO2009035746A2 (en) 2007-09-07 2009-03-19 Amberwave Systems Corporation Multi-junction solar cells
US8183667B2 (en) 2008-06-03 2012-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Epitaxial growth of crystalline material
US8274097B2 (en) 2008-07-01 2012-09-25 Taiwan Semiconductor Manufacturing Company, Ltd. Reduction of edge effects from aspect ratio trapping
US8981427B2 (en) 2008-07-15 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Polishing of small composite semiconductor materials
US7872303B2 (en) * 2008-08-14 2011-01-18 International Business Machines Corporation FinFET with longitudinal stress in a channel
WO2010033813A2 (en) 2008-09-19 2010-03-25 Amberwave System Corporation Formation of devices by epitaxial layer overgrowth
US20100072515A1 (en) 2008-09-19 2010-03-25 Amberwave Systems Corporation Fabrication and structures of crystalline material
US8253211B2 (en) 2008-09-24 2012-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor sensor structures with reduced dislocation defect densities
SG171987A1 (en) 2009-04-02 2011-07-28 Taiwan Semiconductor Mfg Devices formed from a non-polar plane of a crystalline material and method of making the same
JP5666961B2 (ja) * 2011-03-31 2015-02-12 猛英 白土 半導体記憶装置
JP5667017B2 (ja) * 2011-09-03 2015-02-12 猛英 白土 半導体装置及びその製造方法
FR3029011B1 (fr) 2014-11-25 2018-04-13 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede ameliore de mise en contrainte d'une zone de canal de transistor
US9362400B1 (en) 2015-03-06 2016-06-07 International Business Machines Corporation Semiconductor device including dielectrically isolated finFETs and buried stressor
US10411128B1 (en) 2018-05-22 2019-09-10 International Business Machines Corporation Strained fin channel devices

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6645797B1 (en) * 2002-12-06 2003-11-11 Advanced Micro Devices, Inc. Method for forming fins in a FinFET device using sacrificial carbon layer

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6197641B1 (en) * 1998-08-28 2001-03-06 Lucent Technologies Inc. Process for fabricating vertical transistors
JP2002076334A (ja) * 2000-08-30 2002-03-15 Hitachi Ltd 半導体装置及びその製造方法
JP3782021B2 (ja) * 2002-02-22 2006-06-07 株式会社東芝 半導体装置、半導体装置の製造方法、半導体基板の製造方法
US6635909B2 (en) * 2002-03-19 2003-10-21 International Business Machines Corporation Strained fin FETs structure and method
CN1225799C (zh) * 2002-04-24 2005-11-02 华邦电子股份有限公司 金属氧化物半导体场效应晶体管及其制造方法
AU2003237473A1 (en) 2002-06-07 2003-12-22 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US7074623B2 (en) * 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
JP4546021B2 (ja) * 2002-10-02 2010-09-15 ルネサスエレクトロニクス株式会社 絶縁ゲート型電界効果型トランジスタ及び半導体装置
US6806534B2 (en) * 2003-01-14 2004-10-19 International Business Machines Corporation Damascene method for improved MOS transistor
US6815738B2 (en) * 2003-02-28 2004-11-09 International Business Machines Corporation Multiple gate MOSFET structure with strained Si Fin body
WO2004081982A2 (en) * 2003-03-07 2004-09-23 Amberwave Systems Corporation Shallow trench isolation process
US6835618B1 (en) * 2003-08-05 2004-12-28 Advanced Micro Devices, Inc. Epitaxially grown fin for FinFET
US6855583B1 (en) * 2003-08-05 2005-02-15 Advanced Micro Devices, Inc. Method for forming tri-gate FinFET with mesa isolation
US6955969B2 (en) * 2003-09-03 2005-10-18 Advanced Micro Devices, Inc. Method of growing as a channel region to reduce source/drain junction capacitance

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6645797B1 (en) * 2002-12-06 2003-11-11 Advanced Micro Devices, Inc. Method for forming fins in a FinFET device using sacrificial carbon layer

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Huang et al.: "Sub 50nm FinFET: PMOS" in: IEDM 99, 1999, S. 67-70 *

Also Published As

Publication number Publication date
JP2007518272A (ja) 2007-07-05
US20050153486A1 (en) 2005-07-14
KR20060130098A (ko) 2006-12-18
DE602004006782T2 (de) 2008-01-24
CN100477126C (zh) 2009-04-08
WO2005071728A1 (en) 2005-08-04
CN1902744A (zh) 2007-01-24
TW200529367A (en) 2005-09-01
TWI360197B (en) 2012-03-11
KR101065049B1 (ko) 2011-09-19
US7138302B2 (en) 2006-11-21
EP1723668A1 (en) 2006-11-22
EP1723668B1 (en) 2007-05-30
DE602004006782D1 (de) 2007-07-12
DE112004002641T5 (de) 2006-12-14

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