CN202564376U - 氮化物半导体元件及氮化物半导体封装 - Google Patents

氮化物半导体元件及氮化物半导体封装 Download PDF

Info

Publication number
CN202564376U
CN202564376U CN2011204659005U CN201120465900U CN202564376U CN 202564376 U CN202564376 U CN 202564376U CN 2011204659005 U CN2011204659005 U CN 2011204659005U CN 201120465900 U CN201120465900 U CN 201120465900U CN 202564376 U CN202564376 U CN 202564376U
Authority
CN
China
Prior art keywords
layer
algan
nitride semiconductor
gan
lattice constant
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CN2011204659005U
Other languages
English (en)
Inventor
高堂真也
伊藤范和
山口敦司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Application granted granted Critical
Publication of CN202564376U publication Critical patent/CN202564376U/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02499—Monolayers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02579—P-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
    • H01L29/151—Compositional structures
    • H01L29/152—Compositional structures with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
    • H01L29/154—Compositional structures with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation comprising at least one long range structurally disordered material, e.g. one-dimensional vertical amorphous superlattices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
    • H01L29/7784—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material with delta or planar doped donor layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0605—Shape
    • H01L2224/06051—Bonding areas having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01012—Magnesium [Mg]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12032—Schottky diode

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

本新型提供一种氮化物半导体元件及氮化物半导体封装。在基板(41)上形成包含AlN层(47)、第一AlGaN层(48)(平均Al组成50％)及第二AlGaN层(49)(平均Al组成20％)的缓冲层(44)。在缓冲层(44)上形成包含GaN电子移动层(45)及AlGaN电子供给层(46)的元件动作层。借此，构成HEMT元件(3)。使用本新型的氮化物半导体元件则GaN电子移动层的厚度的设计自由度高，所以能够提供耐压优秀的封装。而且，可以减轻氮化物半导体元件的GaN电子移动层的龟裂及Si基板的翘曲，所以能够提供可靠性高的封装。

Description

氮化物半导体元件及氮化物半导体封装
技术领域
本新型涉及一种使用III族氮化物半导体的氮化物半导体元件及该元件的半导体封装。
背景技术
所谓III族氮化物半导体，是指在III-V族半导体中使用氮作为V族元素而成的半导体。代表例有氮化铝(AlN)、氮化镓(GaN)、氮化铟(InN)。一般来说，可以表示为AlxInyGa1-x-yN(0≤x≤1、0≤y≤1、0≤x+y≤1)。
这种III族氮化物半导体具有适用于高温、高功率器件、高频器件的物性。鉴于此物性，III族氮化物半导体作为构成HEMT(High Electron Mobility Transistor：高电子迁移率晶体管)等器件的半导体而使用。
例如，提出一种HEMT，其包含Si基板、及通过磊晶成长而依次积层在Si基板上的AlN层、AlGaN层(Al组成为0.3以上且0.6以下)、GaN层及AlGaN电子供给层(例如参照专利文献1)。
[先行技术文献]
专利文献
专利文献1：日本专利特开2008-166349号公报
新型内容
然而，在专利文献1的HEMT中，由于AlGaN层与GaN层的晶格常数之差较大，所以若积层大厚度的GaN层，则会引起GaN的晶格松弛，施加在GaN层上的压缩应力消失，因Si基板与GaN的线膨胀系数之差而产生拉伸应力。所以，发生GaN层上产生细裂纹(龟裂)的不良状况。这样就导致GaN层的厚度受到限制，器件设计的自由度小。
因此，本新型的目的在于提供一种能够在广范围内选择GaN电子移动层的厚度、且可提高器件设计的自由度的氮化物半导体元件。
而且，本新型的其他目的在于提供一种耐压及可靠性优秀的氮化物半导体元件封装。
为了达成所述目的，技术方案1的新型是一种氮化物半导体元件，包括：Si基板；缓冲层，包含形成在所述Si基板的主表面上的AlN层及形成在该AlN层上且积层多层AlGaN层而成的AlGaN积层构造；GaN电子移动层，形成在所述AlGaN积层构造上；及AlGaN电子供给层，形成在所述GaN电子移动层上；且所述AlGaN积层构造中，某一基准AlGaN层的Al组成小于比该基准AlGaN层更靠所述AlN层一侧的AlGaN层的Al组成。换句话说，多层AlGaN层优选包含第一AlGaN层、及第二AlGaN层，所述第二AlGaN层相对于该第一AlGaN层而配置在所述AlN层的相反侧(GaN电子移动层侧)，且Al组成小于该第一AlGaN层。
根据所述构成，多层AlGaN层是以层越靠近GaN电子移动层则Al组成变得越小的方式规定各组成。由此，AlGaN层的晶格常数可以从靠近AlN的晶格常数的值开始，阶段性地增大至靠近GaN的晶格常数的值。因此，可以减小GaN电子移动层、与接于该GaN电子移动层的最上层的AlGaN层之间的晶格常数差。如此一来可以自由设计GaN电子移动层的厚度。由此，可以通过将GaN电子移动层设计的较厚，来提高元件耐压。
然而，GaN结晶通过磊晶成长而积层在Si基板上的情况下，在磊晶成长后的冷却中或者冷却后，有时候会由于Si基板与GaN层的热膨胀系数差(即降温时的收缩率之差)导致GaN层上产生较大拉伸应力。这样就会引起GaN层产生细裂纹(龟裂)及Si基板产生翘曲的情况。
根据本新型，在Si基板上形成AlN层，并在该AlN层与GaN电子移动层之间设置AlGaN积层构造。而且，在AlGaN积层构造中，多层AlGaN层是以层越靠近GaN电子移动层则Al组成变得越小的方式规定各组成。因此，可以将由于AlN层与最下层的AlGaN层的晶格常数差而施加给该AlGaN层的压缩应力(应变)传递到最上层的AlGaN层。这样一来，即便GaN电子移动层上产生拉伸应力，也可以通过从AlN层及AlGaN缓冲层施加给GaN电子移动层的压缩应力，来缓和所述拉伸应力。由此，能够减轻GaN电子移动层的龟裂及Si基板的翘曲。
而且，在所述AlGaN积层构造中，如技术方案2所示，所述基准AlGaN层的Al组成(％)、与接于该基准AlGaN层的所述AlN层侧的面而配置的AlGaN层的Al组成(％)之差优选为10％以上。
借此，能够使基准AlGaN层、与接于该基准AlGaN层的AlGaN层之间确切地产生晶格常数差。
例如，如果基准AlGaN层的Al组成(％)、与接于该基准AlGaN层的AlN层侧的面而配置的AlGaN层的Al组成(％)之差是1％左右，那么有时候基准AlGaN层的晶格常数会与和其接于的AlGaN层的晶格常数一致。因此，最上层的AlGaN层与GaN电子移动层的晶格常数之差变大，产生完全的晶格松弛，故难以从缓冲层向GaN电子移动层传递压缩应力(应变)。
所以，若为技术方案2的新型的构成，相比于所述产生晶格常数一致的部位的情况，能够减小GaN电子移动层与最上层的AlGaN层的晶格常数差。由此，可以从缓冲层向GaN电子移动层良好地传递压缩应力(应变)，这样就能够良好地减轻GaN电子移动层的龟裂及Si基板的翘曲。
例如，所述AlGaN积层构造也可以如技术方案3所示，包含从所述AlN层开始依次积层Al组成为50％的第一AlGaN层及Al组成为20％的第二AlGaN层而成的构造。
而且，所述AlGaN积层构造也可以如技术方案4所示，包含从所述AlN层开始依次积层Al组成为80％的第一AlGaN层、Al组成为60％的第二AlGaN层、Al组成为40％的第三AlGaN层及Al组成为20％的第四AlGaN层而成的构造。
而且，技术方案5的新型是根据技术方案1至4中任一技术方案所述的氮化物半导体，其中所述缓冲层的主表面的面方位是c面，在所述AlGaN积层构造中，所述基准AlGaN层的a轴平均晶格常数比接于该基准AlGaN层的所述AlN层侧的面而配置的AlGaN层的a轴面内晶格常数大，比该基准AlGaN层原本具有的a轴平均晶格常数小。
根据所述构成，基准AlGaN层的a轴平均晶格常数比接于该基准AlGaN层的AlGaN层的a轴面内晶格常数大，比该基准AlGaN层原本具有的a轴平均晶格常数(无应变状态下的a轴晶格常数)小。借此，对基准AlGaN层施加与接于该基准AlGaN层的AlN层侧的面而配置的AlGaN层的a轴晶格常数不一致这样的程度的a轴压缩应力。而且，能够将所述a轴压缩应力传递到最上层的AlGaN层。因此，即便GaN电子移动层上产生a轴拉伸应力，也可以通过从AlN层及AlGaN缓冲层施加给GaN电子移动层的a轴压缩应力，来缓和所述a轴拉伸应力。
还有，所谓面内晶格常数，是指接于基准AlGaN层的AlN层侧的面的AlGaN层与基准AlGaN层的界面的晶格常数。
而且，Si基板的主表面也可以如技术方案6所示为(111)面。
而且，GaN电子移动层的c轴晶格常数的应变度如技术方案7所示，优选为-0.07％以上。
借此，能够确切地防止GaN电子移动层产生龟裂。
而且，所述GaN电子移动层的厚度如技术方案8所示，优选为500nm～2000nm。
而且，所述AlN层的厚度如技术方案9所示，优选为50nm～200nm。
而且，所述第一AlGaN层的厚度如技术方案10所示，优选为100nm～500nm。
而且，所述第二AlGaN层的厚度如技术方案11所示，优选为100nm～500nm。
而且，技术方案12的新型是一种氮化物半导体封装，包含根据技术方案1至11中任一技术方案所述的氮化物半导体元件、及以覆盖所述氮化物半导体元件的方式而形成的树脂封装。
根据所述构成，使用本新型的氮化物半导体元件则GaN电子移动层的厚度的设计自由度高，所以能够提供耐压优秀的封装。而且，可以减轻氮化物半导体元件的GaN电子移动层的龟裂及Si基板的翘曲，所以能够提供可靠性高的封装。
附图说明
图1是本新型的一实施方式的HEMT封装的示意性整体图。
图2是表示图1所示的HEMT封装内部的透视图。
图3是图2的虚线A围住的部分的放大图。
图4是本新型的一实施方式的HEMT元件的示意性截面图，其表示图3的B-B切断面的截面。
图5是氮化物半导体层上产生的残留应力的影像图。
图6是对用来成长构成III族氮化物半导体积层构造的各层的处理装置的构成进行说明的图解图。
图7是用来说明图4的AlGaN积层构造的变形例的图。
图8是表示实施例的HEMT元件的构成的示意性截面图。
图9是表示实施例的GaN电子移动层的c轴晶格常数的应变度的表格。
图10是表示实施例的第二AlGaN层的晶格常数的表格。
[符号的说明]
1HEMT封装
3HEMT元件
4树脂封装
41基板
43(基板的)主表面
44缓冲层
45GaN电子移动层
46AlGaN电子供给层
47AlN层
48第一AlGaN层
49第二AlGaN层
52第一AlGaN层
53第AlGaN层
54第三AlGaN层
55第四AlGaN层
具体实施方式
以下，参照附图来详细说明本新型的实施方式。
图1是本新型的一实施方式的HEMT封装的示意性整体图。图2是表示图1所示的HEMT封装内部的透视图。图3是图2的虚线A围住的部分的放大图。
作为本新型的氮化物半导体封装一例的HEMT封装1包含端子框架2、HEMT元件3(芯片)、及树脂封装4。
端子框架2是形成为金属制的板状。端子框架2俯视时具有四边形状，且包含支撑HEMT封装1的底座部5、与该底座部5一体形成的源极端子6、与该底座部5隔开形成的汲极端子7及闸极端子8。
源极端子6、汲极端子7及闸极端子8分别形成为包含一端及另一端的俯视直线状，且按照源极端子6、汲极端子7及闸极端子8的顺序彼此平行地排列配置。所述多个端子6～8中，只有与底座部5一体的源极端子6的一端连接在底座部5的一角部上。剩余的端子7～8中，闸极端子8是以一端与和连接着源极端子6的角部相邻的底座部5的另一角部对向的方式配置，而汲极端子7是配置在闸极端子8与源极端子6之间。
HEMT元件3是本新型的氮化物半导体元件的一例，且包含汲极垫9、源极垫10及闸极垫11。所述多个汲极垫9、源极垫10及闸极垫11是形成为金属制的板状，且彼此隔开配置。
汲极垫9一体包含焊接部12D、支臂部13D及电极部14D。
汲极垫9的焊接部12D形成包含一端及另一端、且在横切端子框架2的各端子6～8的方向上延伸的俯视直线状。焊接部12D是使用焊线15D(图2中是3根接线)而电性连接到汲极端子7上。
汲极垫9的支臂部13D是从该焊接部12D的一端及另一端开始，以向远离端子6～8的方向延伸而彼此平行的俯视直线状形成为一对。汲极垫9通过焊接部12D及一对支臂部13D，来划分露出支臂部13D的移动端(另一端)侧且被包围成俯视凹状(コ字状)的元件区域16。
汲极垫9的电极部14D设置在元件区域16内，且呈从各支臂部13D朝向另一支臂部13D延伸的条纹状而形成着多个电极部14D。在连接于一支臂部13D上的电极部14D的前端、与连接于另一支臂部13D上的电极部14D的前端之间，设置着具有特定宽度的缝隙17。
源极垫10一体包含焊接部18S、支臂部19S及电极部20S。
源极垫10的焊接部18S在元件区域16的露出端，形成为与汲极垫9的焊接部12D平行延伸的俯视直线状。焊接部18S是使用焊线21S(图2中是2根接线)而电性连接到底座部5上。借此，源极垫10的焊接部18S电性连接到与底座部5为一体的源极端子6上。
源极垫10的支臂部19S是以在汲极垫9的电极部14D的缝隙17内，在横切汲极垫9的电极部14D的方向上延伸的方式形成1根。
源极垫10的电极部20S是以从支臂部19S朝向汲极垫9的各支臂部13D的两个方向延伸的条纹状而形成着多个。电极部20S在汲极垫9的电极部14D各者之间分别设置1根。
闸极垫11一体包含焊接部22G、第一支臂部23G、第二支臂部24G及电极部25G。
闸极垫11的焊接部22G形成为俯视四边形状，且配置在汲极垫9的一支臂部13D的移动端部附近。焊接部22G是使用焊线26G(图2中是1根接线)而电性连接到闸极端子8上。
闸极垫11的第一支臂部23G形成为俯视直线状，即，从焊接部22G的角部直到汲极垫9的另一支臂部13D的移动端部为止，相对源极垫10的焊接部18S而靠近元件区域16一侧相对于汲极垫9的焊接部12D平行延伸。
闸极垫11的第二支臂部24G是以从第一支臂部23G开始，在汲极垫9的电极部14D的缝隙17内，向横切汲极垫9的电极部14D的方向延伸的方式，在源极垫10的支臂部19S的两侧分别形成1根。
闸极垫11的电极部25G是以从各第二支臂部24G朝向汲极垫9的各支臂部13D的两个方向延伸的条纹状形成着多个。电极部25G在汲极垫9的电极部14D与源极垫10的电极部20S各者之间分别设置1根。而且，该电极部25G与电极部14D的间隔GD比电极部25G与电极部20S的间隔GS更广。即，电极部25G是相对于电极部14D与电极部20S的中间位置而配置在靠近电极部20S一侧。借此，对汲极侧的电极部14D施加正电压、对闸极侧的电极部25G施加0(零)V以下的电压时，汲极-闸极间能够实现充分的电压降。这样一来，能够防止对于电极部25G的静电聚焦。
树脂封装4构成HEMT封装1的外形，且形成为大体长方体状。树脂封装4包含例如环氧树脂等熟知模具树脂，将端子框架2的底座部5及焊线15D、21S、26G和HEMT元件3一起覆盖，露出3根端子(源极端子6、汲极端子7及闸极端子8)，从而将HEMT元件3密封。
图4是本新型的一实施方式的HEMT元件的示意截面图，其表示图3的B-B切断面的截面。
接着，参照图4来详细说明HEMT元件的内部构造。
HEMT元件3包含作为半导体基板的基板41、及通过磊晶成长(结晶成长)而形成在基板41上的III族氮化物半导体积层构造42。
基板41在本实施方式中是由Si单晶基板(线膨胀系数α1为例如2.5×10-6～3.5×10-6(293K))构成。该基板41是以(111)面为主表面43且偏离角为0°的同轴(111)面Si基板。
基板41的a轴平均晶格常数LC1(与沿着基板41的主表面43方向的构成氮化物半导体的原子键结的Si原子的晶格间距离)为例如0.768nm～0.769nm。而且，通过该主表面43上的结晶成长，而形成III族氮化物半导体积层构造42。III族氮化物半导体积层构造42包含例如以c面((0001)面))为结晶成长主表面的III族氮化物半导体。
形成III族氮化物半导体积层构造42的各层、与底层的晶格不对准是通过结晶成长层的晶格应变而吸收，从而确保与底层的界面上的晶格连续性。例如，从GaN层的c面((0001)面))分别成长InGaN层及AlGaN层时，无应变状态下的InGaN的a轴方向的平均晶格常数(a轴平均晶格常数)比GaN的a轴平均晶格常数大，所以InGaN层上产生朝向a轴方向的压缩应力(压缩应变)。相对于此，无应变状态下的AlGaN的a轴平均晶格常数比GaN的a轴平均晶格常数小，所以AlGaN层上产生朝向a轴方向的拉伸应力(拉伸应变)。
III族氮化物半导体积层构造42构成为从基板41侧开始依次积层缓冲层44、GaN电子移动层45、及AlGaN电子供给层46。
缓冲层44构成为积层AlN层47、第一AlGaN层48、及第二AlGaN层49。该实施方式中，第一AlGaN层48与第二AlGaN层49的积层构造是本新型的AlGaN积层构造的一例。而且，第二AlGaN层49是本新型的基准AlGaN层的一例，第一AlGaN层48是接于基准AlGaN层的AlN层侧的面而配置的AlGaN层的一例。
AlN层47的厚度为50nm～200nm，例如为120nm。而且，AlN层47的a轴平均晶格常数LC2例如为0.311nm～0.312nm，线膨胀系数α2例如为4.1×10-6～4.2×10-6(293K)。
第一AlGaN层48在本实施方式中是构成为未有意添加杂质的未掺杂AlGaN层。然而，第一AlGaN层48有时候也会无意地包含微量杂质。第一AlGaN层48的厚度为100nm～500nm，例如为140nm。而且，第一AlGaN层48的平均Al组成为40～60％(例如50％)。而且，第一AlGaN层48的a轴平均晶格常数LC3为例如0.314nm～0.316nm，线膨胀系数α3为例如4.6×10-6～5.0×10-6(293K)。
而且，第一AlGaN层48的上表面(与第二AlGaN层49的界面)的a轴面内晶格常数LC3′为例如0.312nm～0.314nm。
第二AlGaN层49在本实施方式中是构成为未有意添加杂质的未掺杂AlGaN层。然而，第二AlGaN层49中有时候也会无意地包含微量杂质。第二AlGaN层49的厚度为100nm～500nm，例如140nm。而且，第二AlGaN层49的平均Al组成比第一AlGaN层48小10％以上，具体来说，小10～30％(例如20％)。而且，第二AlGaN层49的a轴平均晶格常数LC4比第一AlGaN层48的上表面(与第二AlGaN层49的界面)的a轴面内晶格常数LC3′大，且比AlGaN原本具有的a轴平均晶格常数(0.316nm～0.318nm)小，例如为0.314nm～0.316nm。而且，第二AlGaN层49的线膨胀系数α4为例如5.0×10-6～5.4×10-6(293K)。
GaN电子移动层45在本实施方式中构成为未有意添加杂质的未掺杂GaN层。然而，GaN电子移动层45中有时候会无意地包含微量杂质。GaN电子移动层45的a轴平均晶格常数LC5为例如0.318nm～0.319nm，线膨胀系数α5为例如5.5×10-6～5.6×10-6(293K)。
而且，GaN电子移动层45的c轴晶格常数的应变度为例如-0.07％以上且0(零)以下。该c轴晶格常数的应变度例如通过X射线绕射测定测定GaN电子移动层45的c轴晶格常数，将其与GaN原本具有的c轴晶格常数进行对比而获得。只要GaN电子移动层45的c轴晶格常数的应变度处于所述范围内，便可抑制施加的c轴压缩应力，防止龟裂产生。
c轴及a轴存在彼此正交的关系。因此，如图5所示，沿着所述各方向的压缩应力及拉伸应力存在相反关系，即，向一方向(例如c轴方向)施加压缩应力时，向另一方向(例如a轴方向)施加拉伸应力。
因此，如上所述，将GaN电子移动层45的c轴晶格常数的应变度设为-0.07％以上且0(零)以下，可以抑制施加给GaN电子移动层45的c轴压缩应力，防止龟裂产生。
AlGaN电子供给层46在本实施方式中是构成为未有意添加杂质的未掺杂AlGaN层。然而，AlGaN电子供给层46中有时候也会无意地包含微量杂质。AlGaN电子供给层46的a轴平均晶格常数LC6为例如0.318nm～0.319nm。而且，AlGaN电子供给层46的平均Al组成为20～30％(例如25％)。而且，AlGaN电子供给层46的线膨胀系数α6为例如5.0×10-6～5.2×10-6(293K)。
如此一来，组成互不相同的GaN电子移动层45与AlGaN电子供给层46的接合变成异质接合，因此GaN电子移动层45上，在与AlGaN电子供给层46的接合界面附近，产生2维电子气(2DEG)。2维电子气遍布GaN电子移动层45的与AlGaN电子供给层46的接合界面附近的大体整个区域，其浓度为例如8×1012cm-2～2×1013cm-2。HEMT元件3中，利用该2维电子气使源极-汲极间流动电流，从而执行元件动作。
在AlGaN电子供给层46上，以接于该AlGaN电子供给层46的方式，隔开间隔而设置着所述闸极垫11的电极部25G、源极垫10的电极部20S及汲极垫9的电极部14D。
闸极垫11的电极部25G(以下称为闸极电极25G)可以由能够与AlGaN电子供给层46之间形成肖特基接合的电极材料、例如Ni/Au(镍/金合金)等构成。
源极垫10的电极部20S(以下称为源极电极20S)及汲极垫9的电极部14D(以下称为汲极电极14D)均可以由能够对AlGaN电子供给层46实现欧姆接于的电极材料、例如Ti/Al(钛/铝合金)、Ti/Al/Ni/Au(钛/铝/镍/金合金)、Ti/Al/Nb/Au(钛/铝/铌/金合金)、Ti/Al/Mo/Au(钛/铝/钼/金合金)等构成。
而且，在基板41的背面形成着背面电极51。该背面电极51通过连接到端子框架2的底座部5，而使基板41的电位变成接地(ground)电位。还有，也可以通过将基板41的电位设为与源极电极20S相同的电位，而使源极电极20S变成接地电位。
图6是对用来成长构成III族氮化物半导体积层构造的各层的处理装置的构成进行说明的图解图。
接着，参照图6来详细说明III族氮化物半导体积层构造的作制方法。
处理室60内配置着内置了加热器61的基座62。基座62结合于旋转轴63上，且该旋转轴63是利用配置在处理室60外的旋转驱动机构64而旋转。借此，通过在基座62上保持处理对象的晶片65，可以在处理室60内将晶片65升温到特定温度，且可使其旋转。晶片65是构成所述Si单晶基板41的Si单晶晶片。
处理室60上连接着排气配管66。排气配管66是连接于旋转泵等排气设备。借此，处理室60内的压力设为1/10气压～常压，始终对处理室60内的处理环境进行排气。
另一方面，在处理室60内，导入用来向基座62上保持的晶片65表面供给原料气体的原料气体供给管路70。该原料气体供给管路70上连接着供给作为氮原料气体的氨的氮原料配管71、供给作为镓原料气体的三甲基镓(TMG)的镓原料配管72、供给作为铝原料气体的三甲基铝(TMAl)的铝原料配管73、供给作为硼原料气体的三乙基硼(TEB)的硼原料配管74、供给作为镁原料气体的乙基环戊二烯基镁(EtCp2Mg)的镁原料配管75、供给作为硅原料气体的硅烷(SiH4)的硅原料配管76、以及供给载体气体的载体气体配管77。所述多个原料配管71～77内分别介装着阀81～87。各原料气体均是与包含氢或氮或者包含这两者的载体气体一起供给。
例如，将以(111)面为主表面的Si单晶晶片作为晶片65而保持在基座62上。在此状态下，关闭阀81～86，打开载体气体阀87，向处理室60内供给载体气体。另外，向加热器61通电，将晶片温度升温至1000℃～1100℃(例如1050℃)。借此，可以不产生表面粗化地成长III族氮化物半导体。
当晶片温度达到1000℃～1100℃而待机后，打开氮原料阀81及铝原料阀83。借此，从原料气体供给管路70与载体气体一起供给氨及三甲基铝。这样一来，在晶片65的表面磊晶成长AlN层47。
接着，形成第一AlGaN层48。也就是说，打开氮原料阀81、镓原料阀82及铝原料阀83，关闭其他阀84～86。借此，向晶片65供给氨、三甲基镓及三甲基铝，形成包含AlGaN的第一AlGaN层48。形成该第一AlGaN层48时，晶片65的温度宜设为1000℃～1100℃(例如1050℃)。
接着，形成第二AlGaN层49。也就是说，打开氮原料阀81、镓原料阀82及铝原料阀83，关闭其他阀84～86。借此，向晶片65供给氨、三甲基镓及三甲基铝，形成包含AlGaN的第二AlGaN层49。形成该第二AlGaN层49时，晶片65的温度宜设为1000℃～1100℃(例如1050℃)。
然后，形成GaN电子移动层45。在形成GaN电子移动层45时，打开氮原料阀81及镓原料阀82，向晶片65供给氨及三甲基镓，借此成长GaN层。在形成GaN电子移动层45时，晶片65的温度宜设为例如1000℃～1100℃(例如1050℃)。
接着，形成AlGaN电子供给层46。也就是说，打开氮原料阀81、镓原料阀82及铝原料阀83，关闭其他阀84、85。借此，向晶片65供给氨、三甲基镓及三甲基铝，形成AlGaN电子供给层46。在形成该AlGaN电子供给层46时，晶片65的温度宜设为1000℃～1100℃(例如1050℃)。
之后，在常温下将晶片65放置20～60分钟使其冷却。这样就形成了III族氮化物半导体积层构造42。
如上所述，根据本实施方式，在Si单晶基板41上设置将AlN层47、第一AlGaN层48(Al平均组成50％)及第二AlGaN层49(Al平均组成20％)依次积层而成的缓冲层44，GaN电子移动层45形成为接于第二AlGaN层49的主表面(c面)。
借此，AlN层47到GaN电子移动层45为止的a轴平均晶格常数是阶段性地从LC2(0.311nm)、LC3(0.314nm)及LC4(0.316nm)不断增大到接近GaN电子移动层的a轴平均晶格常数LC5(0.318nm)的值。因此，可以减小GaN电子移动层45、与接于该GaN电子移动层45的第二AlGaN层49的a轴平均晶格常数之差(LC5-LC4)。这样一来，能够自由地设计GaN电子移动层45的厚度。由此，可以通过将GaN电子移动层45设计地较厚，来提高HEMT元件3的耐压。
而且，可以将由于AlN层47与第一AlGaN层48的a轴平均晶格常数差(LC3-LC2)而施加给第一AlGaN层48的压缩应力，传递到第二AlGaN层49。借此，第二AlGaN层49的a轴平均晶格常数LC4比接于第二AlGaN层49的第一AlGaN层48的a轴面内晶格常数LC3′大，且比第二AlGaN层49原本具有的a轴平均晶格常数小。即，第二AlGaN层49上施加与第一AlGaN层48的a轴面内晶格常数LC3′不一致这样程度的a轴压缩应力。而且，可以对GaN电子移动层45施加所述a轴压缩应力。
因此，在III族氮化物半导体积层构造42形成后的冷却中或冷却后，即便由于基板41与GaN电子移动层45的线膨胀系数差(α5-α1)导致GaN电子移动层45产生拉伸应力，也可以通过从第二AlGaN层49施加给GaN电子移动层45的压缩应力，来缓和所述拉伸应力。
这样一来，如上所述，可以将GaN电子移动层45的c轴晶格常数的应变度设为-0.07％以上且0(零)以下，也就是说，能够将GaN电子移动层45保持为施加着不产生龟裂这一程度的a轴拉伸应力的状态。由此，可以减轻GaN电子移动层45的龟裂及基板41的翘曲。
以上，对本新型的一实施方式进行了说明，但本新型还可以通过其他形态来实施。
例如，缓冲层44的AlGaN积层构造并非必须由Al组成互不相同的两种AlGaN层48、49构成，例如，也可以如图7所示，构成为从AlN层47侧开始依次积层第一AlGaN层52(平均Al组成为例如80％)、第二AlGaN层53(平均Al组成为例如60％)、第三AlGaN层54(平均Al组成为例如40％)及第四AlGaN层55(平均Al组成为例如20％)。而且，还可以构成为积层Al组成互不相同的三种AlGaN层、五种AlGaN层、及五种以上的AlGaN层。
此外，可以在权利要求记载的事项范围内实施各种设计变更。
[实施例]
接下来，基于实施例来说明本新型，但本新型并非由下述实施例限定。
<实施例>
实施例是为了确认GaN电子移动层的c轴晶格常数的应变度及第二AlGaN层的晶格常数，随着第二AlGaN层的Al组成的变化而发生何种变化。
首先，在以(111)面为主表面的Si单晶基板的表面上，磊晶成长AlN层(120nm厚)。接着，依次磊晶成长第一AlGaN层(平均Al组成50％厚度140nm)及第二AlGaN层(平均Al组成10％厚度140nm)。借此，形成缓冲层。
然后，在第二AlGaN层上依次形成GaN电子移动层(厚度1000nm)及AlGaN电子供给层，借此制作图8所示的III族氮化物半导体积层构造。之后，在AlGaN电子供给层上形成源极电极及汲极电极。
而且，同样地制作设置平均Al组成17％及25％的第二AlGaN层代替平均Al组成10％的第二AlGaN层的III族氮化物半导体积层构造。
<评估>
(1)GaN电子移动层的c轴应变度的测定
对实施例中获得的III族氮化物半导体积层构造的GaN电子移动层进行X射线绕射测定，测定出GaN电子移动层的c轴晶格常数。借此，评估施加给GaN电子移动层的残留应力的方向及其大小。图9表示结果。
根据图9，可知无论第二AlGaN层的平均Al组成如何，GaN电子移动层的残留应力都相对于c轴压缩(相对于a轴拉伸)。我们认为这是由于Si单晶基板与GaN电子移动层的线膨胀系数差所导致。
即，GaN电子移动层上虽然被施加a轴拉伸应力，但c轴应变度的大小为-0.07以上，换句话说，确认该a轴拉伸应力是不会导致GaN电子移动层产生龟裂这一程度的适当大小。
而且，可知当第二AlGaN层的平均Al组成为17％时，GaN电子移动层的残留应力的大小变得最小，是三个实施例中的最佳值。
(2)第二AlGaN层的晶格常数的测定
对实施例中获得的III族氮化物半导体积层构造的第二AlGaN进行X射线绕射测定，测定出第二AlGaN层的a轴晶格常数。图10表示结果。而且，下述表1表示所述第二AlGaN层与GaN电子移动层的a轴晶格常数之差。
[表1]
  平均Al组成(％)   与GaN的a轴晶格常数差(％)
  10   0.34
  17   0.62
  25   0.91
在图10中，直线表示AlGaN层原本具有的c轴晶格常数与a轴晶格常数的关系。该直线左侧的墨点表示该墨点所示的AlGaN层受到a轴压缩应力，右侧的墨点表示该墨点所示的AlGaN层受到a轴拉伸应力。而且，直线与墨点之间的距离表示该应力大小。即，直线与墨点之间的距离越大，则表示该墨点所示的AlGaN层受到的应力越大。
根据图10，可知无论第二AlGaN层的平均Al组成如何，第二AlGaN层都施加着适当的a轴压缩应力。借此，确认该a轴压缩应力作用于GaN电子移动层，缓和由于Si单晶基板与GaN电子移动层的线膨胀系数差引起的拉伸应力。

Claims (9)

1.一种氮化物半导体元件，其特征在于包括：
Si基板；
缓冲层，包含形成在所述Si基板的主表面上的AlN层、及形成在该AlN层上且积层多层AlGaN层而形成的AlGaN积层构造；
GaN电子移动层，形成在所述AlGaN积层构造上；及
AlGaN电子供给层，形成在所述GaN电子移动层上；
在所述AlGaN积层构造中，基准AlGaN层的a轴平均晶格常数比接于该基准AlGaN层的所述AlN层侧的面而配置的AlGaN层的a轴面内晶格常数大，且比该基准AlGaN层原本具有的a轴平均晶格常数小。
2.根据权利要求1所述的氮化物半导体元件，其中所述缓冲层的主表面的面方位为c面。
3.根据权利要求1或2所述的氮化物半导体元件，其中所述Si基板的所述主表面为(111)面。
4.根据权利要求3所述的氮化物半导体元件，其中所述GaN电子移动层的c轴晶格常数的应变度为-0.07％以上。
5.根据权利要求1或2所述的氮化物半导体元件，其中所述GaN电子供给层的厚度为500nm～2000nm。
6.根据权利要求1或2所述的氮化物半导体元件，其中所述AlN层的厚度为50nm～200nm。
7.根据权利要求1或2所述的氮化物半导体元件，其中所述第一AlGaN层的厚度为100nm～500nm。
8.根据权利要求1或2所述的氮化物半导体元件，其中所述第二AlGaN层的厚度为 100nm～500nm。
9.一种氮化物半导体封装，其特征在于包含：
根据权利要求1至8中任一权利要求所述的氮化物半导体元件；及
树脂封装，以覆盖所述氮化物半导体元件的方式形成。 
CN2011204659005U 2010-11-16 2011-11-16 氮化物半导体元件及氮化物半导体封装 Expired - Lifetime CN202564376U (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2010-255912 2010-11-16
JP2010255912A JP5781292B2 (ja) 2010-11-16 2010-11-16 窒化物半導体素子および窒化物半導体パッケージ

Publications (1)

Publication Number Publication Date
CN202564376U true CN202564376U (zh) 2012-11-28

Family

ID=46046987

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2011204659005U Expired - Lifetime CN202564376U (zh) 2010-11-16 2011-11-16 氮化物半导体元件及氮化物半导体封装

Country Status (3)

Country Link
US (5) US9257548B2 (zh)
JP (1) JP5781292B2 (zh)
CN (1) CN202564376U (zh)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103337517A (zh) * 2013-06-09 2013-10-02 中国电子科技集团公司第十三研究所 基于iii族氮化物材料含多层背势垒的器件结构
CN105336770A (zh) * 2014-08-06 2016-02-17 江西省昌大光电科技有限公司 氮化镓基高电子迁移率晶体管外延结构及其制造方法
CN105702826A (zh) * 2014-11-25 2016-06-22 东莞市中镓半导体科技有限公司 一种在Si衬底上制备无裂纹GaN薄膜的方法
CN109671776A (zh) * 2018-12-24 2019-04-23 广东省半导体产业技术研究院 半导体器件及其制造方法
CN111962018A (zh) * 2019-09-20 2020-11-20 深圳市晶相技术有限公司 一种半导体外延结构及其应用与制造方法

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012015304A (ja) * 2010-06-30 2012-01-19 Sumitomo Electric Ind Ltd 半導体装置
JP5781292B2 (ja) * 2010-11-16 2015-09-16 ローム株式会社 窒化物半導体素子および窒化物半導体パッケージ
JP5815976B2 (ja) * 2011-04-21 2015-11-17 トランスフォーム・ジャパン株式会社 半導体装置
JP2013145782A (ja) * 2012-01-13 2013-07-25 Sharp Corp ヘテロ接合型電界効果トランジスタ用のエピタキシャルウエハ
JP5319810B2 (ja) * 2012-03-08 2013-10-16 株式会社東芝 窒化物半導体層の製造方法
JP6151487B2 (ja) * 2012-07-10 2017-06-21 富士通株式会社 化合物半導体装置及びその製造方法
JP5421442B1 (ja) 2012-09-26 2014-02-19 株式会社東芝 窒化物半導体ウェーハ、窒化物半導体素子及び窒化物半導体ウェーハの製造方法
JP2014072427A (ja) * 2012-09-28 2014-04-21 Fujitsu Ltd 半導体装置及び半導体装置の製造方法
US9577056B2 (en) 2012-09-28 2017-02-21 Fraunhofer-Gesellschaft Zur Forderung Der Angewandten Forschung E.V. Semiconductor component comprising at least one contact structure for feeding in and/or leading away charge carriers
US10546949B2 (en) * 2012-12-26 2020-01-28 Agency For Science, Technology And Research Group III nitride based high electron mobility transistors
JP6392498B2 (ja) * 2013-03-29 2018-09-19 富士通株式会社 化合物半導体装置及びその製造方法
JP2014220407A (ja) * 2013-05-09 2014-11-20 ローム株式会社 窒化物半導体素子
WO2014198550A1 (de) * 2013-06-11 2014-12-18 Osram Opto Semiconductors Gmbh Verfahren zur herstellung eines nitridverbindungshalbleiter-bauelements
JP5996489B2 (ja) * 2013-07-09 2016-09-21 株式会社東芝 窒化物半導体ウェーハ、窒化物半導体素子及び窒化物半導体ウェーハの製造方法
US9443969B2 (en) * 2013-07-23 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Transistor having metal diffusion barrier
CN104347695A (zh) * 2013-07-31 2015-02-11 浙江大学苏州工业技术研究院 一种提高器件纵向耐压能力的半导体装置
US9130026B2 (en) * 2013-09-03 2015-09-08 Taiwan Semiconductor Manufacturing Co., Ltd. Crystalline layer for passivation of III-N surface
JP2015053328A (ja) * 2013-09-05 2015-03-19 富士通株式会社 半導体装置
US20150115327A1 (en) * 2013-10-30 2015-04-30 International Rectifier Corporation Group III-V Device Including a Buffer Termination Body
JP6302254B2 (ja) * 2014-01-15 2018-03-28 株式会社東芝 窒化物半導体素子、窒化物半導体ウェーハ、及び、窒化物半導体素子の製造方法
US9425301B2 (en) 2014-04-30 2016-08-23 Taiwan Semiconductor Manufacturing Co., Ltd. Sidewall passivation for HEMT devices
JP2016100471A (ja) * 2014-11-21 2016-05-30 住友電気工業株式会社 半導体装置及び半導体装置の製造方法
CN106548972B (zh) * 2015-09-18 2019-02-26 胡兵 一种将半导体衬底主体与其上功能层进行分离的方法
US20180061975A1 (en) * 2016-08-24 2018-03-01 Rohm Co., Ltd. Nitride semiconductor device and nitride semiconductor package
TWI703726B (zh) * 2016-09-19 2020-09-01 新世紀光電股份有限公司 含氮半導體元件
JP7019942B2 (ja) * 2016-09-28 2022-02-16 富士通株式会社 化合物半導体基板及びその製造方法、化合物半導体装置及びその製造方法、電源装置、高出力増幅器
US10636899B2 (en) * 2016-11-15 2020-04-28 Infineon Technologies Austria Ag High electron mobility transistor with graded back-barrier region
CN107910244B (zh) * 2017-11-01 2020-05-22 大连芯冠科技有限公司 采用硅图形衬底生长氮化镓外延方法
CN107799590B (zh) * 2017-11-21 2024-05-24 华南理工大学 一种大栅宽的GaN基微波功率器件及其制造方法
TWI631668B (zh) 2017-11-22 2018-08-01 聯鈞光電股份有限公司 氮化物半導體結構
US11515407B2 (en) * 2018-12-26 2022-11-29 Intel Corporation High breakdown voltage structure for high performance GaN-based HEMT and MOS devices to enable GaN C-MOS
US11414782B2 (en) 2019-01-13 2022-08-16 Bing Hu Method of separating a film from a main body of a crystalline object
WO2022141190A1 (en) * 2020-12-30 2022-07-07 Innoscience (suzhou) Semiconductor Co., Ltd. Epitaxial layers with discontinued aluminium content for iii-nitride semiconductor

Family Cites Families (84)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6072197A (en) * 1996-02-23 2000-06-06 Fujitsu Limited Semiconductor light emitting device with an active layer made of semiconductor having uniaxial anisotropy
JP2000277441A (ja) * 1999-03-26 2000-10-06 Nagoya Kogyo Univ 半導体構造とそれを備えた半導体素子及び結晶成長方法
JP4022708B2 (ja) * 2000-06-29 2007-12-19 日本電気株式会社 半導体装置
US6680959B2 (en) * 2000-07-18 2004-01-20 Rohm Co., Ltd. Semiconductor light emitting device and semiconductor laser
US6548333B2 (en) * 2000-12-01 2003-04-15 Cree, Inc. Aluminum gallium nitride/gallium nitride high electron mobility transistors having a gate contact on a gallium nitride based cap segment
WO2002103812A1 (en) * 2001-06-13 2002-12-27 Matsushita Electric Industrial Co., Ltd. Nitride semiconductor, production method therefor and nitride semiconductor element
US7030428B2 (en) * 2001-12-03 2006-04-18 Cree, Inc. Strain balanced nitride heterojunction transistors
KR101030068B1 (ko) * 2002-07-08 2011-04-19 니치아 카가쿠 고교 가부시키가이샤 질화물 반도체 소자의 제조방법 및 질화물 반도체 소자
US6841001B2 (en) * 2002-07-19 2005-01-11 Cree, Inc. Strain compensated semiconductor structures and methods of fabricating strain compensated semiconductor structures
EP1403926A2 (en) * 2002-09-27 2004-03-31 Matsushita Electric Industrial Co., Ltd. Semiconductor device
US7612390B2 (en) * 2004-02-05 2009-11-03 Cree, Inc. Heterojunction transistors including energy barriers
JP2006032911A (ja) * 2004-06-15 2006-02-02 Ngk Insulators Ltd 半導体積層構造、半導体素子およびｈｅｍｔ素子
US20060073621A1 (en) * 2004-10-01 2006-04-06 Palo Alto Research Center Incorporated Group III-nitride based HEMT device with insulating GaN/AlGaN buffer layer
JP4514584B2 (ja) * 2004-11-16 2010-07-28 富士通株式会社 化合物半導体装置及びその製造方法
JP4189386B2 (ja) * 2005-01-27 2008-12-03 ローム株式会社 窒化物半導体結晶層の成長方法および窒化物半導体発光素子の製法
US20070018199A1 (en) * 2005-07-20 2007-01-25 Cree, Inc. Nitride-based transistors and fabrication methods with an etch stop layer
EP1755172A1 (en) * 2005-08-17 2007-02-21 Ngk Insulators, Ltd. Semiconductor layered structure and its method of formation, and light emitting device
JP2007115887A (ja) * 2005-10-20 2007-05-10 Rohm Co Ltd 窒化物半導体素子およびその製法
US8853666B2 (en) * 2005-12-28 2014-10-07 Renesas Electronics Corporation Field effect transistor, and multilayered epitaxial film for use in preparation of field effect transistor
JP2008056553A (ja) * 2006-08-01 2008-03-13 Ngk Insulators Ltd 窒化アルミニウム単結晶
JP2008109066A (ja) * 2006-09-29 2008-05-08 Rohm Co Ltd 発光素子
JP2008118044A (ja) * 2006-11-07 2008-05-22 Toshiba Corp 電界効果トランジスタ及びその製造方法
JP5383974B2 (ja) 2006-12-27 2014-01-08 住友電工デバイス・イノベーション株式会社 半導体基板および半導体装置
US7825432B2 (en) * 2007-03-09 2010-11-02 Cree, Inc. Nitride semiconductor structures with interlayer structures
US8362503B2 (en) * 2007-03-09 2013-01-29 Cree, Inc. Thick nitride semiconductor structures with interlayer structures
JP5165264B2 (ja) * 2007-03-22 2013-03-21 浜松ホトニクス株式会社 窒化物半導体基板
JP2008244121A (ja) * 2007-03-27 2008-10-09 Rohm Co Ltd 窒化物半導体素子の製造方法
US7907652B2 (en) * 2007-04-25 2011-03-15 Sanyo Electric Co., Ltd. Semiconductor laser device
US7869480B2 (en) * 2007-05-24 2011-01-11 Sanyo Electric Co., Ltd. Semiconductor laser device
JP5118392B2 (ja) * 2007-06-08 2013-01-16 ローム株式会社 半導体発光素子およびその製造方法
JP2009010142A (ja) * 2007-06-27 2009-01-15 Toyoda Gosei Co Ltd Ｉｉｉ族窒化物半導体で構成されたｈｆｅｔおよびその製造方法
KR101537300B1 (ko) * 2007-08-08 2015-07-16 더 리전츠 오브 더 유니버시티 오브 캘리포니아 미스컷 기판들 상에 성장된 평면의 무극성 ｍ-면 Ⅲ족-질화물 막들
JP2009081428A (ja) * 2007-09-03 2009-04-16 Rohm Co Ltd 半導体発光素子およびその製造方法
JP2009081374A (ja) * 2007-09-27 2009-04-16 Rohm Co Ltd 半導体発光素子
US8432946B2 (en) * 2007-12-06 2013-04-30 Rohm Co., Ltd. Nitride semiconductor laser diode
JP4592742B2 (ja) * 2007-12-27 2010-12-08 Ｄｏｗａエレクトロニクス株式会社 半導体材料、半導体材料の製造方法及び半導体素子
US20090238227A1 (en) * 2008-03-05 2009-09-24 Rohm Co., Ltd. Semiconductor light emitting device
CN102017082B (zh) * 2008-03-13 2013-03-20 昭和电工株式会社 Ⅲ族氮化物半导体元件及其制造方法、ⅲ族氮化物半导体发光元件及其制造方法和灯
JP2009252861A (ja) * 2008-04-03 2009-10-29 Rohm Co Ltd 半導体レーザ素子
JP4390007B2 (ja) * 2008-04-07 2009-12-24 住友電気工業株式会社 Ｉｉｉ族窒化物半導体素子及びエピタキシャルウエハ
CN101604704B (zh) * 2008-06-13 2012-09-05 西安能讯微电子有限公司 Hemt器件及其制造方法
JP2010040867A (ja) * 2008-08-06 2010-02-18 Showa Denko Kk Ｉｉｉ族窒化物半導体積層構造体およびその製造方法
US8159004B2 (en) * 2008-08-26 2012-04-17 Sanken Electric Co., Ltd. Compound semiconductor device having dopant concentration gradient
WO2010029775A1 (ja) * 2008-09-11 2010-03-18 住友電気工業株式会社 窒化物系半導体光素子、窒化物系半導体光素子のためのエピタキシャルウエハ、及び半導体発光素子を製造する方法
JP2010123920A (ja) * 2008-10-20 2010-06-03 Sumitomo Electric Ind Ltd 窒化物系半導体発光素子を作製する方法、及びエピタキシャルウエハを作製する方法
JP5316276B2 (ja) * 2009-01-23 2013-10-16 住友電気工業株式会社 窒化物半導体発光素子、エピタキシャル基板、及び窒化物半導体発光素子を作製する方法
US8390091B2 (en) * 2009-02-03 2013-03-05 Freescale Semiconductor, Inc. Semiconductor structure, an integrated circuit including a semiconductor structure and a method for manufacturing a semiconductor structure
JP5487631B2 (ja) * 2009-02-04 2014-05-07 富士通株式会社 化合物半導体装置及びその製造方法
JP2010232297A (ja) * 2009-03-26 2010-10-14 Sumitomo Electric Device Innovations Inc 半導体装置
JP5316210B2 (ja) * 2009-05-11 2013-10-16 住友電気工業株式会社 窒化物半導体発光素子
US9048385B2 (en) * 2009-06-24 2015-06-02 Nichia Corporation Nitride semiconductor light emitting diode
JP2011023537A (ja) * 2009-07-15 2011-02-03 Sumitomo Electric Ind Ltd Ｉｉｉ族窒化物半導体素子、エピタキシャル基板、及びｉｉｉ族窒化物半導体素子を作製する方法
JP4978667B2 (ja) * 2009-07-15 2012-07-18 住友電気工業株式会社 窒化ガリウム系半導体レーザダイオード
US8481991B2 (en) * 2009-08-21 2013-07-09 The Regents Of The University Of California Anisotropic strain control in semipolar nitride quantum wells by partially or fully relaxed aluminum indium gallium nitride layers with misfit dislocations
JP5515575B2 (ja) * 2009-09-30 2014-06-11 住友電気工業株式会社 Ｉｉｉ族窒化物半導体光素子、エピタキシャル基板、及びｉｉｉ族窒化物半導体光素子を作製する方法
US8575660B2 (en) * 2009-10-14 2013-11-05 International Rectifier Corporation Group III-V semiconductor device with strain-relieving interlayers
JP5577681B2 (ja) * 2009-11-30 2014-08-27 住友電気工業株式会社 半導体装置
JP5559814B2 (ja) * 2009-12-08 2014-07-23 パナソニック株式会社 窒化物系半導体発光ダイオードおよびその製造方法
US8835998B2 (en) * 2009-12-14 2014-09-16 University Of Notre Dame Du Lac Compositionally graded heterojunction semiconductor device and method of making same
JP5604147B2 (ja) * 2010-03-25 2014-10-08 パナソニック株式会社 トランジスタ及びその製造方法
US8921894B2 (en) * 2010-03-26 2014-12-30 Nec Corporation Field effect transistor, method for producing the same, and electronic device
JP5706102B2 (ja) * 2010-05-07 2015-04-22 ローム株式会社 窒化物半導体素子
JP2012015303A (ja) * 2010-06-30 2012-01-19 Sumitomo Electric Ind Ltd 半導体基板および半導体装置
EP2595181B8 (en) * 2010-07-14 2018-07-04 Fujitsu Limited Compound semiconductor device and manufacturing method thereof
JP2012033575A (ja) * 2010-07-28 2012-02-16 Sumitomo Electric Ind Ltd 半導体装置
JP5259660B2 (ja) * 2010-09-06 2013-08-07 株式会社東芝 半導体発光素子
JP5742072B2 (ja) * 2010-10-06 2015-07-01 住友電気工業株式会社 半導体装置およびその製造方法
JP5781292B2 (ja) * 2010-11-16 2015-09-16 ローム株式会社 窒化物半導体素子および窒化物半導体パッケージ
US20120126239A1 (en) * 2010-11-24 2012-05-24 Transphorm Inc. Layer structures for controlling stress of heteroepitaxially grown iii-nitride layers
US20120189029A1 (en) * 2010-12-07 2012-07-26 Rohm Co., Ltd. Semiconductor laser device
JP2013042107A (ja) * 2011-02-17 2013-02-28 Rohm Co Ltd 半導体レーザ素子
US8358673B2 (en) * 2011-02-17 2013-01-22 Corning Incorporated Strain balanced laser diode
US8629531B2 (en) * 2011-02-18 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method to reduce wafer warp for gallium nitride on silicon wafer
US9373688B2 (en) * 2011-05-04 2016-06-21 Infineon Technologies Austria Ag Normally-off high electron mobility transistors
KR101813177B1 (ko) * 2011-05-06 2017-12-29 삼성전자주식회사 고전자이동도 트랜지스터 및 그 제조방법
JP2012248575A (ja) * 2011-05-25 2012-12-13 Sumitomo Electric Ind Ltd 窒化物半導体レーザ素子、エピタキシャル基板、及び窒化物半導体レーザ素子を作製する方法
JP2013038394A (ja) * 2011-07-14 2013-02-21 Rohm Co Ltd 半導体レーザ素子
US8710511B2 (en) * 2011-07-29 2014-04-29 Northrop Grumman Systems Corporation AIN buffer N-polar GaN HEMT profile
JP5127978B1 (ja) * 2011-09-08 2013-01-23 株式会社東芝 窒化物半導体素子、窒化物半導体ウェーハ及び窒化物半導体層の製造方法
JP5362085B1 (ja) * 2012-09-05 2013-12-11 株式会社東芝 窒化物半導体ウェーハ、窒化物半導体素子及び窒化物半導体ウェーハの製造方法
JP5421442B1 (ja) * 2012-09-26 2014-02-19 株式会社東芝 窒化物半導体ウェーハ、窒化物半導体素子及び窒化物半導体ウェーハの製造方法
US9837521B2 (en) * 2012-10-11 2017-12-05 Rohm Co., Ltd. Nitride semiconductor device and fabrication method therefor
JP2014220407A (ja) * 2013-05-09 2014-11-20 ローム株式会社 窒化物半導体素子
US20150115327A1 (en) * 2013-10-30 2015-04-30 International Rectifier Corporation Group III-V Device Including a Buffer Termination Body

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103337517A (zh) * 2013-06-09 2013-10-02 中国电子科技集团公司第十三研究所 基于iii族氮化物材料含多层背势垒的器件结构
CN103337517B (zh) * 2013-06-09 2016-05-18 中国电子科技集团公司第十三研究所 基于iii族氮化物材料含多层背势垒的器件结构
CN105336770A (zh) * 2014-08-06 2016-02-17 江西省昌大光电科技有限公司 氮化镓基高电子迁移率晶体管外延结构及其制造方法
CN105702826A (zh) * 2014-11-25 2016-06-22 东莞市中镓半导体科技有限公司 一种在Si衬底上制备无裂纹GaN薄膜的方法
CN105702826B (zh) * 2014-11-25 2018-10-19 东莞市中镓半导体科技有限公司 一种在Si衬底上制备无裂纹GaN薄膜的方法
CN109671776A (zh) * 2018-12-24 2019-04-23 广东省半导体产业技术研究院 半导体器件及其制造方法
CN111962018A (zh) * 2019-09-20 2020-11-20 深圳市晶相技术有限公司 一种半导体外延结构及其应用与制造方法

Also Published As

Publication number Publication date
US20120119219A1 (en) 2012-05-17
US20160155807A1 (en) 2016-06-02
JP5781292B2 (ja) 2015-09-16
US10062565B2 (en) 2018-08-28
US9905419B2 (en) 2018-02-27
US9472623B2 (en) 2016-10-18
US9257548B2 (en) 2016-02-09
JP2012109345A (ja) 2012-06-07
US20180337041A1 (en) 2018-11-22
US20180158678A1 (en) 2018-06-07
US20170011911A1 (en) 2017-01-12

Similar Documents

Publication Publication Date Title
CN202564376U (zh) 氮化物半导体元件及氮化物半导体封装
US8405064B2 (en) Nitride semiconductor device
JP5634681B2 (ja) 半導体素子
TWI230978B (en) Semiconductor device and the manufacturing method thereof
US8067787B2 (en) Semiconductor electronic device
US8264001B2 (en) Semiconductor wafer having multi-layered buffer region formed from compound semiconductor materials
TWI518899B (zh) 半導體裝置
KR101933230B1 (ko) 반도체 소자, ｈｅｍｔ 소자, 및 반도체 소자의 제조 방법
JP5495069B2 (ja) 半導体素子及びその製造方法
US8754419B2 (en) Semiconductor device
US9012959B2 (en) Semiconductor device
US8946863B2 (en) Epitaxial substrate for electronic device comprising a high resistance single crystal substrate on a low resistance single crystal substrate, and method of manufacturing
TW201304138A (zh) 具有極佳穩定性的氮基半導體裝置
EP2600393A1 (en) Semiconductor element, hemt element, and production method for semiconductor element
KR20150091705A (ko) 질화물 반도체 소자 및 그 제조 방법
US11552171B2 (en) Method for fabricating semiconductor structure including the substrate structure
KR20140132524A (ko) 이종 기판, 질화물 반도체 발광 소자 및 그 제조 방법
JP7069584B2 (ja) 基板生産物の製造方法
KR102273305B1 (ko) 신뢰성을 개선한 다이아몬드 기판 상 질화 갈륨 반도체 구조체 및 이를 제조하는 공정
EP2565930B1 (en) III-nitride semiconductor device
KR20130083198A (ko) 질화물계 반도체 이종접합 반도체 소자
JP6089122B2 (ja) 窒化物半導体積層体およびその製造方法並びに窒化物半導体装置
TWI740457B (zh) 半導體結構以及半導體裝置
WO2016073505A1 (en) Thermal treated semiconductor/gate dielectric interface for group iiia-n devices
US11251264B2 (en) Semiconductor device and manufacturing method of the same

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
CX01 Expiry of patent term

Granted publication date: 20121128

CX01 Expiry of patent term