US20180061975A1 - Nitride semiconductor device and nitride semiconductor package - Google Patents
Nitride semiconductor device and nitride semiconductor package Download PDFInfo
- Publication number
- US20180061975A1 US20180061975A1 US15/683,130 US201715683130A US2018061975A1 US 20180061975 A1 US20180061975 A1 US 20180061975A1 US 201715683130 A US201715683130 A US 201715683130A US 2018061975 A1 US2018061975 A1 US 2018061975A1
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- Prior art keywords
- layer
- nitride semiconductor
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- electron
- electron supply
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- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
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- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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Definitions
- the present invention relates to a nitride semiconductor device, having an HEMT (High Electron Mobility Transistor) structure, and a package thereof.
- HEMT High Electron Mobility Transistor
- Japanese Patent Publication No. 4705412 discloses a field effect transistor including a sapphire substrate, an AlN buffer layer on the sapphire substrate, an undoped GaN layer on the AlN buffer layer, an undoped AlGaN layer on the undoped GaN layer, a p type GaN layer provided on a portion of the undoped AlGaN layer, a high concentration p type GaN layer on the p type GaN layer, and a gate electrode on the high concentration p type GaN layer.
- the transistor of Patent Document 1 is of the normally-off type
- the layers below the gate electrode contain a p type impurity and therefore whereas holes are implanted from the p type GaN gate layer when the transistor is on, a time corresponding to the carrier life is required when turning off the transistor because the implanted holes must be annihilated by recombination with the electrons, thus making the turnoff time long and making the transistor unsuitable for high speed switching operations.
- the AlGaN layer electron supply layer
- a decrease in gate threshold voltage occurs and in some cases, the transistor becomes normally on. That is, the sheet carrier density outside a gate region directly below the gate electrode and the gate threshold voltage are in a tradeoff relationship.
- An object of the present invention is to provide a nitride semiconductor device and a package thereof, with which both high sheet carrier density and high gate threshold voltage can be realized at the same time.
- the gate layer effectively does not contain an acceptor type impurity, and therefore even when the device is turned on, holes are not implanted into the electron supply layer from the gate layer.
- the turnoff time can thereby be shortened and high speed switching can thus be realized. Also, due to satisfying the formula (1) above, normally-off operation is enabled.
- the electron transit layer and the gate layer may contain GaN and the electron supply layer may contain AlGaN.
- the effective acceptor concentration N DA +N A ⁇ N DD ⁇ N D of the electron transit layer may be not less than 5 ⁇ 10 16 cm ⁇ 3
- the thickness d G of the gate layer may be not less than 80 nm
- an Al composition of the electron supply layer may be not more than 25%
- the thickness d B of the electron supply layer may be not more than 20 nm.
- the electron transit layer may contain Mg as a deep acceptor.
- the concentration of the acceptor type impurity in the gate layer may be less than 1 ⁇ 10 16 cm ⁇ 3 .
- a nitride semiconductor device includes an electron transit layer, constituted of a nitride semiconductor, an electron supply layer, constituted of Al x Ga 1 ⁇ x N (x ⁇ 1) on the electron transit layer, a gate layer, constituted of a nitride semiconductor formed selectively on the electron supply layer, and a gate electrode formed on the gate layer, and the Al composition x of the electron supply layer is such that x ⁇ 0.3.
- the Al composition x of the electron supply layer constituted of Al x Ga 1 ⁇ x N (x ⁇ 1), is such that x ⁇ 0.3, and therefore both high sheet carrier density and high gate threshold voltage can be realized at the same time.
- a thickness of the electron supply layer may be not more than 10 nm.
- the nitride semiconductor device may include a source electrode and a drain electrode disposed to sandwich the gate electrode, and portions or entireties of the electron supply layer and the etching stop layer may be removed selectively in formation regions of the source electrode and the drain electrode.
- the electron transit layer may contain Mg as an impurity.
- a concentration of Mg in the electron transit layer may be not less than 1 ⁇ 10 16 cm ⁇ 3 and not more than 1 ⁇ 10 17 cm ⁇ 3 .
- the gate electrode may contain Ni, Pt, Mo, W, or TiN.
- FIG. 5 is an energy band diagram of the nitride semiconductor device.
- FIG. 10A to FIG. 10C are energy band diagrams showing movements of electrons with time until the electrons begin to flow.
- FIG. 13 is a diagram (simulation results) of a relationship of Al composition of an electron supply layer and d G ⁇ square root over (N DA +N A ⁇ N DD ⁇ N D ) ⁇ of the nitride semiconductor device according to the reference embodiment of the present invention.
- FIG. 15 is an energy band diagram (simulation results) of a nitride semiconductor device according to a preferred embodiment of the present invention.
- FIG. 16 is a diagram (simulation results) of a relationship of Al composition of an electron supply layer and d G ⁇ square root over (N DA +N A ⁇ N DD ⁇ N D ) ⁇ of the nitride semiconductor device according to the preferred embodiment of the present invention.
- FIG. 17 is a diagram (simulation results) of a relationship of gate voltage and current density of the nitride semiconductor device according to the preferred embodiment of the present invention.
- FIG. 19 is a diagram showing relationships of the Al composition of the electron supply layer and film thickness of the electron supply layer according to sheet carrier density.
- FIG. 21D is a diagram of a process subsequent that of FIG. 21C .
- FIG. 22 is a diagram of GaN Fermi level dependence of the gate threshold voltage.
- FIG. 23 is a diagram of the GaN Fermi level dependence of the gate threshold voltage.
- FIG. 24 is a diagram of the GaN Fermi level dependence of the gate threshold voltage.
- FIG. 25 is a diagram of the GaN Fermi level dependence of the gate threshold voltage.
- FIG. 26 is a diagram showing the GaN Fermi level dependence of the gate threshold voltage according to acceptor concentration of an electron transit layer.
- FIG. 27 is a sectional view for describing the arrangement of a nitride semiconductor device according to a preferred embodiment of a second invention.
- FIG. 28A is a diagram of a portion of a manufacturing process of the nitride semiconductor device of FIG. 27 .
- FIG. 28B is a diagram of a process subsequent that of FIG. 28A .
- FIG. 28C is a diagram of a process subsequent that of FIG. 28B .
- FIG. 28D is a diagram of a process subsequent that of FIG. 28C .
- FIG. 28F is a diagram of a process subsequent that of FIG. 28E .
- FIG. 28G is a diagram of a process subsequent that of FIG. 28F .
- FIG. 29 is a sectional view of the arrangement of a nitride semiconductor device according to a comparative example.
- FIG. 30 is an energy band diagram showing an energy distribution of the comparative example.
- FIG. 31 is an electric field intensity distribution diagram showing an electric field intensity distribution of the comparative example.
- FIG. 32 is an energy band diagram showing an energy distribution of the preferred embodiment.
- FIG. 33 is an electric field intensity distribution diagram showing an electric field intensity distribution of the preferred embodiment.
- FIG. 34 is an energy band diagram showing an energy distribution in a case where a gate insulating film is constituted of SiO 2 .
- FIG. 35 is an electric field intensity distribution diagram showing an electric field intensity distribution in the case where the gate insulating film is constituted of SiO 2 .
- FIG. 1 is an external view of a semiconductor package 1 that includes a nitride semiconductor device 3 according to the first preferred embodiment of the present invention.
- the semiconductor package 1 includes a terminal frame 2 , the nitride semiconductor device 3 (chip), and a resin package 4 .
- the terminal frame 2 has the form of a plate made of a metal.
- the terminal frame 2 includes a base portion 5 (island), supporting the nitride semiconductor device 3 , a drain terminal 6 , a source terminal 7 , and a gate terminal 8 .
- the drain terminal 6 is formed integral to the base portion 5 .
- the drain terminal 6 , the source terminal 7 , and the gate terminal 8 are electrically connected respectively by bonding wires 9 to 11 to a drain, a source, and a gate of the nitride semiconductor device 3 .
- the source terminal 7 and the gate terminal 8 are disposed so as to sandwich the drain terminal 6 at a center.
- the resin package 4 is constituted, for example, of a known molding resin, such as an epoxy resin, etc., and seals the nitride semiconductor device 3 .
- the resin package 4 covers the nitride semiconductor device 3 together with the base portion 5 of the terminal frame 2 and the bonding wires 9 to 11 . Portions of the three terminals 6 to 8 are exposed from the resin package 4 .
- FIG. 2 is a schematic sectional view of the nitride semiconductor device 3 of FIG. 1 .
- FIG. 2 does not show a section plane at a specific position of FIG. 1 but shows an assembly of elements, considered necessary for describing the present preferred embodiment, in a single section.
- the nitride semiconductor device 3 includes a substrate 12 , an electron transit layer 13 on the substrate 12 , and an electron supply layer 14 on the electron transit layer 13 .
- the electron transit layer 13 and the electron supply layer 14 are formed on the substrate 12 , for example, by an epitaxial growth method.
- a buffer layer constituted of AlN or AlGaN, etc., may be interposed as necessary between the substrate 12 and the electron transit layer 13 .
- the nitride semiconductor device 3 further includes a gate layer 15 , formed selectively on the electron supply layer 14 , arid a gate electrode 16 , formed on the gate layer 15 .
- the gate electrode 16 faces the electron supply layer 14 via the gate layer 15 .
- a surface insulating film 17 is formed on the electron supply layer 14 so as to cover the gate electrode 16 .
- Contact holes 18 a and 19 a selectively exposing portions of the electron supply layer 14 , are formed in the surface insulating film 17 , and a source electrode 18 and a drain electrode 19 are put in ohmic contact with the electron supply layer 14 via the contact holes 18 a and 19 a.
- the source electrode 18 and the drain electrode 19 are disposed across an interval and the gate electrode 16 is disposed therebetween.
- the source electrode 18 is formed in a pattern that covers the gate electrode 16 via the surface insulating film 17 .
- the substrate 12 may, for example, be a conductive silicon substrate.
- the conductive silicon substrate may have an impurity concentration, for example, of 1 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 20 cm ⁇ 3 (and more specifically, approximately 1 ⁇ 10 18 cm ⁇ 3 ).
- the gate layer 15 may, for example, be an undoped GaN layer.
- undoped GaN signifies GaN that effectively does not contain an acceptor type impurity and is specifically GaN with which an impurity is not intentionally introduced when forming the gate layer 15 and is more specifically GaN with a concentration of, for example, less than 1 ⁇ 10 17 cm ⁇ 3 and more preferably less than 1 ⁇ 10 16 cm ⁇ 3 . This is because if the impurity concentration contained in the gate layer 15 is of approximately such level, the impurity will not function as an acceptor.
- the impurity concentrations may be determined by performing SIMS (secondary ion mass spectroscope) analysis on the gate layer 15 .
- the electron transit layer 13 is constituted of a GaN layer
- the electron supply layer 14 is constituted of an Al x Ga 1 ⁇ x N layer (0 ⁇ x ⁇ 1).
- the electron transit layer 13 and the electron supply layer 14 are thus constituted of nitride semiconductors that differ mutually in composition and form a heterojunction. Therefore, as shown in FIG. 3 , in addition to spontaneous polarizations P sp(GaN) and P sp(AlGaN) occurring in the layers 13 and 14 due to configurations of respective atoms in interiors of crystal structures, a piezo polarization P pz(AlGaN) , due to lattice mismatch of the two, occurs in the electron supply layer 14 .
- positive polarization charges 20 are generated in a portion of the electron supply layer 14 near an interface (GaN/AlGaN heterointerface) with the electron transit layer 13 .
- the magnitude (P) of the polarization charges 20 is expressed by the following formula (2) using the abovementioned spontaneous polarizations and the piezo polarization and, as shown in FIG. 4 , increases substantially linearly in proportion to an Al composition of the electronic supply layer 14 (AlGaN).
- the bonding wires 9 to 11 are connected respectively to the drain electrode 19 , the source electrode 18 , and the gate electrode 16 .
- a rear surface electrode 22 is formed on a rear surface of the substrate 12 and the substrate 12 is connected to the base portion 5 via the rear surface electrode 22 . Therefore, with the present preferred embodiment, the substrate 12 is electrically connected to the drain electrode 19 via the bonding wire 9 and thereby set at a drain potential.
- the positive polarization charges 20 are generated in the portion of the electron supply layer 14 near the interface (GaN/AlGaN heterointerface) with the electron transit layer 13 .
- the entire system of the junction (AlGaN/GaN junction) of the electron supply layer 14 and the electron transit layer 13 positive spatial charges are canceled out by negative spatial charges so that the total of the spatial charges is zero and therefore in correspondence to the positive polarization charges 20 inside the electron supply layer 14 , the two-dimensional electron gas 21 , constituted of negative spatial charges, is generated in the electron transit layer 13 (GaN) that has a bandgap smaller than the electron supply layer 14 (AlGaN).
- the gate layer 15 constituted of GaN, which has a smaller bandgap than the electron supply layer 14 (AlGaN), and effectively not containing an acceptor type impurity, is interposed between the electron supply layer 14 and the gate electrode 16 to realize a normally-off type device.
- the mechanism by which a normally-off arrangement is realized in the present invention is as follows. That is, in principle, the positive polarization charges 20 are canceled out by a spontaneous polarization P sp(GaN-Gate) occurring inside the gate layer 15 and consequently, the two-dimensional electron gas 21 is eliminated selectively from a gate region Ga in which the gate electrode 16 is disposed. That is, it suffices to provide an arrangement where the spontaneous polarization ( ⁇ P sp(GaN-Gate) ) of the gate layer 15 is added to the formula (2) above and the magnitude P of the polarization charges 20 is as indicated by the following formula (3).
- the magnitude of the polarization charges 20 is dependent on the Al composition of the electron supply layer 14 (AlGaN) as shown in FIG. 4 . It is thus necessary to set conditions of the gate layer 15 and the electron transit layer 13 in accordance with physical properties of the electron supply layer 14 to reliably suppress the polarization charges 20 in the gate region Ga.
- the conditions are set so that in FIG. 5 , (P 2 )+(P 3 ) ⁇ (P 1 )>0 is satisfied for increments/decrements (P 1 ), (P 2 ), and (P 3 ) of the potential of a conduction band E C between the gate electrode 16 and a potential well 23 , formed at the junction interface (GaN/AlGaN interface) of the electron transit layer 13 and the electron supply layer 14 .
- This is because it will thereby become necessary to apply a positive voltage to the gate electrode 16 to lower the potential of the conduction band E C of the potential well 23 to a position lower than a Fermi level (at the position of 0.0 eV in FIG. 5 ) and make the drain current flow.
- the ordinate indicates the potential with respect to electrons.
- FIG. 6 when expressed as an electric field intensity distribution, the conditions of FIG. 5 will be as shown in FIG. 6 .
- a black solid line indicates the electric field intensities at the respective layers when the threshold voltage Vth of 1.0 V is applied, to the gate electrode 16 .
- an electric field intensity integration value A (hatched portion in FIG. 6 ) of the AlGaN electron supply layer 14 and an electric field intensity integration value B (cross-hatched portion in FIG. 6 ) of the GaN gate layer 15 satisfy B>A to realize a normally-off arrangement.
- the internal electric field of the electron supply layer 14 is thereby canceled out by the internal electric field of the gate layer 15 and therefore the generation of the two-dimensional electron gas 21 is suppressed.
- the first term, the second, term, and the third term from the left respectively correspond to the decrement (P 2 ), the decrement (P 3 ), and the increment (P 1 ) of the potential of the conduction band E C .
- the definitions of the respective symbols in the formula (1) are as follows.
- d B P/ ⁇ 0 ⁇ B corresponding to the increment (P 1 ) of the potential of the conduction band E C .
- d B P/ ⁇ 0 ⁇ B which is the increment (P 1 ) of the potential of the conduction band E C , increases proportionally with an increase in the thickness d B of the electron supply layer 14 and therefore in regard to d B P/ ⁇ 0 ⁇ B , it is preferable for the thickness d B to be as small as possible. Therefore, although when the thickness d B exceeds 20 nm, a satisfactory sheet carrier density can be achieved, the increment (P 1 ) of the potential of the conduction band E C becomes large, and it is thus preferable for the thickness d B of the electron supply layer 14 to be not more than 20 nm and not more than 30 nm at the most.
- the increase in d B P/ ⁇ 0 ⁇ B in FIG. 8 is also small because the film thickness is small, and both high sheet carrier density and high gate threshold voltage can be realized at the same time.
- the Al composition of the AlGaN electron supply layer 14 is large and the AlGaN electron supply layer 14 is thin, AlGaN itself is readily oxidized, for example, when performing etching of the GaN gate layer 15 on the AlGaN electron supply layer 14 using a plasma of a mixed gas of Cl 2 and O 2 .
- the ranges of physical properties of the electron supply layer 14 are a thickness d B of not more than 30 nm (more preferably not more than 20 nm and not less than 3 nm) and an Al composition of not more than 25% . If the thickness d B of the electron supply layer 14 is not less than 3 nm, the occurrence of direct tunneling due to the electron supply layer 14 being too thin can be prevented and a gate leak current can be reduced.
- the electron supply layer 14 may be an undoped AlGaN layer.
- AlGaN signifies AlGaN that effectively does not contain an acceptor type impurity and is specifically AlGaN with which an impurity is not intentionally introduced when forming the electron supply layer 14 .
- FIG. 9 is a diagram of relationships of physical properties of the electron supply layer 14 and d G ⁇ square root over (N DA +N A ⁇ N DD ⁇ N D ) ⁇ , which is a portion of the decrement (P 2 ) of the potential of the conduction band E C , and shows preferable ranges of d G ⁇ square root over (N DA +N A ⁇ N DD ⁇ N D ) ⁇ for a plurality of combinations of the thickness d B and the Al composition.
- the upper side is a range in which a normally-off arrangement can be realized and the lower side is a range in which a normally-on arrangement is realized. Therefore, for each thickness d B and Al composition of the electron supply layer 14 , the value of d G ⁇ square root over (N DA +N A ⁇ N DD ⁇ N D ) ⁇ is set as suited so as to be included in the range higher than the corresponding graph in FIG. 9 .
- a shallow donor level E D a deep donor level E DD , a shallow acceptor level E A , and a deep acceptor level E DA are formed.
- the deep donor level E DD is, for example, an energy level at a position separated by not less than 0.025 eV from the lower end (bottom) energy level E C of the conduction band of the electron transit layer 13 . That is, the deep donor level E DD is formed by doping of a donor, with which an ionization energy necessary for excitation is greater than the thermal energy at room temperature. Therefore, ordinarily, the donor electrons doped at this position are not excited to the conduction band and are in a state of being captured by the donor at room temperature.
- the deep donor level E DD may, for example, be that due to a crystal defect occurring spontaneously in GaN during epitaxial growth of the electron transit layer 13 .
- the shallow acceptor level E A is, for example, an energy level at a position separated by not more than 0.025 eV from an upper end (top) energy level E V of valence electrons of the electron transit layer 13 and may be referred to simply as the “acceptor level E A ” as long as distinction can be made with respect to the deep acceptor level E DA .
- acceptor level E A an energy level at a position separated by not more than 0.025 eV from an upper end (top) energy level E V of valence electrons of the electron transit layer 13 and may be referred to simply as the “acceptor level E A ” as long as distinction can be made with respect to the deep acceptor level E DA .
- an impurity doped into the electron transit layer 13 constituted of GaN, to form the deep acceptor level E DA
- at least one type selected from the group consisting of C, Be, Cd, Ca, Cu, Ag, Au, Sr, Ba, Li, Na, K, Sc, Zr, Fe, Co, Ni, Mg, Ar, and He can be cited.
- Mg is preferably contained in a region in the electron transit layer 13 that is within 150 nm from the interface with the electron supply layer 14 .
- a region of the GaN electron transit layer 13 in which the energy band is curved is approximately 150 nm from the AlGaN electron supply layer 14 /GaN electron transit layer 13 interface. That is, this is because the region within 150 nm from the interface contributes to the threshold voltage and the concentrations and types of impurities in this region are important.
- C may also be used as the deep acceptor.
- C When C is used for the deep acceptor level, it is known to form, for example, a level of 0.9 eV from the upper end (top) energy level E V of the valence band of the electron transit layer 13 .
- E V the upper end (top) energy level
- Mg Mg
- it is known to form a level of 0.1 to 0.2 eV from E V .
- FIG. 10A when a voltage is not applied across both electrodes (unbiased state), the acceptors and the deep acceptors capture electrons emitted by the donors and the deep donors. In this state, positive charges, due to the donors and the deep donors that emitted the electrons, and negative charges, due to the acceptors and the deep acceptors that captured the electrons, are equal in number and therefore the GaN layer is electrically neutral as a whole.
- the thickness d G of the gate layer 15 is preferably, for example, 50 nm to 100 nm.
- (N DA +N A ⁇ N DD ⁇ N D ) is not less than 5 ⁇ 10 16 cm ⁇ 3 . This preferable range of (N DA +N A ⁇ N DD ⁇ N D ) can be explained with reference to FIG 11 .
- the threshold voltage in this state is 0.3 eV and a normally-off operation is narrowly realized. From this, it can be understood that for a normally-off operation, (N DA +N A ⁇ N DD ⁇ N D ) of at least 5 ⁇ 10 16 cm ⁇ 3 is necessary.
- ⁇ B work function (eV) of the gate electrode 16 ⁇ electron affinity (3.6 eV) of GaN
- ⁇ B work function (eV) of the gate electrode 16 ⁇ electron affinity (3.6 eV) of GaN
- the electron transit layer contains Ga and N in its composition and differs in Al composition from the electron supply layer.
- the electron supply layer and the electron transit layer differing in Al composition a lattice mismatch arises between the two and carriers due to polarization are thereby made to contribute to the forming of a two-dimensional electron gas.
- silicon was taken up as an example of the material of the substrate 12 , besides this, any substrate material, such as a sapphire substrate, a GaN substrate, etc., may be applied.
- An external view of a semiconductor package 1 that includes a nitride semiconductor device 3 according to the second preferred embodiment is the same as the external view of the semiconductor package 1 that includes the nitride semiconductor device 3 according to the first preferred embodiment of the first invention described using FIG. 1 .
- the semiconductor package 1 which includes the nitride semiconductor device 3 according to the second preferred embodiment, includes a terminal frame 2 , the nitride semiconductor device 3 (chip), and a resin package 4 .
- the terminal frame 2 has the form of a plate made of a metal.
- the terminal frame 2 includes a base portion 5 (island), supporting the nitride semiconductor device 3 , a drain terminal 6 , a source terminal 7 , and a gate terminal 8 .
- the drain terminal 6 is formed integral to the base portion 5 .
- the drain terminal 6 , the source terminal 7 , and the gate terminal 8 are electrically connected respectively by bonding wires 9 to 11 to a drain, a source, and a gate of the nitride semiconductor device 3 .
- the source terminal 7 and the gate terminal 8 are disposed so as to sandwich the drain terminal 6 at a center.
- the resin package 4 is constituted, for example, of a known molding resin, such as an epoxy resin, etc., and seals the nitride semiconductor device 3 .
- the resin package 4 covers the nitride semiconductor device 3 together with the base portion 5 of the terminal frame 2 and the bonding wires 9 to 11 . Portions of the three terminals 6 to 8 are exposed from the resin package 4 .
- a schematic sectional view of the nitride semiconductor device 3 according to the second preferred embodiment is the same as the schematic sectional view of the nitride semiconductor device 3 according to the first preferred embodiment described using FIG. 2 .
- the nitride semiconductor device 3 includes a substrate 12 , and an electron supply layer 14 on the electron transit layer 13 .
- the electron transit layer 13 and the electron supply layer 14 are formed on the substrate 12 , for example, by an epitaxial growth method.
- a buffer layer constituted of AlN or AlGaN, etc., may be interposed as necessary between the substrate 12 and the electron transit layer 13 .
- the nitride semiconductor device 3 further includes a gate layer 15 , formed selectively on the electron supply layer 14 , and a gate electrode 16 , formed on the gate layer 15 .
- the gate electrode 16 faces the electron supply layer 14 via the gate layer 15 .
- a surface insulating film 17 is formed on the electron supply layer 14 so as to cover the gate electrode 16 .
- contact holes 18 a and 19 a selectively exposing portions of the electron supply layer 14 , are formed in the surface insulating film 17 , and a source electrode 18 and a drain electrode 19 are put in ohmic contact with the electron supply layer 14 via the contact holes 18 a and 19 a.
- the source electrode 18 and the drain electrode 19 are disposed across an interval and the gate electrode 16 is disposed therebetween. Also, the source electrode 18 is formed in a pattern that covers the gate electrode 16 via the surface insulating film 17 .
- the substrate 12 may, for example, be a conductive silicon substrate.
- the conductive silicon substrate may have an impurity concentration, for example, of 1 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 20 cm ⁇ 3 (and more specifically, approximately 1 ⁇ 10 18 cm ⁇ 3 ).
- the gate layer 15 may, for example, be an undoped GaN layer or may be a GaN layer containing an acceptor type level.
- undoped GaN signifies GaN that effectively does not contain an acceptor type impurity.
- it is GaN with which an impurity is not intentionally introduced when forming the gate layer 15 and is more specifically GaN with a concentration of, for example, less than 1 ⁇ 10 17 cm ⁇ 3 and more preferably less than 1 ⁇ 10 16 cm ⁇ 3 . This is because if the impurity concentration contained in the gate layer 15 is of approximately such level, the impurity will not function as an acceptor.
- the impurity concentrations may be determined by performing SIMS (secondary ion mass spectroscope) analysis on the gate layer 15 .
- the GaN layer that includes the acceptor type level may contain, for example, Mg or C as the acceptor or may have a hole defect formed therein.
- the electron transit layer 13 is constituted of a GaN layer
- the electron supply layer 14 is constituted of an Al x Ga 1 ⁇ x N layer (0 ⁇ x ⁇ 1) and may contain In as necessary.
- the electron transit layer 13 and the electron supply layer 14 are thus constituted of nitride semiconductors that differ mutually in composition and form a heterojunction. Therefore, as shown in FIG. 3 , in addition to spontaneous polarizations P sp(GaN) and P sp(AlGaN) occurring in the layers 13 and 14 due to configurations of respective atoms in interiors of crystal structures, a piezo polarization P pz(AlGaN) , due to lattice mismatch of the two, occurs in the electron supply layer 14 .
- positive polarization charges 20 are generated in a portion of the electron supply layer 14 near an interface (GaN/AlGaN heterointerface) with the electron transit layer 13 .
- the magnitude (P) of the polarization charges 20 is expressed by the following formula (2) using the spontaneous polarizations and the piezo polarization and, as shown in FIG. 4 , increases substantially linearly in proportion to the Al composition of the electronic supply layer 14 (AlGaN).
- a large internal electric field is generated due to the polarization charges 20 and a two-dimensional electron gas 21 spreads as shown in FIG. 2 .
- the bonding wires 9 to 11 are connected respectively to the drain electrode 19 , the source electrode 18 , and the gate electrode 16 .
- a rear surface electrode 22 is formed on a rear surface of the substrate 12 and the substrate 12 is connected to the base portion 5 via the rear surface electrode 22 . Therefore, with the present preferred embodiment, the substrate 12 is electrically connected to the drain electrode 19 via the bonding wire 9 and thereby set at the drain potential.
- FIG. 5 is an energy band diagram of the nitride semiconductor device 3 .
- FIG. 6 is a diagram of the electric field intensity distribution of the nitride semiconductor device 3 .
- the positive polarization charges 20 are generated in the portion of the electron supply layer 14 near the interface (GaN/AlGaN heterointerface) with the electron transit layer 13 .
- the entire system of the junction (AlGaN/GaN junction) of the electron supply layer 14 and the electron transit layer 13 positive spatial charges are canceled out by negative spatial charges so that the total of the spatial charges is zero and therefore in correspondence to the positive polarization charges 20 inside the electron supply layer 14 , the two-dimensional electron gas 21 , constituted of negative spatial charges, is generated in the electron transit layer 13 (GaN) that has a bandgap smaller than the electron supply layer 14 (AlGaN).
- the two-dimensional electron gas 21 serves as a passage (channel) for electrons between the source and the drain.
- a so-called normally-on type arrangement is realized in which a current flows between the source and the drain due to the potential difference between the source and the drain even when a voltage is not applied to the gate electrode 16 .
- the gate layer 15 constituted of GaN, which has a smaller bandgap than the electron supply layer 14 (AlGaN), and effectively not containing an acceptor type impurity, is interposed between the electron supply layer 14 and the gate electrode 16 to realize a normally-off type device.
- the magnitude of the polarization charges 20 is dependent on the Al composition of the electron supply layer 14 (AlGaN) as shown in FIG. 4 .
- the ordinate indicates the potential with respect to electrons.
- a shallow donor level E D a deep donor level E DD , a shallow acceptor level E A , and a deep acceptor level E DA are formed.
- the shallow donor level E D is, for example, an energy level at a position separated by not more than 0.025 eV from the lower end (bottom) energy level E C of the conduction band of the electron transit layer 13 and may be referred to simply as the “donor level E D ” as long as distinction can be made with respect to the deep donor level E DD .
- As an impurity forming the shallow donor level E D for example, at least one type selected from the group consisting of Si and O can be cited. These may be incorporated into the film during epitaxial growth of the electron transit layer 13 or may be doped intentionally. For example, oxygen (O) maybe incorporated from a raw material gas or a carrier gas.
- the deep donor level E DD is, for example, an energy level at a position separated by not less than 0.025 eV from the lower end (bottom) energy level E C of the conduction band of the electron transit layer 13 . That is, the deep donor level E DD is formed by doping of a donor, with which an ionization energy necessary for excitation is greater than the thermal energy at room temperature. Therefore, ordinarily, the donor electrons doped at this position are not excited to the conduction band and are in a state of being captured by the donor at room temperature.
- the deep donor level E DD may, for example, be that due to a crystal defect occurring spontaneously in GaN during epitaxial growth of the electron transit layer 13 .
- the shallow acceptor level E A is, for example, an energy level at a position separated by not more than 0.025 eV from an upper end (top) energy level E V of valence electrons of the electron transit layer 13 and may be referred to simply as the “acceptor level E A ” as long as distinction can be made with respect to the deep acceptor level E DA .
- the deep acceptor level E DA is, for example, an energy level at a position separated by not less than 0.025 eV from the upper end (top) energy level E V of the valence electrons of the electron transit layer 13 . That is, the deep acceptor level E DA is formed by doping of an acceptor, with which an ionization energy necessary for excitation is greater than the thermal energy at room temperature. Therefore ordinarily, the acceptor holes doped at this position are not excited to the valence band and are in a state of being captured by the acceptor at room temperature.
- an impurity doped into the electron transit layer 13 constituted of GaN, to form the deep acceptor level E DA
- at least one type selected from the group consisting of C, Be, Cd, Ca, Cu, Ag, Au, Sr, Ba, Li, Na, K, Sc, Zr, Fe, Co, Ni, Mg, Ar, and He can be cited.
- C and Mg can be cited mainly, carbon (C) functions as a deep acceptor when incorporated, in a nitrogen site inside GaN and functions as a shallow donor when incorporated in a Ga site, and therefore, to increase (N DA +N A ⁇ N DD ⁇ N D ) reliably, it is preferable to use Mg.
- a region of the electron transit layer 13 in which the energy band is curved depends on the type (Fermi level) of impurity and (N DA +N A ⁇ N DD ⁇ N D ).
- the region of the electron transit layer 13 in which Mg is contained depends on the Mg concentration. For example, in FIG.
- the impurity is Mg and (N DA +N A ⁇ N DD ⁇ N D ) is 1 ⁇ 10 17 cm ⁇ 3
- the region of the GaN electron transit layer 13 in which the energy band is curved is approximately 150 nm from the AlGaN electron supply layer 14 /GaN electron transit layer 13 interface.
- the impurity is Mg and (N DA +N A ⁇ N DD ⁇ N D ) is 4 ⁇ 10 16 cm ⁇ 3
- the region in which the energy band is curved is approximately 250 nm from the AlGaN electron supply layer 14 /GaN electron transit layer 13 interface. That is, this is because the region within the abovementioned upper limit from the AlGaN electron supply layer 14 /GaN electron transit layer 13 interface contributes to the threshold voltage and the concentrations and types of impurities in this region are important.
- C may also be used as the deep acceptor.
- C When C is used for the deep acceptor level, it is known to form, for example, a level of 0.9 eV from the upper end (top) energy level E V of the valence band of the electron transit layer 13 .
- E V the upper end (top) energy level
- Mg Mg
- it is known to form a level of 0.1 to 0.2 eV from E V .
- the leak current is increased by the formed hole acting as a carrier.
- an impurity with which the deep acceptor level will be at a position separated from E V by more than 0.2 eV and, for example, not less than 0.3 eV, is preferable, and C satisfies this condition.
- Concentrations of the impurities (dopants) forming the shallow donor level E D , the deep donor level E DD , the shallow acceptor level E A , and the deep acceptor level E DA described above shall be referred to respectively as a shallow donor concentration N D , a deep donor concentration N DD , a shallow acceptor concentration N A , and a deep acceptor concentration N DA .
- a shallow donor concentration N D a deep donor concentration
- N DD a deep donor concentration
- N A shallow acceptor concentration
- N DA a deep acceptor concentration N DA
- concentrations N D , N DD , N A , and N DA may be measured, for example, by SIMS (Secondary Ion Mass Spectrometry).
- FIG. 10A when a voltage is not applied across both electrodes (unbiased state), the acceptors and the deep acceptors capture electrons emitted by the donors and the deep donors. In this state, positive charges, due to the donors and the deep donors that emitted the electrons, and negative charges, due to the acceptors and the deep acceptors that captured the electrons, are equal in number and therefore the GaN layer is electrically neutral as a whole.
- Preferable ranges of d G and (N DA +N A ⁇ N DD ⁇ N D ) that constitute d G ⁇ square root over (N DA +N A ⁇ N DD ⁇ N D ) ⁇ are, for example, as indicated below.
- the preferable ranges indicated below differ according to the respective thicknesses d B and Al compositions of the electron supply layer 14 and may therefore be set as suited in accordance with the respective thicknesses d B and Al compositions of the electron supply layer 14 .
- the thickness d G of the gate layer 15 is preferably, for example, 50 nm to 200 nm.
- (N DA +N A ⁇ N DD ⁇ N D ) of the electron transit layer 13 is, for example, 1 ⁇ 10 16 cm ⁇ 3 to 5 ⁇ 10 17 cm ⁇ 3 and preferably, the Mg concentration is not less than 1 ⁇ 10 16 cm ⁇ 3 and more preferably, the Mg concentration is not more than 1 ⁇ 10 17 cm ⁇ 3 .
- ⁇ B work function (eV) of the gate electrode 16 ⁇ electron affinity (3.6 eV) of GaN
- ⁇ B work function (eV) of the gate electrode 16 ⁇ electron affinity (3.6 eV) of GaN
- d B P/ ⁇ 0 ⁇ B corresponding to the increment (P 1 ) of the potential of the conduction band E C .
- d B P/ ⁇ 0 ⁇ B which is the increment (P 1 ) of the potential of the conduction band E C , increases proportionally with an increase in the thickness d B of the electron supply layer 14 and therefore if making d B P/ ⁇ 0 ⁇ B small is considered with priority, it is preferable for the thickness d B to be as small as possible. It is thus preferable for the thickness d B of the electron supply layer 14 to be as small as possible within a range of not more than 10 nm.
- the sheet carrier density decreases.
- the decrease is especially significant in a region of d B ⁇ 5 nm.
- the sheet carrier density is preferably, for example, not less than 6.0 ⁇ 10 12 cm ⁇ 2 because if it is too low, channel mobility decreases.
- the Al composition of the electron supply layer 14 should thus be set in a range of not more than 10 nm along the abscissa and not less than 6.0 ⁇ 10 12 cm ⁇ 2 along the ordinate in FIG. 7 .
- the Al composition is in a proportional relationship with the variable P in d B P/ ⁇ 0 ⁇ B , which corresponds to the increment (P 1 ) of the potential of the conduction band E C and, depending on the case, influences the gate threshold voltage. Relationships of the Al composition of the electron supply layer 14 and the gate threshold voltage were thus examined.
- FIG. 18 is a diagram showing relationships of the Al composition of the electron supply layer 14 and the gate threshold voltage according to sheet carrier density.
- FIG. 15 is a diagram showing relationships of the Al composition of the electron supply layer 14 and the film thickness of the electron supply layer 14 according to sheet carrier density.
- FIG. 18 and FIG. 19 calculations were made with the deep acceptor concentration of the gate layer 15 being set to 2 ⁇ 10 17 cm ⁇ 3 and the deep acceptor concentration of the electron transit layer 13 being set to 4 ⁇ 10 16 cm ⁇ 3 .
- the Al composition and the sheet carrier density N S of the electron supply layer 14 at which the gate threshold voltage exceeds 0 V are determined from the graphs of FIG. 18 and the readings are applied to the graphs of the FIG. 19 to read the thickness d B (film thickness).
- the thickness d B film thickness
- the channel mobility may decrease due to alloy scattering. Therefore, to suppress alloy scattering and make the gate threshold voltage high, it is preferable to use an AlN electron supply layer 14 .
- the electron supply layer 14 is an AlN layer, a problem occurs in that the AlN layer itself becomes oxidized entirely when the gate layer 15 is formed, for example, by etching with Cl 2 /O 2 (see FIG. 21C described below).
- the electron supply layer 14 is to be made an AlN layer, it is preferable to dispose an etching stop layer 24 , constituted of Al x Ga 1 ⁇ x′ N (x′ ⁇ 1), on the electron supply layer 14 as shown in FIG. 20 .
- the AlN electron supply layer 14 is thereby covered by etching stop layer 24 in the process of etching the gate layer 15 and the oxidation of the AlN electron supply layer 14 can thus be suppressed.
- the effect of suppressing the oxidation of the electron supply layer 14 such as described above is not restricted to an AlN layer and can be achieved when the etching stop layer 24 , constituted of Al x′ Ga 1 ⁇ x′ N (x′ ⁇ 1), is formed on an electron supply layer 14 constituted of Al x Ga 1 ⁇ x N (x ⁇ 1) and a relationship, x ⁇ x′, is further established in regard to the Al composition.
- the etching stop layer 24 and the electron supply layer 14 are further removed selectively so as to be continuous with the contact holes 18 a and 19 a, and the source electrode 18 and the drain electrode 19 are put in ohmic contact with the electron transit layer 13 via the contact holes 18 a and 19 a.
- FIG. 21A to FIG. 21F are diagrams showing, in order of process, portions of a manufacturing process of the nitride semiconductor device 3 (third preferred embodiment) of FIG. 20 .
- the electrode material 26 is etched selectively to form the gate electrode 16 .
- the gate layer 15 is etched selectively using, for example, a Cl 2 /O 2 plasma. The etching stops at the AlGaN etching stop layer 24 .
- the surface insulating film 17 constituted, for example, of SiN, is formed so as to cover the etching stop layer 24 , the gate layer 15 , and the gate electrode 16 .
- the surface insulating film 17 , the etching stop layer 24 , and the electron supply layer 14 are continuously etched selectively to form the contact holes 18 a and 19 a.
- contact resistances of the source electrode 18 and the drain electrode 19 can be reduced by etching the electron supply layer 14 as well to expose the electron transit layer 13 .
- the source electrode 18 and the drain electrode 19 are formed.
- the rear surface electrode 22 , etc. the nitride semiconductor device 3 is obtained.
- FIG. 22 to FIG. 26 are diagrams of GaN Fermi level dependence of the gate threshold voltage.
- FIG. 24 is an energy band diagram of a turn-on state under conditions that are the same as those of FIG. 22 with the exception that N DA +N A ⁇ N DD ⁇ N D of the electron transit layer 13 is 1 ⁇ 10 17 cm ⁇ 3 .
- FIG. 25 is an energy band diagram of a turn-on state under conditions that are the same as those of FIG. 23 with the exception that N DA +N A ⁇ N DD ⁇ N D of the electron transit layer 13 is 1 ⁇ 10 17 cm ⁇ 3 .
- N DA +N A ⁇ N DD ⁇ N D in this case is preferably not less than 1 ⁇ 10 16 cm ⁇ 3 and not more than 1 ⁇ 10 18 cm ⁇ 3 .
- the electron transit layer 13 is constituted of GaN and the electron supply layer 14 is constituted of AlGaN or AlN was described, it suffices that the electron transit layer 13 and the electron supply layer 14 differ in Al composition and other combinations are also possible.
- the electron supply layer/electron transit layer combination may be any of AlGaN layer/GaN layer, AlGaN layer/AlGaN layer (with the layers differing in Al composition), AlInN layer/AlGaN layer, AlInN layer/GaN layer, AlN layer/GaN layer, and AlN layer/AlGaN layer.
- the electron supply layer contains Al and N in its composition.
- the electron transit layer contains Ga and N in its composition and differs in Al composition from the electron supply layer.
- the electron supply layer and the electron transit layer differing in Al composition a lattice mismatch arises between the two and carriers due to polarization are thereby made to contribute to the forming of a two-dimensional electron gas.
- the electron supply layer 14 is Al x Ga 1 ⁇ x N (x ⁇ 1) was mainly described, in a case where the electron supply layer 14 contains In, that is, with Al x In y Ga 1 ⁇ x ⁇ y N, x and y may be such that x ⁇ 0.3, 0.2 ⁇ y ⁇ 0, and 1 ⁇ x+y.
- silicon was taken up as an example of the material of the substrate 12 , besides this, any substrate material, such as a sapphire substrate, a GaN substrate, etc., may be applied.
- the second invention relates to a nitride semiconductor device constituted of a group III nitride semiconductor (may hereinafter be referred to simply as “nitride semiconductor” in some cases).
- a group III nitride semiconductor is a semiconductor with which nitrogen is used as a group V element in a group III-V semiconductor.
- Representative examples are aluminum, nitride (AlN), gallium nitride (GaN), and indium nitride (InN).
- AlN aluminum, nitride
- GaN gallium nitride
- InN indium nitride
- the semiconductor can be expressed generally as Al x In y Ga 1 ⁇ x ⁇ y N (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x+y ⁇ 1).
- Such an HEMT includes, for example, an electron transit layer, constituted of GaN, and an electron supply layer, constituted of AlGaN that is grown epitaxially on the electron transit layer.
- a pair of source electrode and drain electrode are formed to be in contact with the electron supply layer and a gate electrode is disposed therebetween. Due to polarization caused by lattice mismatch of GaN and AlGaN, a two-dimensional electron gas is formed inside the electron transit layer at a position located only a few ⁇ inward from an interface of the electron transit layer and the electron supply layer.
- the source and the drain are connected to each other with the two-dimensional electron gas as a channel.
- the source and the drain are cut off from each other.
- the source and the drain are continuous to each other in a state where the control voltage is not applied to the gate electrode and therefore the device is of the normally-on type.
- Devices using a nitride semiconductor have features of high withstand voltage, high temperature operation, high current density, high speed switching, and low on resistance and are thus being examined for application to power devices.
- a device for use as a power device, a device must be of the normally-off type, in which current is cut off in a zero bias state, and therefore an HEMT such as described above cannot be applied to a power device.
- Japanese Patent Application Publication No. 2006-339561 discloses an arrangement where a p type GaN gate layer (nitride semiconductor gate layer) is laminated on an AlGaN electron supply layer, a gate electrode is disposed thereon, and the channel is eliminated by a depletion layer spreading from the P type GaN gate layer to realize a normally-off arrangement.
- a gate electrode constituted of Pd (palladium) in ohmic junction with the p type GaN gate layer, is used as the gate electrode.
- a gate electrode constituted of TiN (titanium nitride) or other metal in Schottky junction with the p type GaN gate layer, as the gate electrode may be considered.
- a nitride semiconductor device of such an arrangement may be referred to in some cases as a compared device. With the compared device, there is a problem in that due to the nitride semiconductor gate layer and the gate electrode being in Schottky junction, a gate leak current becomes large and the nitride semiconductor gate layer degrades readily.
- An object of the second invention is to provide a nitride semiconductor device with which the gate leak current can be reduced in comparison to the compared device.
- the second invention has the following features.
- a nitride semiconductor device including a first nitride semiconductor layer, constituting an electron transit layer, a second nitride semiconductor layer, formed on the first nitride semiconductor layer, being larger in bandgap than the first nitride semiconductor layer, and constituting an electron supply layer, and a gate portion, disposed on the second nitride semiconductor layer, and where the gate portion includes a nitride semiconductor gate layer, disposed on the second nitride semiconductor layer and containing an acceptor type impurity, a gate insulating film, formed on the nitride semiconductor gate layer, and a gate electrode, formed on the gate insulating film.
- A4 The nitride semiconductor device according to any one of “A1.” to “A3.,” where the gate leak current is not more than 1 nA/mm.
- A5. The nitride semiconductor device according to any one of “A1.” to “A3.,” where the nitride semiconductor gate layer has a film thickness of not more than 100 nm and the gate insulating film has a film thickness of not less than 3 nm.
- A7 The nitride semiconductor device according to “A1.,” where a carbon concentration of an interface of the nitride semiconductor gate layer and the gate insulating film is not more than 1 ⁇ 10 13 cm ⁇ 2 .
- A8 The nitride semiconductor device according to any one of “A1.” to “A7.,” where the first nitride semiconductor layer is constituted of a GaN layer, the second nitride semiconductor layer is constituted of an AlGaN layer, and the nitride semiconductor gate layer is constituted of a p type GaN layer.
- the nitride semiconductor device according to “A6.”
- the first nitride semiconductor layer is constituted of a GaN layer
- the second nitride semiconductor layer is constituted of an AlGaN layer
- the nitride semiconductor gate layer is constituted of a p type GaN layer
- the third nitride semiconductor layer is constituted of an AlGaN layer.
- FIG. 27 is a sectional view for describing the arrangement of a nitride semiconductor device according to the preferred embodiment of the second invention.
- the nitride semiconductor device 1 includes a substrate 2 , a buffer layer 3 , formed on a front surface of the substrate 2 , a first nitride semiconductor layer 4 , grown epitaxially on the buffer layer 3 , and a second nitride semiconductor layer 5 , grown epitaxially on the first nitride semiconductor layer 4 . Further, the nitride semiconductor device 1 includes a gate portion 20 formed on the second nitride semiconductor layer 5 .
- the buffer layer 3 is constituted from a multilayer buffer layer in which a plurality of nitride semiconductor films are laminated.
- the buffer layer 3 is constituted from a first buffer layer 3 A, constituted of an AlN film in contact with the front surface of the substrate 2 , and a second buffer layer 3 B, constituted of an AlGaN film laminated on a front surface of the first buffer layer 3 A (the front surface at the side opposite the substrate 2 side).
- the first buffer layer 3 A has a film thickness of approximately 100 nm to 300 nm.
- the second buffer layer 3 B has a film thickness of approximately 100 nm to 5 ⁇ m.
- the first nitride semiconductor layer 4 constitutes an electron transit layer.
- the first nitride semiconductor layer 4 is constituted of a GaN layer doped with an acceptor type impurity and has a thickness of approximately 100 nm to 5 ⁇ m.
- the concentration of the acceptor type impurity is preferably not less than 4 ⁇ 10 16 cm ⁇ 3 .
- the acceptor type impurity is C (carbon).
- the gate portion 20 includes a nitride semiconductor gate layer 6 , grown epitaxially on the second nitride semiconductor layer 5 , a gate insulating film 7 , formed on the nitride semiconductor gate layer 6 , and a gate electrode 8 , formed on the gate insulating film 7 .
- the nitride semiconductor gate layer 6 is constituted of a nitride semiconductor doped with an acceptor type impurity.
- the nitride semiconductor gate layer 6 is constituted of a GaN layer (p type GaN layer) doped with the acceptor type impurity and has a thickness of approximately 10 nm to 100 nm.
- the film thickness of the nitride semiconductor gate layer 6 is preferably not more than 100 nm. The reason for this shall be described later. In the present preferred embodiment, the film thickness of the nitride semiconductor gate layer 6 is 60 nm.
- the concentration of the acceptor type impurity implanted in the nitride semiconductor gate layer 6 is preferably not less than 3 ⁇ 10 17 cm ⁇ 3 .
- the acceptor type impurity is Mg (magnesium).
- the acceptor type impurity may be Fe or other acceptor type impurity besides Mg.
- the nitride semiconductor gate layer 6 is disposed the two-dimensional electron gas 16 generated in the interface of the first nitride semiconductor layer 4 (electron transit layer) and the second nitride semiconductor layer 5 (electron supply layer).
- a front surface (upper surface) of the nitride semiconductor gate layer 6 is a c plane of a GaN crystal and a side surface of the nitride semiconductor gate layer 6 is an m plane of the GaN crystal.
- the gate insulating film 7 is formed to be in contact with the front surface (c plane) of the nitride semiconductor gate layer 6 .
- the gate insulating film 7 is constituted of in-situ SiN, formed as a film in-situ with the nitride semiconductor gate layer 6 .
- the gate insulating film 7 has a thickness of approximately 3 nm to 30 nm.
- the film thickness of the gate insulating film 7 is preferably not less than 3 nm. In the present preferred embodiment, the film thickness of the gate insulating film 7 is 30 nm.
- the gate insulating film 7 may be constituted from SiN (other than in-situ SiN), SiO 2 , SiON, Al 2 O 3 , AlN, AlON, HfO, HfN, HfON, HfSiON, AlON, etc.
- a carbon concentration of the interface of the nitride semiconductor gate layer 6 and the gate insulating film 7 is not more than 1 ⁇ 10 13 cm ⁇ 2 .
- the gate electrode 8 is formed to be in contact with a front surface of the gate insulating film 7 .
- the gate electrode 8 is constituted from a TiN layer and has a thickness of approximately 50 nm to 200 nm.
- the gate electrode 8 is disposed biasedly toward the source electrode contact hole 11 .
- the passivation film 9 covers a front surface of the second nitride semiconductor layer 5 (with the exception of regions facing the contact holes 11 and 12 ) and a side surface and a front surface of the gate portion 20 .
- the passivation film 9 is constituted of an SiN film and has a thickness of approximately 50 nm to 200 nm. In the present preferred embodiment, the thickness of the passivation film 9 is 50 nm.
- the barrier metal film 10 is laminated on the passivation film 9 .
- the barrier metal film 10 is constituted of a TiN film and has a thickness of approximately 10 nm to 50 nm. In the present preferred embodiment, the thickness of the barrier metal film 10 is 25 nm.
- the source electrode 13 and the drain electrode 14 are constituted of lower layers (ohmic metal layers) 13 A and 14 A, in contact with the second nitride semiconductor layer 5 , intermediate layers (main electrode metal layers) 13 B and 14 B, laminated on the lower layers 13 A and 14 A, and upper layers (barrier metal layers) 13 C and 14 C, laminated on the intermediate layers 13 B and 14 B.
- the lower layers 13 A and 14 A are, for example, Ti layers with thicknesses of approximately 10 nm to 20 nm.
- the intermediate layers 13 B and 14 B are Al layers with thicknesses of approximately 100 nm to 300 nm.
- the upper layers 13 C and 14 C are, for example, TiN with thicknesses of approximately 10 nm to 50 nm.
- the interlayer insulating film 15 is constituted, for example, of SiO 2 .
- the interlayer insulating film 15 has a thickness of approximately 1 ⁇ m.
- a heterojunction is formed by the second nitride semiconductor layer 5 (electron supply layer), differing in bandgap (Al composition) from the first nitride semiconductor layer 4 (electron transit layer), being formed on the first nitride semiconductor layer 4 .
- the two-dimensional electron gas 16 is thereby formed inside the first nitride semiconductor layer 4 near the interface of the first nitride semiconductor layer 4 and the second nitride semiconductor layer 5 , and an HEMT making use of the two-dimensional electron gas 16 as a channel is formed.
- the gate electrode 8 faces the second nitride semiconductor layer 5 across the gate insulating film 7 and the nitride semiconductor gate layer 6 , constituted of the p type GaN layer.
- the gate electrode 8 energy levels of the first nitride semiconductor layer 4 and the second nitride semiconductor layer 5 are pulled up by the ionized acceptors contained in the nitride semiconductor gate layer 6 , constituted of the p type GaN layer, and therefore the energy level of the conduction band at the heterojunction interface is made higher than the Fermi level. Therefore, the two-dimensional electron gas 16 , due to the spontaneous polarizations of the first nitride semiconductor layer 4 and the second nitride semiconductor layer 5 and the piezo polarization due to the lattice mismatch of the two layers, is not formed directly below the gate electrode 8 (gate portion 20 ).
- a predetermined voltage for example, of 200 V to 300 V
- an off voltage (0 V) or an on voltage (3 V) is applied to the gate electrode 8 with the source electrode 13 being at a reference potential (0 V).
- FIG. 28A to FIG. 28G are sectional views for describing an example of a manufacturing process of the nitride semiconductor device 1 described above and show a cross-sectional structure at a plurality of stages in the manufacturing process.
- the buffer layer 3 and the first nitride semiconductor layer (electron transit layer) 4 are successively grown epitaxially on the substrate 2 by an MOCVD (Metal Organic Chemical Vapor Deposition) method. Further, the second nitride semiconductor layer (electron supply layer) 5 is grown epitaxially on the first nitride semiconductor layer 4 by the MOCVD method.
- MOCVD Metal Organic Chemical Vapor Deposition
- a gate layer material film 31 which is a material film of the nitride semiconductor gate layer 6 , is formed on the second nitride semiconductor layer 5 by the MOCVD method.
- an insulating material film 32 which is a material film of the gate insulating film 7 , is formed on the gate layer material film 31 .
- the gate insulating film 7 is constituted of SiN
- film formation of the gate insulating film 32 may be performed in succession to and using the same MOCVD device used in film formation of the gate layer material film 31 .
- the insulating material film 32 becomes in-situ SiN, which is formed as a film in-situ with the gate layer material film 31 .
- the insulating material film 32 may also be formed as a film on the gate layer material film 31 by a plasma CVD method. Also, if the gate insulating film 7 is constituted of SiO 2 or other material besides SiN, the insulating material film 32 may be formed as a film on the gate layer material film 31 by the plasma CVD method, an LPCVD (Low Pressure CVD) method, an ALD (Atomic Layer Deposition) method, etc.
- a gate electrode film 33 which is a material film of the gate electrode 8 , is formed on the insulating material film 32 by a sputtering method or a vapor deposition method.
- the gate electrode film 33 is constituted, for example, of a metal film of TiN.
- a resist film 34 covering a region of a front surface of the gate electrode film 33 at which the preparation of the gate electrode is planned, is formed.
- the gate electrode film 33 , the insulating material film 32 , and the gate layer material film 31 are then etched selectively using the resist film 34 as a mask.
- the gate electrode film 33 is thereby patterned and the gate electrode 8 is obtained. Also, the insulating material film 32 and the gate layer material film 31 are patterned in the same pattern as the gate electrode 8 .
- the gate portion 20 constituted of the nitride semiconductor gate layer 6 , the gate insulating film 7 , and the gate electrode 8 , is thereby formed on the second nitride semiconductor layer 5 .
- the passivation film 9 is formed by the plasma CVD method or the LPCVD method so as to cover entireties of exposed front surfaces.
- the barrier metal film 10 is then formed on the front surface of the passivation film 9 by the sputtering method.
- the passivation film 9 is constituted, for example, of an SiN layer.
- the barrier metal film 10 is constituted, for example, of a TiN layer.
- the source electrode contact hole 11 and the drain electrode contact hole 12 are formed, in the laminated film of the passivation film 9 and the barrier metal film 10 .
- the source/drain electrode film 35 and the barrier metal film 10 are patterned by etching and further subject to an annealing processing to form the source electrode 13 and the drain electrode 14 in ohmic contact with the second nitride semiconductor layer 5 .
- the source electrode 13 is constituted from a lower-layer 13 A, constituted of the TiN layer 35 A, an intermediate layer 13 B, constituted of the Al layer 35 B, and an upper layer 13 C, constituted of the TiN layer 35 C.
- the drain electrode 14 is constituted from a lower layer 14 A, constituted of the TiN layer 35 A, an intermediate layer 14 B, constituted of the Al layer 35 B, and an upper layer 14 C, constituted of the TiN layer 35 C.
- the interlayer insulating film 15 is formed so as to cover the source electrode 13 , the drain electrode 14 , and the barrier metal film 10 , and the nitride semiconductor device 1 with the structure such as shown in FIG. 27 is thereby obtained.
- FIG. 29 is a sectional view of the arrangement of the nitride semiconductor device 101 according to the comparative example.
- a gate portion 20 is constituted of a nitride semiconductor gate layer 6 , formed on a second nitride semiconductor layer 5 , and a gate electrode 8 , formed on the nitride semiconductor gate layer 6 .
- the gate electrode 8 constituted of TiN, is in Schottky junction with the nitride semiconductor gate layer 6 , constituted of p type GaN.
- the nitride semiconductor gate layer 6 of the comparative example has a film thickness of 80 nm.
- the nitride semiconductor gate layer 6 of the nitride semiconductor device 1 described above has a film thickness of 60 nm and the gate insulating film 7 has a film thickness of 30 nm.
- the gate electrode 8 is in Schottky junction with the nitride semi conductor gate layer 6 and therefore the gate leak current is large.
- the nitride semiconductor gate layer 6 thus degrades readily.
- the gate insulating film 7 is formed on the nitride semiconductor gate layer 6 and the gate electrode 8 is formed on the gate insulating film 7 . That is, with the present preferred embodiment, the gate insulating film 7 is interposed between the nitride semiconductor gate layer 6 and the gate electrode 8 , and therefore the gate leak current can be made small in comparison to the comparative example. The nitride semiconductor gate layer 6 is thereby made unlikely to degrade. With the present preferred embodiment, the gate leak current is not more than 1 nA/mm.
- a threshold voltage Vth can be made high in comparison to the comparative example. Also, with the present preferred embodiment, it is possible to make the nitride semiconductor gate layer 6 thin in comparison to the comparative example, and it is therefore possible to reduce the electric field intensity of the nitride semiconductor gate layer 6 and the nitride semiconductor gate layer 6 is made unlikely to undergo time dependent dielectric breakdown (TDDB). Further, with the present preferred embodiment, the threshold voltage Vth can be stabilized in comparison to the comparative example.
- TDDB time dependent dielectric breakdown
- the threshold voltage Vth can be made high in comparison to the comparative example and the reason why the nitride semiconductor gate layer 6 can be made thin in comparison to the comparative example shall now be described.
- FIG. 30 is an energy band diagram showing an energy distribution of the comparative example.
- FIG. 31 is an electric field intensity distribution diagram showing an electric field intensity distribution of the comparative example.
- GaN indicates the first nitride semiconductor layer 4
- AlGaN indicates the second nitride semiconductor layer 5
- P-GaN indicates the nitride semiconductor gate layer 6
- Metal indicates the gate electrode 8 .
- E C is the energy level of the conduction band
- E V is the energy level of the valence band
- E F is the Fermi level.
- the gate electrode 8 is put in Schottky junction with the nitride semiconductor gate layer 6 .
- a potential barrier (Schottky barrier) ⁇ B at the interface of the gate electrode 8 and the nitride semiconductor gate layer 6 influences the threshold voltage Vth.
- the threshold voltage Vth is 2[V].
- the threshold voltage Vth of a nitride semiconductor device is small in comparison to the threshold, voltage Vth of an Si semiconductor device and therefore it is important to make the threshold voltage Vth large.
- the film thickness of the nitride semiconductor gate layer 6 must be increased. Mg and Fe, which are acceptors in p-GaN, have a memory effect, and therefore as can be understood from FIG. 31 , when the film thickness of the nitride semiconductor gate layer 6 is made large, the electric field intensity in the interior of the nitride semiconductor gate layer 6 increases as a portion at the boundary with the gate electrode 8 is approached.
- a nitride semiconductor is low in the tolerable electric field intensity in comparison to an insulating film.
- the film thickness of the nitride semiconductor gate layer 6 thus cannot be increased and it is thus difficult to increase the threshold voltage Vth.
- the film thickness of the nitride semiconductor gate layer 6 is ordinarily set to not more than 100 nm.
- FIG. 32 is an energy band diagram showing an energy distribution of the present preferred embodiment.
- FIG. 33 is an electric field intensity distribution diagram showing an electric field intensity distribution of the present preferred embodiment.
- GaN indicates the first nitride semiconductor layer 4
- AlGaN indicates the second nitride semiconductor layer 5
- P-GaN indicates the nitride semiconductor gate layer 6
- SiN indicates the gate insulating film 7
- Metal indicates the gate electrode 8 .
- E C is the energy level of the conduction band
- E V is the energy level of the valence band
- E F is the Fermi level.
- the gate insulating film 7 is formed on the nitride semiconductor gate layer 6 .
- the electric field intensity distribution in the interior of the gate insulating film 7 is uniform and the insulating film 7 is made thick. Therefore, with the present preferred embodiment, the threshold voltage Vth can be made high (3[V] in FIG. 32 ) while making the film thickness of the nitride semiconductor gate layer 6 thin in comparison to the film thickness of the nitride semiconductor gate layer 6 of the comparative example (and therefore keeping small the electric field intensity at the boundary of the gate insulating film 7 with the gate electrode 8 ).
- the threshold voltage Vth can be made high by forming the gate insulating film 7 on the nitride semiconductor gate layer 6 and therefore there is no need to make the film thickness of the nitride semiconductor gate layer 6 thick to make the threshold voltage Vth high.
- the film thickness of the nitride semiconductor gate layer 6 is made thin in comparison to the comparative example. As shown in FIG.
- the electric field intensity at the portion of the nitride semiconductor gate layer 6 at the boundary with the gate insulating film 7 of the present preferred embodiment is thereby made smaller than the electric field intensity at the portion of the nitride semiconductor gate layer 6 at the boundary with the gate electrode 8 of the comparative example, and therefore, with the present preferred embodiment, time dependent dielectric breakdown (TDDB) of the nitride semiconductor gate layer 6 is unlikely to occur in comparison to the comparative example.
- TDDB time dependent dielectric breakdown
- the electric field intensity at the portion of the gate insulating film 7 at the boundary with the gate electrode 8 becomes higher than the electric field intensity at the portion of the nitride semiconductor gate layer 6 at the boundary with the gate insulating film 7 , there is no problem because the dielectric breakdown voltage of the gate insulating film 7 is higher than the dielectric breakdown voltage of the nitride semiconductor gate layer 6 .
- the nitride semiconductor gate layer 6 constituted of p type GaN is a polarizable material and therefore polarization charges appear at the front surface (c plane) thereof. If, in a process of manufacturing the nitride semiconductor gate layer 6 is exposed to atmosphere, polar organic molecules (carboxylic acids, siloxanes, etc.) become attached to the front surface so as to cancel out the polarization charges on the front surface.
- polar organic molecules carboxylic acids, siloxanes, etc.
- the material film (gate layer material film) of the nitride semiconductor gate layer 6 is formed by a CVD device
- the material film (gate electrode film) of the gate electrode is formed on the gate layer material film by a sputtering device.
- the front surface of the nitride semiconductor gate layer 6 is thus exposed to the atmosphere and organic molecules in the atmosphere become attached to the front surface.
- the magnitude of the Schottky barrier ⁇ B thereby varies and the threshold voltage Vth becomes unstable.
- the material film (gate layer material film 31 ) of the nitride semiconductor gate layer 6 is formed by the MOCVD device
- the material film (insulating material film 32 ) of the gate insulating film 7 constituted of in-situ SiN, is formed in succession on the gate layer material film 31 by the same MOCVD device. Therefore, in the process of manufacturing the nitride semiconductor device 1 , the front surface (c plane) of the nitride semiconductor gate layer 6 is not exposed to the atmosphere. Therefore, with the present preferred embodiment, organic molecules are unlikely to become attached to the front surface (c plane) of the nitride semiconductor gate layer 6 in comparison to the comparative example. Thereby, with the present preferred embodiment, the potential barrier ⁇ B at the interface of the gate electrode 8 and the gate insulating film 7 is made stable and the threshold voltage Vth is made stable in comparison to the comparative example.
- the insulating material film 32 is constituted of a material besides in-situ SiN, that is, for example, SiO 2 , the front surface of the material film (gate layer material film 31 ) of the nitride semiconductor gate layer 6 will be exposed to the atmosphere after it is formed by the MOCVD method. In this case, it suffices to form the insulating material film 32 after removing the organic molecules attached to the front surface of the gate layer material film 31 by heating the gate layer material film 31 to not less than 400° C. inside an insulating film forming device, such as a plasma CVD device, an LPCVD device, an ALD device, etc.
- an insulating film forming device such as a plasma CVD device, an LPCVD device, an ALD device, etc.
- FIG. 34 and FIG. 35 An energy distribution and an electric field intensity distribution in a case where the gate insulating film 7 is constituted of SiO 2 are shown in FIG. 34 and FIG. 35 .
- the gate insulating film (SiO 2 ) 7 has a film thickness of 30 nm and the nitride semiconductor gate layer (p-GaN) 6 has a film thickness of 50 nm.
- the second invention may be implemented in yet other modes.
- the first nitride semiconductor layer (electron transit layer) 4 is constituted of a GaN layer and the second nitride semiconductor layer (electron supply layer) 5 is constituted of an AlGaN layer was described, it suffices that the first nitride semiconductor layer 4 and the second nitride semiconductor layer 5 differ in bandgap (for example, in Al composition), and other combinations are also possible.
- the first nitride semiconductor layer 4 /second nitride semiconductor layer 5 combination GaN/AlN, AlGaN/AlN, etc., can be cited.
- silicon was taken up as an example of the material of the substrate 2 , besides this, any substrate material, such as a sapphire substrate, a GaN substrate, etc., may be applied.
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Abstract
Provided is a nitride semiconductor device 3 including a GaN electron transit layer 13, an AlGaN electron supply layer 14 in contact with the electron transit layer 13, a gate layer 15, formed selectively on the electron supply layer 14 and constituted of a nitride semiconductor composition effectively not containing an acceptor type impurity, and a gate electrode 16, formed on the gate layer 15, and satisfying the following formula (1):
Description
- The present invention relates to a nitride semiconductor device, having an HEMT (High Electron Mobility Transistor) structure, and a package thereof.
- For example, as a normally-off type transistor, Japanese Patent Publication No. 4705412 discloses a field effect transistor including a sapphire substrate, an AlN buffer layer on the sapphire substrate, an undoped GaN layer on the AlN buffer layer, an undoped AlGaN layer on the undoped GaN layer, a p type GaN layer provided on a portion of the undoped AlGaN layer, a high concentration p type GaN layer on the p type GaN layer, and a gate electrode on the high concentration p type GaN layer.
- The inventor of preferred embodiments of the present invention described and claimed in the present application conducted an extensive study and research regarding a nitride semiconductor device and a nitride semiconductor package, such as the one described above, and in doing so, discovered and first recognized new unique challenges and previously unrecognized possibilities for improvements as described in greater detail below.
- With the transistor of Japanese Patent Publication No. 4705412, when a positive voltage is applied to the gate electrode, a gate current begins to flow at a certain rising voltage and holes are implanted into channels from the p type AlGaN layer. Subsequently, electrons are induced in the channels to cancel out the implanted positive charges and an on state is thereby entered. Thus, although the transistor of
Patent Document 1 is of the normally-off type, the layers below the gate electrode contain a p type impurity and therefore whereas holes are implanted from the p type GaN gate layer when the transistor is on, a time corresponding to the carrier life is required when turning off the transistor because the implanted holes must be annihilated by recombination with the electrons, thus making the turnoff time long and making the transistor unsuitable for high speed switching operations. - An object of the present invention is to provide a normally-off type nitride semiconductor device and a package thereof, with which high speed switching can be achieved.
- Also, with the conventional structure, when the AlGaN layer (electron supply layer) is thickened to increase sheet carrier densities between source and gate and between gate and drain, a decrease in gate threshold voltage occurs and in some cases, the transistor becomes normally on. That is, the sheet carrier density outside a gate region directly below the gate electrode and the gate threshold voltage are in a tradeoff relationship.
- An object of the present invention is to provide a nitride semiconductor device and a package thereof, with which both high sheet carrier density and high gate threshold voltage can be realized at the same time.
- A nitride semiconductor device according to a preferred embodiment of the present invention includes an electron transit layer, an electron supply layer, in contact with the electron transit layer and constituted of a nitride semiconductor composition differing from that of the electron transit layer, a gate layer, formed selectively on the electron supply layer and constituted of a nitride semiconductor composition effectively not containing an acceptor type impurity, and a gate electrode, formed on the gate layer, and satisfies the following formula (1):
-
- The definitions of the respective symbols in the formula (1) are as follows.
-
- dG: thickness (cm) of the gate layer
- dB: thickness (cm) of the electron supply layer
- P: polarization (C/cm2) of the electron supply layer
- q: elementary charge (C)
- ΦB: work function (eV) of the gate electrode−electron affinity (3.6 eV) of GaN
- NDA+NA−NDD−ND: effective acceptor concentration of the electron transit layer
- εC: relative permittivity of the electron transit layer
- εB: relative permittivity of the electron supply layer
- ε0: permittivity of vacuum
- EF: energy difference (eV) between a Fermi level and a lower end of a conduction band (EC) of the electron transit layer
- With the present arrangement, the gate layer effectively does not contain an acceptor type impurity, and therefore even when the device is turned on, holes are not implanted into the electron supply layer from the gate layer. The turnoff time can thereby be shortened and high speed switching can thus be realized. Also, due to satisfying the formula (1) above, normally-off operation is enabled.
- In the nitride semiconductor device according to the preferred embodiment of the present invention, the electron transit layer and the gate layer may contain GaN and the electron supply layer may contain AlGaN.
- In the nitride semiconductor device according to the preferred embodiment of the present invention, the effective acceptor concentration NDA+NA−NDD−ND of the electron transit layer may be not less than 5×1016 cm−3, the thickness dG of the gate layer may be not less than 80 nm, an Al composition of the electron supply layer may be not more than 25%, and the thickness dB of the electron supply layer may be not more than 20 nm.
- In the nitride semiconductor device according to the preferred embodiment of the present invention, the electron transit layer may contain Mg in a region with 150 nm from an interface with the electron supply layer.
- In the nitride semiconductor device according to the preferred embodiment of the present invention, the electron transit layer may contain Mg as a deep acceptor.
- In the nitride semiconductor device according to the preferred embodiment of the present invention, the electron transit layer may contain C as a deep acceptor.
- In the nitride semiconductor device according to the preferred embodiment of the present invention, that the gate layer effectively does not contain an acceptor type impurity may signify that a concentration of the acceptor type impurity in the gate layer is less than 1×1017 cm−3.
- In the nitride semiconductor device according to the preferred embodiment of the present invention, the concentration of the acceptor type impurity in the gate layer may be less than 1×1016 cm−3.
- A nitride semiconductor device according to the preferred embodiment of the present invention includes an electron transit layer, constituted of a nitride semiconductor, an electron supply layer, constituted of AlxGa1−xN (x≦1) on the electron transit layer, a gate layer, constituted of a nitride semiconductor formed selectively on the electron supply layer, and a gate electrode formed on the gate layer, and the Al composition x of the electron supply layer is such that x≧0.3.
- With the present arrangement, the Al composition x of the electron supply layer, constituted of AlxGa1−xN (x≦1), is such that x≧0.3, and therefore both high sheet carrier density and high gate threshold voltage can be realized at the same time.
- In the nitride semiconductor device according to the preferred embodiment of the present invention, a thickness of the electron supply layer may be not more than 10 nm.
- In the nitride semiconductor device according to the preferred embodiment of the present invention, the Al composition x of the electron supply layer may be such that x=1.
- The nitride semiconductor device according to the preferred embodiment of the present invention may further include an etching stop layer, constituted of Alx′Ga1−x′N (x′≦1) on the electron supply layer, and a relationship x<x′ may hold between the electron supply layer and the etching stop layer.
- In the nitride semiconductor device according to the preferred embodiment of the present invention, the electron supply layer may include an AlN electron supply layer and the Al composition x′ of the etching stop layer may be such that 0.1≦x′≦0.2.
- In the nitride semiconductor device according to the preferred embodiment of the present invention, the electron supply layer may include an AlN electron supply layer with a thickness of not more than 2 nm, the etching stop layer may have a thickness of not more than 10 nm, and the Al composition x′ of the etching stop layer may be such that x′=0.1.
- The nitride semiconductor device according to the preferred embodiment of the present invention may include a source electrode and a drain electrode disposed to sandwich the gate electrode, and portions or entireties of the electron supply layer and the etching stop layer may be removed selectively in formation regions of the source electrode and the drain electrode.
- In the nitride semiconductor device according to the preferred embodiment of the present invention, the electron supply layer may further contain In.
- In the nitride semiconductor device according to the preferred embodiment of the present invention, the electron transit layer may contain Mg as an impurity.
- In the nitride semiconductor device according to the preferred embodiment of the present invention, a concentration of Mg in the electron transit layer may be not less than 1×1016 cm−3 and not more than 1×1017 cm−3.
- In the nitride semiconductor device according to the preferred embodiment of the present invention, the gate electrode may contain Ni, Pt, Mo, W, or TiN.
- A nitride semiconductor package according to a preferred embodiment of the present invention includes the nitride semiconductor device, a terminal frame, on which the nitride semiconductor device is installed, and a resin package, sealing the nitride semiconductor device and the terminal frame.
- The above and other elements, features, steps, characteristics and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments with reference to the attached drawings.
-
FIG. 1 is an external view of a semiconductor package that includes a nitride semiconductor device according to a preferred embodiment of the present invention. -
FIG. 2 is a schematic sectional view of the nitride semiconductor device ofFIG. 1 . -
FIG. 3 is a diagram for describing polarization states of interiors of an electron transit layer and an electron supply layer. -
FIG. 4 is a graph of a relationship of Al composition and polarization charge of the electron supply layer (AlGaN). -
FIG. 5 is an energy band diagram of the nitride semiconductor device. -
FIG. 6 is a diagram of electric field intensity distribution of the nitride semiconductor device. -
FIG. 7 is a diagram of a relationship of film thickness and sheet carrier density of the electron supply layer. -
FIG. 8 is a diagram of a relationship of the film thickness and PdB/ε0εB of the electron supply layer. -
FIG. 9 is a diagram of relationships of physical properties of the electron supply layer and dG√{square root over (NDA+NA−NDD−ND)}. -
FIG. 10A toFIG. 10C are energy band diagrams showing movements of electrons with time until the electrons begin to flow. -
FIG. 11 is an energy band diagram of a nitride semiconductor device. -
FIG. 12 is an energy band diagram (simulation results) of a nitride semiconductor device according to a reference embodiment of the present invention. -
FIG. 13 is a diagram (simulation results) of a relationship of Al composition of an electron supply layer and dG√{square root over (NDA+NA−NDD−ND)} of the nitride semiconductor device according to the reference embodiment of the present invention. -
FIG. 14 is a diagram (simulation results) of a relationship of gate voltage and current density of the nitride semiconductor device according to the reference embodiment of the present invention. -
FIG. 15 is an energy band diagram (simulation results) of a nitride semiconductor device according to a preferred embodiment of the present invention. -
FIG. 16 is a diagram (simulation results) of a relationship of Al composition of an electron supply layer and dG√{square root over (NDA+NA−NDD−ND)} of the nitride semiconductor device according to the preferred embodiment of the present invention. -
FIG. 17 is a diagram (simulation results) of a relationship of gate voltage and current density of the nitride semiconductor device according to the preferred embodiment of the present invention. -
FIG. 18 is a diagram showing relationships of the Al composition of the electron supply layer and gate threshold voltage according to sheet carrier density. -
FIG. 19 is a diagram showing relationships of the Al composition of the electron supply layer and film thickness of the electron supply layer according to sheet carrier density. -
FIG. 20 is a schematic sectional view of the nitride semiconductor device. -
FIG. 21A is a diagram of a portion of a manufacturing process of the nitride semiconductor device ofFIG. 20 . -
FIG. 21B is a diagram of a process subsequent that ofFIG. 21A . -
FIG. 21C is a diagram of a process subsequent that ofFIG. 21B . -
FIG. 21D is a diagram of a process subsequent that ofFIG. 21C . -
FIG. 21E is a diagram of a process subsequent that ofFIG. 21D . -
FIG. 21F is a diagram of a process subsequent that ofFIG. 21E . -
FIG. 22 is a diagram of GaN Fermi level dependence of the gate threshold voltage. -
FIG. 23 is a diagram of the GaN Fermi level dependence of the gate threshold voltage. -
FIG. 24 is a diagram of the GaN Fermi level dependence of the gate threshold voltage. -
FIG. 25 is a diagram of the GaN Fermi level dependence of the gate threshold voltage. -
FIG. 26 is a diagram showing the GaN Fermi level dependence of the gate threshold voltage according to acceptor concentration of an electron transit layer. -
FIG. 27 is a sectional view for describing the arrangement of a nitride semiconductor device according to a preferred embodiment of a second invention. -
FIG. 28A is a diagram of a portion of a manufacturing process of the nitride semiconductor device ofFIG. 27 . -
FIG. 28B is a diagram of a process subsequent that ofFIG. 28A . -
FIG. 28C is a diagram of a process subsequent that ofFIG. 28B . -
FIG. 28D is a diagram of a process subsequent that ofFIG. 28C . -
FIG. 28E is a diagram of a process subsequent that ofFIG. 28D . -
FIG. 28F is a diagram of a process subsequent that ofFIG. 28E . -
FIG. 28G is a diagram of a process subsequent that ofFIG. 28F . -
FIG. 29 is a sectional view of the arrangement of a nitride semiconductor device according to a comparative example. -
FIG. 30 is an energy band diagram showing an energy distribution of the comparative example. -
FIG. 31 is an electric field intensity distribution diagram showing an electric field intensity distribution of the comparative example. -
FIG. 32 is an energy band diagram showing an energy distribution of the preferred embodiment. -
FIG. 33 is an electric field intensity distribution diagram showing an electric field intensity distribution of the preferred embodiment. -
FIG. 34 is an energy band diagram showing an energy distribution in a case where a gate insulating film is constituted of SiO2. -
FIG. 35 is an electric field intensity distribution diagram showing an electric field intensity distribution in the case where the gate insulating film is constituted of SiO2. - Preferred embodiments of a first invention and a second invention shall now be described in detail with reference to the attached drawings.
- A first preferred embodiment of the first invention shall now be described in detail with reference to
FIG. 1 toFIG. 17 . -
FIG. 1 is an external view of asemiconductor package 1 that includes anitride semiconductor device 3 according to the first preferred embodiment of the present invention. - The
semiconductor package 1 includes aterminal frame 2, the nitride semiconductor device 3 (chip), and aresin package 4. - The
terminal frame 2 has the form of a plate made of a metal. Theterminal frame 2 includes a base portion 5 (island), supporting thenitride semiconductor device 3, adrain terminal 6, asource terminal 7, and agate terminal 8. Thedrain terminal 6 is formed integral to thebase portion 5. Thedrain terminal 6, thesource terminal 7, and thegate terminal 8 are electrically connected respectively bybonding wires 9 to 11 to a drain, a source, and a gate of thenitride semiconductor device 3. Thesource terminal 7 and thegate terminal 8 are disposed so as to sandwich thedrain terminal 6 at a center. - The
resin package 4 is constituted, for example, of a known molding resin, such as an epoxy resin, etc., and seals thenitride semiconductor device 3. Theresin package 4 covers thenitride semiconductor device 3 together with thebase portion 5 of theterminal frame 2 and thebonding wires 9 to 11. Portions of the threeterminals 6 to 8 are exposed from theresin package 4. -
FIG. 2 is a schematic sectional view of thenitride semiconductor device 3 ofFIG. 1 .FIG. 2 does not show a section plane at a specific position ofFIG. 1 but shows an assembly of elements, considered necessary for describing the present preferred embodiment, in a single section. - The
nitride semiconductor device 3 includes asubstrate 12, anelectron transit layer 13 on thesubstrate 12, and anelectron supply layer 14 on theelectron transit layer 13. Theelectron transit layer 13 and theelectron supply layer 14 are formed on thesubstrate 12, for example, by an epitaxial growth method. Also, a buffer layer, constituted of AlN or AlGaN, etc., may be interposed as necessary between thesubstrate 12 and theelectron transit layer 13. - The
nitride semiconductor device 3 further includes agate layer 15, formed selectively on theelectron supply layer 14, arid agate electrode 16, formed on thegate layer 15. Thegate electrode 16 faces theelectron supply layer 14 via thegate layer 15. - Also, a
surface insulating film 17 is formed on theelectron supply layer 14 so as to cover thegate electrode 16. Contact holes 18 a and 19 a, selectively exposing portions of theelectron supply layer 14, are formed in thesurface insulating film 17, and asource electrode 18 and adrain electrode 19 are put in ohmic contact with theelectron supply layer 14 via the contact holes 18 a and 19 a. Thesource electrode 18 and thedrain electrode 19 are disposed across an interval and thegate electrode 16 is disposed therebetween. Also, thesource electrode 18 is formed in a pattern that covers thegate electrode 16 via thesurface insulating film 17. - The
substrate 12 may, for example, be a conductive silicon substrate. The conductive silicon substrate may have an impurity concentration, for example, of 1×1017 cm−3 to 1×1020 cm−3 (and more specifically, approximately 1×1018 cm−3). - The
gate layer 15 may, for example, be an undoped GaN layer. Here, undoped GaN signifies GaN that effectively does not contain an acceptor type impurity and is specifically GaN with which an impurity is not intentionally introduced when forming thegate layer 15 and is more specifically GaN with a concentration of, for example, less than 1×1017 cm−3 and more preferably less than 1×1016 cm−3. This is because if the impurity concentration contained in thegate layer 15 is of approximately such level, the impurity will not function as an acceptor. The impurity concentrations may be determined by performing SIMS (secondary ion mass spectroscope) analysis on thegate layer 15. - The
electron transit layer 13 is constituted of a GaN layer, and theelectron supply layer 14 is constituted of an AlxGa1−xN layer (0<x<1). Theelectron transit layer 13 and theelectron supply layer 14 are thus constituted of nitride semiconductors that differ mutually in composition and form a heterojunction. Therefore, as shown inFIG. 3 , in addition to spontaneous polarizations Psp(GaN) and Psp(AlGaN) occurring in thelayers electron supply layer 14. Due to these polarizations, positive polarization charges 20, shown inFIG. 3 , are generated in a portion of theelectron supply layer 14 near an interface (GaN/AlGaN heterointerface) with theelectron transit layer 13. The magnitude (P) of the polarization charges 20 is expressed by the following formula (2) using the abovementioned spontaneous polarizations and the piezo polarization and, as shown inFIG. 4 , increases substantially linearly in proportion to an Al composition of the electronic supply layer 14 (AlGaN). -
P=P sp(AlGaN) +P pz(AlGaN) −P sp(GaN) (2) - At a position of the
electron transit layer 13 close to the interface with the electron supply layer 14 (for example, a position of a distance of only several Å from the interface) a large internal electric field is generated due to the polarization charges 20 and a two-dimensional electron gas 21 spreads as shown inFIG. 2 . - The
source electrode 18 and thedrain electrode 19 are ohmic electrodes, containing, for example, Ti and Al, and are electrically connected to the two-dimensional electron gas 21 via theelectron supply layer 14. - The
bonding wires 9 to 11, shown inFIG. 1 , are connected respectively to thedrain electrode 19, thesource electrode 18, and thegate electrode 16. Arear surface electrode 22 is formed on a rear surface of thesubstrate 12 and thesubstrate 12 is connected to thebase portion 5 via therear surface electrode 22. Therefore, with the present preferred embodiment, thesubstrate 12 is electrically connected to thedrain electrode 19 via thebonding wire 9 and thereby set at a drain potential. -
FIG. 5 is an energy band diagram of thenitride semiconductor device 3.FIG. 6 is a diagram of electric field intensity distribution of thenitride semiconductor device 3. - As mentioned above, with the
nitride semiconductor device 3, the positive polarization charges 20 (seeFIG. 3 ) are generated in the portion of theelectron supply layer 14 near the interface (GaN/AlGaN heterointerface) with theelectron transit layer 13. In the entire system of the junction (AlGaN/GaN junction) of theelectron supply layer 14 and theelectron transit layer 13, positive spatial charges are canceled out by negative spatial charges so that the total of the spatial charges is zero and therefore in correspondence to the positive polarization charges 20 inside theelectron supply layer 14, the two-dimensional electron gas 21, constituted of negative spatial charges, is generated in the electron transit layer 13 (GaN) that has a bandgap smaller than the electron supply layer 14 (AlGaN). The two-dimensional electron gas 21 servers as a passage (channel) for electrons between the source and the drain. Thus, when the two-dimensional electron gas 21 is present uniformly without interruption between the source and the drain, a so-called normally-on type arrangement is realized in which a current flows between the source and the drain due to a potential difference between the source and the drain even when a voltage is not applied to thegate electrode 16. - Thus, with the present preferred embodiment, the
gate layer 15, constituted of GaN, which has a smaller bandgap than the electron supply layer 14 (AlGaN), and effectively not containing an acceptor type impurity, is interposed between theelectron supply layer 14 and thegate electrode 16 to realize a normally-off type device. - The mechanism by which a normally-off arrangement is realized in the present invention is as follows. That is, in principle, the positive polarization charges 20 are canceled out by a spontaneous polarization Psp(GaN-Gate) occurring inside the
gate layer 15 and consequently, the two-dimensional electron gas 21 is eliminated selectively from a gate region Ga in which thegate electrode 16 is disposed. That is, it suffices to provide an arrangement where the spontaneous polarization (−Psp(GaN-Gate)) of thegate layer 15 is added to the formula (2) above and the magnitude P of the polarization charges 20 is as indicated by the following formula (3). -
P=P sp(AlGaN) +P pz(AlGaN) −P sp(GaN) −P sp(GaN-Gate)=0 (3) - On the other hand, the magnitude of the polarization charges 20 is dependent on the Al composition of the electron supply layer 14 (AlGaN) as shown in
FIG. 4 . It is thus necessary to set conditions of thegate layer 15 and theelectron transit layer 13 in accordance with physical properties of theelectron supply layer 14 to reliably suppress the polarization charges 20 in the gate region Ga. - Specifically, the conditions are set so that in
FIG. 5 , (P2)+(P3)−(P1)>0 is satisfied for increments/decrements (P1), (P2), and (P3) of the potential of a conduction band EC between thegate electrode 16 and apotential well 23, formed at the junction interface (GaN/AlGaN interface) of theelectron transit layer 13 and theelectron supply layer 14. This is because it will thereby become necessary to apply a positive voltage to thegate electrode 16 to lower the potential of the conduction band EC of thepotential well 23 to a position lower than a Fermi level (at the position of 0.0 eV inFIG. 5 ) and make the drain current flow. -
FIG. 5 shows an energy band when a threshold voltage Vth of 1.0 V is applied to thegate electrode 16 and by setting the gate voltage=1.0 V (gate on), the potential of the conduction band EC of thepotential well 23 becomes equivalent to the Fermi level so that electrons fall into the potential well 23 (the two-dimensional electron gas 21 begins to be generated in the gate region Ga) and the drain current begins to flow. That is, in a state where a voltage is not applied to the gate electrode 16 (gate off), the potential of the conduction band EC of thepotential well 23′ is at a position higher than the Fermi level as indicated by an alternate long and short dashed line inFIG. 5 and is in a state where the drain current does not flow. InFIG. 5 , the ordinate indicates the potential with respect to electrons. - Also, when expressed as an electric field intensity distribution, the conditions of
FIG. 5 will be as shown inFIG. 6 . A black solid line indicates the electric field intensities at the respective layers when the threshold voltage Vth of 1.0 V is applied, to thegate electrode 16. Here, an electric field intensity integration value A (hatched portion inFIG. 6 ) of the AlGaNelectron supply layer 14 and an electric field intensity integration value B (cross-hatched portion inFIG. 6 ) of theGaN gate layer 15 satisfy B>A to realize a normally-off arrangement. The internal electric field of theelectron supply layer 14 is thereby canceled out by the internal electric field of thegate layer 15 and therefore the generation of the two-dimensional electron gas 21 is suppressed. - Referring again to
FIG. 5 , (P2)+(P3)−(P1)>0 is expressed, using specific values, by the following formula (1): -
- In the formula (1), the first term, the second, term, and the third term from the left respectively correspond to the decrement (P2), the decrement (P3), and the increment (P1) of the potential of the conduction band EC. Also, the definitions of the respective symbols in the formula (1) are as follows.
-
- dG: thickness (cm) of the
gate layer 15 - dB: thickness (cm) of the
electron supply layer 14 - P: polarization (C/cm2) of the
electron supply layer 14 - q: elementary charge (C)
- ΦB: work function (eV) of the
gate electrode 16−electron affinity (3.6 eV) of GaN - NDA+NA−NDD−ND: effective acceptor concentration of the
electron transit layer 13 - εC: relative permittivity of the
electron transit layer 13 - εB: relative permittivity of the
electron supply layer 14 - ε0: permittivity of vacuum
- EF: energy difference (eV) between the Fermi level and a lower end of conduction band (EC) of the
electron transit layer 13
- dG: thickness (cm) of the
- To satisfy the formula (1) above, it is preferable for dBP/ε0εB, corresponding to the increment (P1) of the potential of the conduction band EC, to be made as small as possible. Making dB and P, which are variables of dBP/ε0εB, small is thus considered.
- First, in regard to the thickness dB of the
electron supply layer 14, reference toFIG. 7 shows that regardless of the Al composition (x=0.1 to 0.9) of AlGaN, a sheet carrier density of the two-dimensional electron gas 21 saturates at approximately dB=20 nm even when the thickness dB is increased. Therefore, as far as the sheet carrier density is concerned, it suffices for the thickness dB to be 20 nm at the most. Oppositely, as shown inFIG. 8 , dBP/ε0εB, which is the increment (P1) of the potential of the conduction band EC, increases proportionally with an increase in the thickness dB of theelectron supply layer 14 and therefore in regard to dBP/ε0εB, it is preferable for the thickness dB to be as small as possible. Therefore, although when the thickness dB exceeds 20 nm, a satisfactory sheet carrier density can be achieved, the increment (P1) of the potential of the conduction band EC becomes large, and it is thus preferable for the thickness dB of theelectron supply layer 14 to be not more than 20 nm and not more than 30 nm at the most. - On the other hand, in regard to mobility of the two-dimensional electron gas 21 (2DEG mobility), there is no tradeoff even when it is high and therefore the higher it is, the more preferable, and an example of a condition with which the mobility of the two-
dimensional electron gas 21 is maximized is a sheet carrier density in a vicinity of 8.0×1012 (cm−2), as indicated in the followingDocument 1. - Document 1: Journal of Applied Physics, Vol. 87, No. 8 ‘Scattering mechanisms limiting two-dimensional electron gas mobility in Al0.25Ga0.75N modulation-doped field-effect transistors’
- Even judging from the standpoint of withstand voltage, it is preferable for the sheet carrier density to be in a vicinity of 8.0×1012 (cm−2) or less. Thus, in
FIG. 7 , when the thickness dB=20 nm, the sheet carrier density is approximately 8.0×1012 (cm−2) if the Al composition is approximately 0.25, and it is therefore preferable for the Al composition to be not more than 0.25 (not more than 25%). In regard to this point, according toFIG. 7 , even if the Al composition is large (for example, even if it is 0.9), the sheet carrier density can be made 8.0×1012 (cm−2) as long as the film thickness dB of the AlGaNelectron supply layer 14 is small. In this case, the increase in dBP/ε0εB inFIG. 8 is also small because the film thickness is small, and both high sheet carrier density and high gate threshold voltage can be realized at the same time. On the other hand, if the Al composition of the AlGaNelectron supply layer 14 is large and the AlGaNelectron supply layer 14 is thin, AlGaN itself is readily oxidized, for example, when performing etching of theGaN gate layer 15 on the AlGaNelectron supply layer 14 using a plasma of a mixed gas of Cl2 and O2. - To summarize the above, the ranges of physical properties of the
electron supply layer 14, constituted of AlGaN, are a thickness dB of not more than 30 nm (more preferably not more than 20 nm and not less than 3 nm) and an Al composition of not more than 25% . If the thickness dB of theelectron supply layer 14 is not less than 3 nm, the occurrence of direct tunneling due to theelectron supply layer 14 being too thin can be prevented and a gate leak current can be reduced. Theelectron supply layer 14 may be an undoped AlGaN layer. Here, undoped. AlGaN signifies AlGaN that effectively does not contain an acceptor type impurity and is specifically AlGaN with which an impurity is not intentionally introduced when forming theelectron supply layer 14. - With the physical property conditions of the
electron supply layer 14 being set as described above, preferable conditions regarding the GaNelectron transit layer 13 and theGaN gate layer 15 shall now be examined based on the physical property conditions described above. - First,
FIG. 9 is a diagram of relationships of physical properties of theelectron supply layer 14 and dG√{square root over (NDA+NA−NDD−ND)}, which is a portion of the decrement (P2) of the potential of the conduction band EC, and shows preferable ranges of dG√{square root over (NDA+NA−NDD−ND)} for a plurality of combinations of the thickness dB and the Al composition. - Referring to
FIG. 9 , with respect to each of the four graphs (straight lines), the upper side is a range in which a normally-off arrangement can be realized and the lower side is a range in which a normally-on arrangement is realized. Therefore, for each thickness dB and Al composition of theelectron supply layer 14, the value of dG√{square root over (NDA+NA−NDD−ND)} is set as suited so as to be included in the range higher than the corresponding graph inFIG. 9 . - Here, a method for determining (NDA+NA−NDD−ND) shall be described.
- First, in regard to the energy band structure of the
electron transit layer 13, a shallow donor level ED, a deep donor level EDD, a shallow acceptor level EA, and a deep acceptor level EDA are formed. - The shallow donor level ED is, for example, an energy level at a position separated by not more than 0.025 eV from the lower end (bottom) energy level EC of the conduction band of the
electron transit layer 13 and may be referred to simply as the “donor level ED” as long as distinction can be made with respect to the deep donor level EDD. Ordinarily, donor electrons doped at this position are excited to the conduction band and are free electrons even at room temperature (thermal energy kT=approximately 0.025 eV). As an impurity forming the shallow donor level ED, for example, at least one type selected from the group consisting of Si and O can be cited. These may be incorporated into the film during epitaxial growth of theelectron transit layer 13 or may be doped intentionally. For example, oxygen (O) maybe incorporated from a raw material gas or a carrier gas. - On the other hand, the deep donor level EDD is, for example, an energy level at a position separated by not less than 0.025 eV from the lower end (bottom) energy level EC of the conduction band of the
electron transit layer 13. That is, the deep donor level EDD is formed by doping of a donor, with which an ionization energy necessary for excitation is greater than the thermal energy at room temperature. Therefore, ordinarily, the donor electrons doped at this position are not excited to the conduction band and are in a state of being captured by the donor at room temperature. The deep donor level EDD may, for example, be that due to a crystal defect occurring spontaneously in GaN during epitaxial growth of theelectron transit layer 13. - The shallow acceptor level EA is, for example, an energy level at a position separated by not more than 0.025 eV from an upper end (top) energy level EV of valence electrons of the
electron transit layer 13 and may be referred to simply as the “acceptor level EA” as long as distinction can be made with respect to the deep acceptor level EDA. Ordinarily, acceptor holes doped at this position are excited to a valence band and are free holes even at room temperature (thermal energy kT=approximately 0.025 eV). - On the other hand, the deep acceptor level EDA is, for example, an energy level at a position separated, by not less than 0.025 eV from the upper end (top) energy level EV of the valence electrons of the
electron transit layer 13. That is, the deep acceptor level EDA is formed by doping of an acceptor, with which an ionization energy necessary for excitation is greater than the thermal energy at room temperature. Therefore ordinarily, the acceptor holes doped at this position are not excited to the valence band and are in a state of being captured by the acceptor at room temperature. - As an impurity doped into the
electron transit layer 13, constituted of GaN, to form the deep acceptor level EDA, for example, at least one type selected from the group consisting of C, Be, Cd, Ca, Cu, Ag, Au, Sr, Ba, Li, Na, K, Sc, Zr, Fe, Co, Ni, Mg, Ar, and He can be cited. - Among these, although C and Mg can be cited mainly, carbon (C) functions as a deep acceptor when incorporated in a nitrogen site inside GaN and functions as a shallow donor when incorporated in a Ga site, and therefore, to increase (NDA+NA−NDD−ND) reliably, it is preferable to use Mg, and Mg is preferably contained in a region in the
electron transit layer 13 that is within 150 nm from the interface with theelectron supply layer 14. For example, inFIG. 5 andFIG. 11 (to be described below), a region of the GaNelectron transit layer 13 in which the energy band is curved is approximately 150 nm from the AlGaNelectron supply layer 14/GaNelectron transit layer 13 interface. That is, this is because the region within 150 nm from the interface contributes to the threshold voltage and the concentrations and types of impurities in this region are important. - However, C may also be used as the deep acceptor. When C is used for the deep acceptor level, it is known to form, for example, a level of 0.9 eV from the upper end (top) energy level EV of the valence band of the
electron transit layer 13. On the other hand, when Mg is used, it is known to form a level of 0.1 to 0.2 eV from EV. Although this is a position separated by not less than 0.025 eV from the upper end (top) energy level EV of the valence band of theelectron transit layer 13 as mentioned above and Mg can thus be said to be a deep acceptor, when the Fermi level is fixed at this level of Mg, a probability of presence of a hole at EV at room temperature will be 0.003 to 0.02. In other words, this means that at room temperature, a hole is generated at EV at a proportion of one in 100 to 1000. If a hole that can move freely is thereby made present inside theelectron transit layer 13, a problem occurs in that a p-n junction is formed and thus a parasitic capacitance is formed in theelectron transit layer 13. Further, leak current is increased by the formed hole acting as a carrier. By the above, an impurity, with which the deep acceptor level will be at a position separated from EV by more than 0.2 eV and, for example, not less than 0.3 eV, is preferable, and C satisfies this condition. - When C is used as the deep acceptor, EF in (1) above is such that EF=2.5 eV because the bandgap of GaN is 3.6 eV, and when Mg is used, EF=3.2 eV.
- Concentrations of the impurities (dopants) forming the shallow donor level ED, the deep donor level EDD, the shallow acceptor level EA, and the deep acceptor level EDA described above shall be referred to respectively as a shallow donor concentration ND, a deep donor concentration NDD, a shallow acceptor concentration NA, and a deep acceptor concentration NDA. For example, if as the impurity forming the deep acceptor level EDA, only C (carbon) is doped in the
electron transit layer 13 at a concentration of 0.5×1016 cm−3, this carbon concentration is defined as the deep acceptor concentration NDA. The concentrations ND, NDD, NA, and NDA may be measured, for example, by SIMS (Secondary Ion Mass Spectrometry). - A more specific measurement method can be described with reference to
FIG. 10A toFIG. 10C . First, as shown inFIG. 10A , when a voltage is not applied across both electrodes (unbiased state), the acceptors and the deep acceptors capture electrons emitted by the donors and the deep donors. In this state, positive charges, due to the donors and the deep donors that emitted the electrons, and negative charges, due to the acceptors and the deep acceptors that captured the electrons, are equal in number and therefore the GaN layer is electrically neutral as a whole. - Next, as a voltage is applied as shown in
FIG. 10B , the positively biased side becomes negatively charged due to the deep acceptors capturing electrons from the valence band (EV). An electric flux generated by the voltage application is canceled out by the negatively charged region and therefore electron implantation into the conduction band EC of the electron transit layer does not occur and the current that flows is extremely minute. - Then, when a voltage Vth of not less than a certain level is applied as shown in
FIG. 10C , electron capture by the deep acceptors occurs in all regions. Electron capture does not occur even when a higher voltage is applied and because the electric flux cannot be canceled out completely, electrons become implanted into the conduction band EC from the source electrode and a current begins to flow. A formula that includes the voltage Vth in this state is derived from the Poisson formula as NDA+NA−ND−NDD=2 Vthε0εC/qW2 (where W is the thickness of the GaN electron transit layer) and consequently, Vth=q(NDA+NA−ND−NDD)·W2/2ε0εC is obtained. That is, (NDA+NA−ND−NDD) can be determined based on this formula. - The preferable ranges of dG√{square root over (NDA+NA−NDD−ND)} for the respective thicknesses dB and Al compositions of the
electron supply layer 14 are as shown inFIG. 9 , and preferable ranges of dG and (NDA+NA−NDD−ND) that constitute dG√{square root over (NDA+NA−NDD−ND)} are, for example, as indicated below. The preferable ranges indicated below differ according to the respective thicknesses dB and Al compositions of theelectron supply layer 14 and may therefore be set as suited in accordance with the respective thicknesses dB and Al compositions of theelectron supply layer 14. - First, the thickness dG of the
gate layer 15 is preferably, for example, 50 nm to 100 nm. On the other hand, (NDA+NA−NDD−ND) is not less than 5×1016 cm−3. This preferable range of (NDA+NA−NDD−ND) can be explained with reference toFIG 11 . -
FIG. 11 is an energy band diagram of a turn-on state when theelectron supply layer 14 has an Al composition of 20% and a thickness dB of 15 nm, the thickness dG of thegate layer 15 is 80 nm, ΦB=1.2 eV, and (NDA+NA−NDD−ND) is 5×1016 cm−3. The threshold voltage in this state is 0.3 eV and a normally-off operation is narrowly realized. From this, it can be understood that for a normally-off operation, (NDA+NA−NDD−ND) of at least 5×1016 cm−3 is necessary. - Also, a preferable range of ΦB (work function (eV) of the
gate electrode 16−electron affinity (3.6 eV) of GaN) in the formula (1) above is 0.7 eV to 1.4 eV. This range may be realized using, for example, Ni (ΦM=4.8 eV), Pt (ΦM=5.0 eV), Mo (ΦM=4.3 eV), W (ΦM=4.6 eV), or TiN (ΦM=4.6 eV) as thegate electrode 16. On the other hand, although Al (ΦM=4.0 eV) may also be used as thegate electrode 16, Al is low in work function compared to Mo, etc., mentioned above and reacts readily with a semiconductor or an insulating film and it is therefore preferable to use Mo or TiN which are rather high in work function. - Next, effects of the present invention were examined by simulation. The results are shown in
FIG. 12 toFIG. 17 . -
- (1) Reference Embodiment (
FIG. 12 toFIG. 14 ) - GaN (electron transit layer 13): NDA+NA−NDD−ND=2.0×1016 cm−3
- AlGaN (electron supply layer 14):
Al composition 25%,film thickness 15 nm - GaN (gate layer 15): non-doped, film thickness 60 nm
- gate electrode: work function ΦM=4.6 eV
- (2) Preferred Embodiment (
FIG. 15 toFIG. 17 ) - GaN (electron transit layer 13): NDA+NA−NDD−ND=1.0×1017 cm−3
- AlGaN (electron supply layer 14):
Al composition 25%,film thickness 15 nm - GaN (gate layer 15): non-doped,
film thickness 100 nm - gate electrode: work function ΦM=4.6 eV
- As shown in
FIG. 12 , with the reference embodiment, application of a negative voltage to thegate electrode 16 raises the potential of the conduction band EC of thepotential well 23 to a position higher than the Fermi level and the off state of the device is maintained thereby. The arrangement is thus of the normally-on type, with which a current flows between the source and the drain in a state where a voltage is not applied to thegate electrode 16. When, for the present reference embodiment, the value of dG√{square root over (NDA+NA−NDD−ND)} is plotted on a graph as inFIG. 9 above, it will be at the position indicated by “∘” inFIG. 13 . Also, from the result shown inFIG. 14 , it was confirmed that a current of approximately 3.0×10−2 (A/mm) flows when the gate voltage Vg=0 V. - On the other hand, as shown in
FIG. 15 , with the present preferred embodiment, application of a positive voltage to thegate electrode 16 lowers the potential of the conduction band EC of thepotential well 23 to a position lower than the Fermi level and the device thereby transitions to the on state. The arrangement is thus of the normally-off type, with which a current does not flow between the source and the drain in a state where a voltage is not applied to thegate electrode 16. When, for the present preferred embodiment, the value of dG√{square root over (NDA+NA−NDD−ND)} is plotted on a graph as inFIG. 9 above, it will be at the position indicated by “∘”0 inFIG. 16 . Also, from the result shown inFIG. 17 , it was confirmed that a current does not flow when the gate voltage Vg=0 V. - Although the first preferred embodiment of the first invention has been described above, the first invention may be implemented in other modes.
- For example, although with the first preferred embodiment described above, an example where the
electron transit layer 13 is constituted of GaN and theelectron supply layer 14 is constituted of AlGaN was described, it suffices that theelectron transit layer 13 and theelectron supply layer 14 differ in Al composition and other combinations are also possible. The electron supply layer/electron transit layer combination may be any of AlGaN layer/GaN layer, AlGaN layer/AlGaN layer (with the layers differing in Al composition), AlInN layer/AlGaN layer, AlInN layer/GaN layer, AlN layer/GaN layer, and AlN layer/AlGaN layer. To generalize further, the electron supply layer contains Al and N in its composition. The electron transit layer contains Ga and N in its composition and differs in Al composition from the electron supply layer. By the electron supply layer and the electron transit layer differing in Al composition, a lattice mismatch arises between the two and carriers due to polarization are thereby made to contribute to the forming of a two-dimensional electron gas. - Also, although with the first preferred embodiment described above, silicon was taken up as an example of the material of the
substrate 12, besides this, any substrate material, such as a sapphire substrate, a GaN substrate, etc., may be applied. - A second preferred embodiment and a third preferred embodiment of the first invention shall now be described in detail with reference to
FIG. 1 toFIG. 8 ,FIG. 10 , andFIG. 18 toFIG. 24 . - An external view of a
semiconductor package 1 that includes anitride semiconductor device 3 according to the second preferred embodiment is the same as the external view of thesemiconductor package 1 that includes thenitride semiconductor device 3 according to the first preferred embodiment of the first invention described usingFIG. 1 . - Referring to
FIG. 1 , thesemiconductor package 1, which includes thenitride semiconductor device 3 according to the second preferred embodiment, includes aterminal frame 2, the nitride semiconductor device 3 (chip), and aresin package 4. - The
terminal frame 2 has the form of a plate made of a metal. Theterminal frame 2 includes a base portion 5 (island), supporting thenitride semiconductor device 3, adrain terminal 6, asource terminal 7, and agate terminal 8. Thedrain terminal 6 is formed integral to thebase portion 5. Thedrain terminal 6, thesource terminal 7, and thegate terminal 8 are electrically connected respectively bybonding wires 9 to 11 to a drain, a source, and a gate of thenitride semiconductor device 3. Thesource terminal 7 and thegate terminal 8 are disposed so as to sandwich thedrain terminal 6 at a center. - The
resin package 4 is constituted, for example, of a known molding resin, such as an epoxy resin, etc., and seals thenitride semiconductor device 3. Theresin package 4 covers thenitride semiconductor device 3 together with thebase portion 5 of theterminal frame 2 and thebonding wires 9 to 11. Portions of the threeterminals 6 to 8 are exposed from theresin package 4. - A schematic sectional view of the
nitride semiconductor device 3 according to the second preferred embodiment is the same as the schematic sectional view of thenitride semiconductor device 3 according to the first preferred embodiment described usingFIG. 2 . - Referring to
FIG. 2 , thenitride semiconductor device 3 according to the second preferred embodiment includes asubstrate 12, and anelectron supply layer 14 on theelectron transit layer 13. Theelectron transit layer 13 and theelectron supply layer 14 are formed on thesubstrate 12, for example, by an epitaxial growth method. Also, a buffer layer, constituted of AlN or AlGaN, etc., may be interposed as necessary between thesubstrate 12 and theelectron transit layer 13. - The
nitride semiconductor device 3 further includes agate layer 15, formed selectively on theelectron supply layer 14, and agate electrode 16, formed on thegate layer 15. Thegate electrode 16 faces theelectron supply layer 14 via thegate layer 15. - Also, a
surface insulating film 17 is formed on theelectron supply layer 14 so as to cover thegate electrode 16. - In
FIG. 2 , contact holes 18 a and 19 a, selectively exposing portions of theelectron supply layer 14, are formed in thesurface insulating film 17, and asource electrode 18 and adrain electrode 19 are put in ohmic contact with theelectron supply layer 14 via the contact holes 18 a and 19 a. - The
source electrode 18 and thedrain electrode 19 are disposed across an interval and thegate electrode 16 is disposed therebetween. Also, thesource electrode 18 is formed in a pattern that covers thegate electrode 16 via thesurface insulating film 17. - The
substrate 12 may, for example, be a conductive silicon substrate. The conductive silicon substrate may have an impurity concentration, for example, of 1×1017 cm−3 to 1×1020 cm−3 (and more specifically, approximately 1×1018 cm−3). - The
gate layer 15 may, for example, be an undoped GaN layer or may be a GaN layer containing an acceptor type level. Here, undoped GaN signifies GaN that effectively does not contain an acceptor type impurity. Specifically, it is GaN with which an impurity is not intentionally introduced when forming thegate layer 15 and is more specifically GaN with a concentration of, for example, less than 1×1017 cm−3 and more preferably less than 1×1016 cm−3. This is because if the impurity concentration contained in thegate layer 15 is of approximately such level, the impurity will not function as an acceptor. The impurity concentrations may be determined by performing SIMS (secondary ion mass spectroscope) analysis on thegate layer 15. Also, the GaN layer that includes the acceptor type level may contain, for example, Mg or C as the acceptor or may have a hole defect formed therein. - The
electron transit layer 13 is constituted of a GaN layer, and theelectron supply layer 14 is constituted of an AlxGa1−xN layer (0<x<1) and may contain In as necessary. Theelectron transit layer 13 and theelectron supply layer 14 are thus constituted of nitride semiconductors that differ mutually in composition and form a heterojunction. Therefore, as shown inFIG. 3 , in addition to spontaneous polarizations Psp(GaN) and Psp(AlGaN) occurring in thelayers electron supply layer 14. Due to these polarizations, positive polarization charges 20, shown inFIG. 3 , are generated in a portion of theelectron supply layer 14 near an interface (GaN/AlGaN heterointerface) with theelectron transit layer 13. The magnitude (P) of the polarization charges 20 is expressed by the following formula (2) using the spontaneous polarizations and the piezo polarization and, as shown inFIG. 4 , increases substantially linearly in proportion to the Al composition of the electronic supply layer 14 (AlGaN). -
P=P sp(AlGaN) +P pz(AlGaN) −P sp(GaN) (2) - At a position of the
electron transit layer 13 close to the interface with the electron supply layer 14 (for example, a position of a distance of only several Å from the interface) a large internal electric field is generated due to the polarization charges 20 and a two-dimensional electron gas 21 spreads as shown inFIG. 2 . - The
source electrode 18 and thedrain electrode 19 are ohmic electrodes, containing, for example, Ti and Al, and are electrically connected to the two-dimensional electron gas 21. - The
bonding wires 9 to 11, shown inFIG. 1 , are connected respectively to thedrain electrode 19, thesource electrode 18, and thegate electrode 16. Arear surface electrode 22 is formed on a rear surface of thesubstrate 12 and thesubstrate 12 is connected to thebase portion 5 via therear surface electrode 22. Therefore, with the present preferred embodiment, thesubstrate 12 is electrically connected to thedrain electrode 19 via thebonding wire 9 and thereby set at the drain potential. -
FIG. 5 is an energy band diagram of thenitride semiconductor device 3.FIG. 6 is a diagram of the electric field intensity distribution of thenitride semiconductor device 3. - As mentioned above, with the
nitride semiconductor device 3, the positive polarization charges 20 (seeFIG. 3 ) are generated in the portion of theelectron supply layer 14 near the interface (GaN/AlGaN heterointerface) with theelectron transit layer 13. In the entire system of the junction (AlGaN/GaN junction) of theelectron supply layer 14 and theelectron transit layer 13, positive spatial charges are canceled out by negative spatial charges so that the total of the spatial charges is zero and therefore in correspondence to the positive polarization charges 20 inside theelectron supply layer 14, the two-dimensional electron gas 21, constituted of negative spatial charges, is generated in the electron transit layer 13 (GaN) that has a bandgap smaller than the electron supply layer 14 (AlGaN). The two-dimensional electron gas 21 serves as a passage (channel) for electrons between the source and the drain. Thus, when the two-dimensional electron gas 21 is present uniformly without interruption between the source and the drain, a so-called normally-on type arrangement is realized in which a current flows between the source and the drain due to the potential difference between the source and the drain even when a voltage is not applied to thegate electrode 16. - Thus, with the present preferred embodiment, the
gate layer 15, constituted of GaN, which has a smaller bandgap than the electron supply layer 14 (AlGaN), and effectively not containing an acceptor type impurity, is interposed between theelectron supply layer 14 and thegate electrode 16 to realize a normally-off type device. - The mechanism by which a normally-off arrangement is realized in the present invention is as follows. That is, in principle, the positive polarization charges 20 are canceled out by a spontaneous polarization Psp(GaN-Gate) occurring inside the
gate layer 15 and consequently, the two-dimensional electron gas 21 disappears selectively from a gate region Ga in which thegate electrode 16 is disposed. That, is, it suffices to provide an arrangement where the spontaneous polarization (−Psp(GaN-Gate)) of thegate layer 15 is added to the formula (2) above and the magnitude P of the polarization charges 20 is as indicated by the following formula (3). -
P=P sp(AlGaN) +P pz(AlGaN) −P sp(GaN) −P sp(GaN-Gate)=0 (3) - On the other hand, the magnitude of the polarization charges 20 is dependent on the Al composition of the electron supply layer 14 (AlGaN) as shown in
FIG. 4 . - In the present preferred embodiment, it is necessary to set the conditions of the
gate layer 15 and theelectron transit layer 13 in accordance with the physical properties of theelectron supply layer 14 to reliably suppress the polarization charges 20 in the gate region Ga. Specifically, the conditions are set so that inFIG. 5 , (P2)+(P3)−(P1)>0 is satisfied for increments/decrements (P1), (P2), and (P3) of the potential of a conduction band EC between thegate electrode 16 and apotential well 23, formed at the junction interface (GaN/AlGaN interface) of the electron because it will thereby become necessary to apply a positive voltage to thegate electrode 16 to lower the potential of the conduction band EC of thepotential well 23 to a position lower than the Fermi level (at the position of 0.0 eV inFIG. 5 ) and make the drain current flow. -
FIG. 5 shows the energy band when a threshold voltage Vth of 1.0 V is applied to thegate electrode 16 and by setting the gate voltage=1.0 V (gate on), the potential of the conduction band EC of thepotential well 23 becomes equivalent to the Fermi level so that electrons fall into the potential well 23 (the two-dimensional electron gas 21 begins to be generated in the gate region Ga) and the drain current begins to flow. That is, in a state where a voltage is not applied to the gate electrode 16 (gate off), the potential of the conduction band EC of thepotential well 23′ is at the position higher than the Fermi level as indicated by the alternate long and short dashed line inFIG. 5 and is in a state where the drain current does not flow. InFIG. 5 , the ordinate indicates the potential with respect to electrons. - Also, when expressed as an electric field intensity distribution, the conditions of
FIG. 5 will be as shown inFIG. 6 . The black solid line indicates the electric field intensities at the respective layers when the threshold voltage Vth of 1.0 V is applied to thegate electrode 16. Here, an electric field intensity integration value A (hatched portion inFIG. 6 ) of the AlGaNelectron supply layer 14 and an electric field intensity integration value B (cross-hatched portion inFIG. 6 ) of theGaN gate layer 14 satisfy B>A to realize a normally-off arrangement. The internal electric field of theelectron supply layer 14 is thereby canceled out by the internal electric field of thegate layer 15 and therefore the generation of the two-dimensional electron gas 21 is suppressed. - Referring again to
FIG. 5 , (P2)+(P3)−(P1)>0 is expressed, using specific values, by the following formula (1): -
- In the formula (1), the first term, the second term, and the third term from the left respectively correspond to the decrement (P2), the decrement (P3), and the increment (P1) of the potential of the conduction band EC. Also, the definitions of the respective symbols in the formula (1) are as follows.
-
- dG: thickness (cm) of the
gate layer 15 - dB: thickness (cm) of the
electron supply layer 14 - P: polarization (C/cm2) of the
electron supply layer 14 - q: elementary charge (C)
- ΦB: work function (eV) of the
gate electrode 16−electron affinity (3.6 eV) of GaN - NDA+NA−NDD−ND: effective acceptor concentration of the
electron transit layer 13 - εC: relative permittivity of the
electron transit layer 13 - εB: relative permittivity of the
electron supply layer 14 - ε0: permittivity of vacuum
- EF: energy difference (eV) between the Fermi level and a lower end of conduction band (EC) of the
electron transit layer 13 - (NDA+NA−NDD−ND) of dG√{square root over (NDA+NA−NDD−ND)}, which, in the formula (1), is a portion of the decrement (P2) of the potential of the conduction band EC, may be determined as follows.
- dG: thickness (cm) of the
- First, in regard to the energy band structure of the
electron transit layer 13, a shallow donor level ED, a deep donor level EDD, a shallow acceptor level EA, and a deep acceptor level EDA are formed. - The shallow donor level ED is, for example, an energy level at a position separated by not more than 0.025 eV from the lower end (bottom) energy level EC of the conduction band of the
electron transit layer 13 and may be referred to simply as the “donor level ED” as long as distinction can be made with respect to the deep donor level EDD. Ordinarily, the donor electrons doped at this position are excited to the conduction band and are free electrons even at room temperature (thermal energy kT=approximately 0.025 eV). As an impurity forming the shallow donor level ED, for example, at least one type selected from the group consisting of Si and O can be cited. These may be incorporated into the film during epitaxial growth of theelectron transit layer 13 or may be doped intentionally. For example, oxygen (O) maybe incorporated from a raw material gas or a carrier gas. - On the other hand, the deep donor level EDD is, for example, an energy level at a position separated by not less than 0.025 eV from the lower end (bottom) energy level EC of the conduction band of the
electron transit layer 13. That is, the deep donor level EDD is formed by doping of a donor, with which an ionization energy necessary for excitation is greater than the thermal energy at room temperature. Therefore, ordinarily, the donor electrons doped at this position are not excited to the conduction band and are in a state of being captured by the donor at room temperature. The deep donor level EDD may, for example, be that due to a crystal defect occurring spontaneously in GaN during epitaxial growth of theelectron transit layer 13. - The shallow acceptor level EA is, for example, an energy level at a position separated by not more than 0.025 eV from an upper end (top) energy level EV of valence electrons of the
electron transit layer 13 and may be referred to simply as the “acceptor level EA” as long as distinction can be made with respect to the deep acceptor level EDA. Ordinarily, the acceptor holes doped at this position are excited to a valence band and are free holes even at room temperature (thermal energy kT=approximately 0.025 eV). - On the other hand, the deep acceptor level EDA is, for example, an energy level at a position separated by not less than 0.025 eV from the upper end (top) energy level EV of the valence electrons of the
electron transit layer 13. That is, the deep acceptor level EDA is formed by doping of an acceptor, with which an ionization energy necessary for excitation is greater than the thermal energy at room temperature. Therefore ordinarily, the acceptor holes doped at this position are not excited to the valence band and are in a state of being captured by the acceptor at room temperature. - As an impurity doped into the
electron transit layer 13, constituted of GaN, to form the deep acceptor level EDA, for example, at least one type selected from the group consisting of C, Be, Cd, Ca, Cu, Ag, Au, Sr, Ba, Li, Na, K, Sc, Zr, Fe, Co, Ni, Mg, Ar, and He can be cited. - Among these, although C and Mg can be cited mainly, carbon (C) functions as a deep acceptor when incorporated, in a nitrogen site inside GaN and functions as a shallow donor when incorporated in a Ga site, and therefore, to increase (NDA+NA−NDD−ND) reliably, it is preferable to use Mg. Also, a region of the
electron transit layer 13 in which the energy band is curved depends on the type (Fermi level) of impurity and (NDA+NA−NDD−ND). Also, the region of theelectron transit layer 13 in which Mg is contained depends on the Mg concentration. For example, inFIG. 25 (to be described below), in which the impurity is Mg and (NDA+NA−NDD−ND) is 1×1017 cm−3, the region of the GaNelectron transit layer 13 in which the energy band is curved, is approximately 150 nm from the AlGaNelectron supply layer 14/GaNelectron transit layer 13 interface. On the other hand, inFIG. 23 (to be described below), in which the impurity is Mg and (NDA+NA−NDD−ND) is 4×1016 cm−3, the region in which the energy band is curved is approximately 250 nm from the AlGaNelectron supply layer 14/GaNelectron transit layer 13 interface. That is, this is because the region within the abovementioned upper limit from the AlGaNelectron supply layer 14/GaNelectron transit layer 13 interface contributes to the threshold voltage and the concentrations and types of impurities in this region are important. - However, C may also be used as the deep acceptor. When C is used for the deep acceptor level, it is known to form, for example, a level of 0.9 eV from the upper end (top) energy level EV of the valence band of the
electron transit layer 13. On the other hand, when Mg is used, it is known to form a level of 0.1 to 0.2 eV from EV. Although this is a position separated by not less than 0.025 eV from the upper end (top) energy level EV of the valence band of theelectron transit layer 13 as mentioned above and Mg can thus be said to be a deep acceptor, when the Fermi level is fixed at this level of Mg, a probability of presence of a hole at EV at room temperature will be 0.003 to 0.02. In other words, this means that at room temperature, a hole is generated at EV at a proportion of one in 100 to 1000. If a hole that can move freely is thereby made present inside theelectron transit layer 13, a problem occurs in that a p-n junction is formed and thus a parasitic capacitance is formed in theelectron transit layer 13. Further, the leak current is increased by the formed hole acting as a carrier. By the above, an impurity, with which the deep acceptor level will be at a position separated from EV by more than 0.2 eV and, for example, not less than 0.3 eV, is preferable, and C satisfies this condition. - When C is used as the deep acceptor, EF in (1) above is such that EF=2.5 eV because the bandgap of GaN is 3.6 eV, and when Mg is used, EF=3.2 eV.
- Concentrations of the impurities (dopants) forming the shallow donor level ED, the deep donor level EDD, the shallow acceptor level EA, and the deep acceptor level EDA described above shall be referred to respectively as a shallow donor concentration ND, a deep donor concentration NDD, a shallow acceptor concentration NA, and a deep acceptor concentration NDA. For example, if as the impurity forming the deep acceptor level EDA, only C (carbon) is doped in the
electron transit layer 13 at a concentration of 0.5×1016 cm−3, this carbon concentration is defined as the deep acceptor concentration NDA. The concentrations ND, NDD, NA, and NDA may be measured, for example, by SIMS (Secondary Ion Mass Spectrometry). - A more specific measurement method can be described with reference to
FIG. 10A toFIG. 10C . First, as shown inFIG. 10A , when a voltage is not applied across both electrodes (unbiased state), the acceptors and the deep acceptors capture electrons emitted by the donors and the deep donors. In this state, positive charges, due to the donors and the deep donors that emitted the electrons, and negative charges, due to the acceptors and the deep acceptors that captured the electrons, are equal in number and therefore the GaN layer is electrically neutral as a whole. - Next, as a voltage is applied as shown in
FIG. 10B , the positively biased side becomes negatively charged due to the deep acceptors capturing electrons from the valence band (EV). An electric flux generated by the voltage application is canceled out by the negatively charged region and therefore electron implantation into the conduction band EC of the electron transit layer does not occur and the current that flows is extremely minute. - Then, when a voltage Vth of not less than a certain level is applied as shown in
FIG. 10C , electron capture by the deep acceptors occurs in all regions. Electron capture does not occur even when a higher voltage is applied and because the electric flux cannot be canceled out completely, electrons become implanted into the conduction band EC from the source electrode and a current begins to flow. The formula that includes the voltage Vth in this state is derived from the Poisson formula as NDA+NA−NDD−ND=2 Vthε0εC/qW2 (where W is the thickness of the GaN electron transit layer) and consequently, Vth=q(NDA+NA−NDD−ND)·W2/2ε0εC is obtained. That is, (NDA+NA−NDD−ND) can be determined based on this formula. - Preferable ranges of dG and (NDA+NA−NDD−ND) that constitute dG√{square root over (NDA+NA−NDD−ND)} are, for example, as indicated below. The preferable ranges indicated below differ according to the respective thicknesses dB and Al compositions of the
electron supply layer 14 and may therefore be set as suited in accordance with the respective thicknesses dB and Al compositions of theelectron supply layer 14. - First, the thickness dG of the
gate layer 15 is preferably, for example, 50 nm to 200 nm. On the other hand, (NDA+NA−NDD−ND) of theelectron transit layer 13 is, for example, 1×1016 cm−3 to 5×1017 cm−3 and preferably, the Mg concentration is not less than 1×1016 cm−3 and more preferably, the Mg concentration is not more than 1×1017 cm−3. - Also, a preferable range of ΦB (work function (eV) of the
gate electrode 16−electron affinity (3.6 eV) of GaN) in the formula (1) above is 0.7 eV to 1.4 eV. This range may be realized using, for example, Ni (ΦM=4.8 eV), Pt (ΦM=5.0 eV), Mo (ΦM=4.3 eV), W (ΦM=4.6 eV), or TiN (ΦM=4.6 eV) as thegate electrode 16. On the other hand, although Al (ΦM=4.0 eV) may also be used as thegate electrode 16, Al is low in work function compared to Mo, etc., mentioned above and reacts readily with a semiconductor or an insulating film and it is therefore preferable to use Mo or TiN which are rather high in work function. - Also, to satisfy the formula (1) above, it is preferable for dBP/ε0εB, corresponding to the increment (P1) of the potential of the conduction band EC, to be made as small as possible. Making dB and P, which are variables of dBP/ε0εB, small is thus considered.
- First, in regard to the thickness dB of the
electron supply layer 14, reference toFIG. 7 shows that regardless of the Al composition (x=0.1 to 0.9) of AlGaN, the sheet carrier density of the two-dimensional electron gas 21 converges to a maximum value at approximately dB=10 nm even when the thickness dB is increased. Therefore, as far as the sheet carrier density is concerned, it suffices for the thickness dB to be 10 nm at the most. Oppositely, as shown inFIG. 8 , dBP/ε0εB, which is the increment (P1) of the potential of the conduction band EC, increases proportionally with an increase in the thickness dB of theelectron supply layer 14 and therefore if making dBP/ε0εB small is considered with priority, it is preferable for the thickness dB to be as small as possible. It is thus preferable for the thickness dB of theelectron supply layer 14 to be as small as possible within a range of not more than 10 nm. - On the other hand, as shown in
FIG. 7 , if the thickness dB of theelectron supply layer 14 is made small, the sheet carrier density decreases. The decrease is especially significant in a region of dB<5 nm. The sheet carrier density is preferably, for example, not less than 6.0×1012 cm−2 because if it is too low, channel mobility decreases. The Al composition of theelectron supply layer 14 should thus be set in a range of not more than 10 nm along the abscissa and not less than 6.0×1012 cm−2 along the ordinate inFIG. 7 . - However, as shown in
FIG. 4 , the Al composition is in a proportional relationship with the variable P in dBP/ε0εB, which corresponds to the increment (P1) of the potential of the conduction band EC and, depending on the case, influences the gate threshold voltage. Relationships of the Al composition of theelectron supply layer 14 and the gate threshold voltage were thus examined. -
FIG. 18 is a diagram showing relationships of the Al composition of theelectron supply layer 14 and the gate threshold voltage according to sheet carrier density.FIG. 15 is a diagram showing relationships of the Al composition of theelectron supply layer 14 and the film thickness of theelectron supply layer 14 according to sheet carrier density. InFIG. 18 andFIG. 19 , calculations were made with the deep acceptor concentration of thegate layer 15 being set to 2×1017 cm−3 and the deep acceptor concentration of theelectron transit layer 13 being set to 4×1016 cm−3. -
FIG. 18 shows that, although depending on the sheet carrier density NS, it is preferable for the Al composition of theelectron supply layer 14 to be not less than 0.3 to realize a normally-off type arrangement. That is, in theelectron supply layer 14, constituted of AlxGa1−xN (x≦1), the Al composition is preferably such that x≧0.3 and more preferably such that x=1. It can also be understood fromFIG. 18 that for the same sheet carrier density, the higher the Al composition of theelectron supply layer 14, the higher the gate threshold voltage. - To set a preferable combination of the Al composition and the thickness dB for the
electron supply layer 14, for example, the Al composition and the sheet carrier density NS of theelectron supply layer 14 at which the gate threshold voltage exceeds 0 V are determined from the graphs ofFIG. 18 and the readings are applied to the graphs of theFIG. 19 to read the thickness dB (film thickness). For example, with any combination within aregion 25 surrounded by alternate long and short dashed lines inFIG. 19 , both a high sheet carrier density (NS≧6.0×1012 cm−2) and a high threshold voltage (Vth>0; x≧0.3 for the electron supply layer 14) can be realized at the same time. - On the other hand, with an AlGaN
electron supply layer 14 with a high Al composition, the channel mobility may decrease due to alloy scattering. Therefore, to suppress alloy scattering and make the gate threshold voltage high, it is preferable to use an AlNelectron supply layer 14. However, if theelectron supply layer 14 is an AlN layer, a problem occurs in that the AlN layer itself becomes oxidized entirely when thegate layer 15 is formed, for example, by etching with Cl2/O2 (seeFIG. 21C described below). - Thus, if the
electron supply layer 14 is to be made an AlN layer, it is preferable to dispose anetching stop layer 24, constituted of AlxGa1−x′N (x′≦1), on theelectron supply layer 14 as shown inFIG. 20 . The AlNelectron supply layer 14 is thereby covered by etchingstop layer 24 in the process of etching thegate layer 15 and the oxidation of the AlNelectron supply layer 14 can thus be suppressed. - Also, if the
etching stop layer 24 is to be formed, it is preferable for the thickness of theelectron supply layer 14 to be not more than 2 nm. Also, the thickness of theetching stop layer 24 is preferably not more than 10 nm. Further, the Al composition of theetching stop layer 24 is preferably such that 0.1≦x′≦0.2 and more preferably such that x′=0.1. The Al composition of theetching stop layer 24 is made not less than 0.1 to sufficiently maintain the etching stop function and meanwhile made not more than 0.2 to keep the influence on the gate threshold voltage Vth small. - The effect of suppressing the oxidation of the
electron supply layer 14 such as described above is not restricted to an AlN layer and can be achieved when theetching stop layer 24, constituted of Alx′Ga1−x′N (x′≦1), is formed on anelectron supply layer 14 constituted of AlxGa1−xN (x≦1) and a relationship, x<x′, is further established in regard to the Al composition. - Also, with the arrangement of
FIG. 20 , theetching stop layer 24 and theelectron supply layer 14 are further removed selectively so as to be continuous with the contact holes 18 a and 19 a, and thesource electrode 18 and thedrain electrode 19 are put in ohmic contact with theelectron transit layer 13 via the contact holes 18 a and 19 a. -
FIG. 21A toFIG. 21F are diagrams showing, in order of process, portions of a manufacturing process of the nitride semiconductor device 3 (third preferred embodiment) ofFIG. 20 . - To manufacture the
nitride semiconductor device 3 ofFIG. 20 , for example, as shown inFIG. 21A , theelectron transit layer 13, theelectron supply layer 14, theetching stop layer 24, and thegate layer 15 are formed on thesubstrate 12, for example, by an epitaxial growth method. - Next, as shown in
FIG. 21B , anelectrode material 26 of thegate electrode 16 is formed on thegate layer 15. - Next, as shown in
FIG. 21C , theelectrode material 26 is etched selectively to form thegate electrode 16. Subsequently, thegate layer 15 is etched selectively using, for example, a Cl2/O2 plasma. The etching stops at the AlGaNetching stop layer 24. - Next, as shown in
FIG. 21D , thesurface insulating film 17, constituted, for example, of SiN, is formed so as to cover theetching stop layer 24, thegate layer 15, and thegate electrode 16. - Next, as shown in
FIG. 21E , thesurface insulating film 17, theetching stop layer 24, and theelectron supply layer 14 are continuously etched selectively to form the contact holes 18 a and 19 a. In this process, contact resistances of thesource electrode 18 and thedrain electrode 19 can be reduced by etching theelectron supply layer 14 as well to expose theelectron transit layer 13. - Next, as shown in
FIG. 21F , thesource electrode 18 and thedrain electrode 19 are formed. By thereafter forming therear surface electrode 22, etc., thenitride semiconductor device 3 is obtained. -
FIG. 22 toFIG. 26 are diagrams of GaN Fermi level dependence of the gate threshold voltage. - More specifically,
FIG. 22 is an energy band diagram of a turn-on state when theelectron supply layer 14 has an Al composition of 40% and a thickness dB of 6 nm, the thickness dG of thegate layer 15 is 60 nm, ΦB=1.2 eV (material of the gate electrode 16: TiN), and NDA+NA−NDD−ND of the electron transit layer 13 (with the deep acceptor being C) is 4×1016 cm−3. -
FIG. 23 is an energy band diagram of a turn-on state when theelectron supply layer 14 has an Al composition of 40% and a thickness dB of 6 nm, the thickness dG of thegate layer 15 is 60 nm, ΦB=1.2 eV (material of the gate electrode 16: TiN), and NDA+NA−NDD−ND of the electron transit layer 13 (with the deep acceptor being Mg) is 4×1016 cm−3. -
FIG. 24 is an energy band diagram of a turn-on state under conditions that are the same as those ofFIG. 22 with the exception that NDA+NA−NDD−ND of theelectron transit layer 13 is 1×1017 cm−3. -
FIG. 25 is an energy band diagram of a turn-on state under conditions that are the same as those ofFIG. 23 with the exception that NDA+NA−NDD−ND of theelectron transit layer 13 is 1×1017 cm−3. - From a comparison of
FIG. 22 andFIG. 23 and a comparison ofFIG. 24 andFIG. 25 , it can be understood that the higher the energy difference EF between the Fermi level and the lower end of the conduction band (EC) of theelectron transit layer 13, the higher the gate threshold voltage. - Also, from a comparison of
FIG. 22 andFIG. 24 and a comparison ofFIG. 23 andFIG. 25 , it can be understood that when using the same deep acceptor, the higher the NDA+NA−NDD−ND of theelectron transit layer 13, the higher the gate threshold voltage. - And, judging comprehensively from
FIG. 26 , it can be understood that it is preferable for the deep acceptor-contained in theelectron transit layer 13 to be Mg (EF=3.2 eV) because the gate threshold voltage can then be made comparatively high, and that NDA+NA−NDD−ND in this case is preferably not less than 1×1016 cm−3 and not more than 1×1018 cm−3. - Although the second and third preferred embodiments of the first invention have been described above, the first invention may be implemented in other modes.
- For example, although with each of the second and third preferred embodiments described above, an example where the
electron transit layer 13 is constituted of GaN and theelectron supply layer 14 is constituted of AlGaN or AlN was described, it suffices that theelectron transit layer 13 and theelectron supply layer 14 differ in Al composition and other combinations are also possible. The electron supply layer/electron transit layer combination may be any of AlGaN layer/GaN layer, AlGaN layer/AlGaN layer (with the layers differing in Al composition), AlInN layer/AlGaN layer, AlInN layer/GaN layer, AlN layer/GaN layer, and AlN layer/AlGaN layer. To generalize further, the electron supply layer contains Al and N in its composition. The electron transit layer contains Ga and N in its composition and differs in Al composition from the electron supply layer. By the electron supply layer and the electron transit layer differing in Al composition, a lattice mismatch arises between the two and carriers due to polarization are thereby made to contribute to the forming of a two-dimensional electron gas. - Also, although with each of the second and third preferred embodiments described above, the case where the
electron supply layer 14 is AlxGa1−xN (x≦1) was mainly described, in a case where theelectron supply layer 14 contains In, that is, with AlxInyGa1−x−yN, x and y may be such that x≧0.3, 0.2≧y≧0, and 1≧x+y. - Also, although with each of the second and third preferred embodiments described above, silicon was taken up as an example of the material of the
substrate 12, besides this, any substrate material, such as a sapphire substrate, a GaN substrate, etc., may be applied. - The second invention relates to a nitride semiconductor device constituted of a group III nitride semiconductor (may hereinafter be referred to simply as “nitride semiconductor” in some cases).
- A group III nitride semiconductor is a semiconductor with which nitrogen is used as a group V element in a group III-V semiconductor. Representative examples are aluminum, nitride (AlN), gallium nitride (GaN), and indium nitride (InN). The semiconductor can be expressed generally as AlxInyGa1−x−yN (0≦x≦1, 0≦y≦1, 0≦x+y≦1).
- An HEMT (High Electron Mobility Transistor) using such a nitride semiconductor has been proposed. Such an HEMT includes, for example, an electron transit layer, constituted of GaN, and an electron supply layer, constituted of AlGaN that is grown epitaxially on the electron transit layer. A pair of source electrode and drain electrode are formed to be in contact with the electron supply layer and a gate electrode is disposed therebetween. Due to polarization caused by lattice mismatch of GaN and AlGaN, a two-dimensional electron gas is formed inside the electron transit layer at a position located only a few Å inward from an interface of the electron transit layer and the electron supply layer. The source and the drain are connected to each other with the two-dimensional electron gas as a channel. When the two-dimensional electron gas is cut off by application of a control voltage to the gate electrode, the source and the drain are cut off from each other. The source and the drain are continuous to each other in a state where the control voltage is not applied to the gate electrode and therefore the device is of the normally-on type.
- Devices using a nitride semiconductor have features of high withstand voltage, high temperature operation, high current density, high speed switching, and low on resistance and are thus being examined for application to power devices.
- However, for use as a power device, a device must be of the normally-off type, in which current is cut off in a zero bias state, and therefore an HEMT such as described above cannot be applied to a power device.
- A structure for realizing a nitride semiconductor HEMT of the normally-off type has been proposed, for example, in Japanese Patent Application Publication No. 2006-339561. Japanese Patent Application Publication No. 2006-339561 discloses an arrangement where a p type GaN gate layer (nitride semiconductor gate layer) is laminated on an AlGaN electron supply layer, a gate electrode is disposed thereon, and the channel is eliminated by a depletion layer spreading from the P type GaN gate layer to realize a normally-off arrangement. In Japanese Patent Application Publication No. 2006-339561, a gate electrode, constituted of Pd (palladium) in ohmic junction with the p type GaN gate layer, is used as the gate electrode.
- Use of a gate electrode, constituted of TiN (titanium nitride) or other metal in Schottky junction with the p type GaN gate layer, as the gate electrode may be considered. A nitride semiconductor device of such an arrangement may be referred to in some cases as a compared device. With the compared device, there is a problem in that due to the nitride semiconductor gate layer and the gate electrode being in Schottky junction, a gate leak current becomes large and the nitride semiconductor gate layer degrades readily.
- An object of the second invention is to provide a nitride semiconductor device with which the gate leak current can be reduced in comparison to the compared device.
- The second invention has the following features.
- A1. A nitride semiconductor device including a first nitride semiconductor layer, constituting an electron transit layer, a second nitride semiconductor layer, formed on the first nitride semiconductor layer, being larger in bandgap than the first nitride semiconductor layer, and constituting an electron supply layer, and a gate portion, disposed on the second nitride semiconductor layer, and where the gate portion includes a nitride semiconductor gate layer, disposed on the second nitride semiconductor layer and containing an acceptor type impurity, a gate insulating film, formed on the nitride semiconductor gate layer, and a gate electrode, formed on the gate insulating film.
- With the present arrangement, the gate insulating film is interposed between the nitride semiconductor gate layer and the gate electrode, and the gate leak current can thus be reduced in comparison to the compared device.
- A2. The nitride semiconductor device according to “A1.,” where the gate insulating film is constituted of one material selected from SiN, SiO2, SiON, Al2O3, AlN, AlON, HfO, HfN, HfON, HfSiON, and AlON.
- A3. The nitride semiconductor device according to “A1.,” where the gate insulating film is constituted of in-situ SiN, formed as a film in-situ with the nitride semiconductor gate layer.
- A4. The nitride semiconductor device according to any one of “A1.” to “A3.,” where the gate leak current is not more than 1 nA/mm.
- A5. The nitride semiconductor device according to any one of “A1.” to “A3.,” where the nitride semiconductor gate layer has a film thickness of not more than 100 nm and the gate insulating film has a film thickness of not less than 3 nm.
- A6. The nitride semiconductor device according to any one of “A1.” to “A5.,” further including a third nitride semiconductor layer, disposed at a side of the first nitride semiconductor layer opposite the second nitride semiconductor layer side and constituting a buffer layer.
- A7. The nitride semiconductor device according to “A1.,” where a carbon concentration of an interface of the nitride semiconductor gate layer and the gate insulating film is not more than 1×1013 cm−2.
- A8. The nitride semiconductor device according to any one of “A1.” to “A7.,” where the first nitride semiconductor layer is constituted of a GaN layer, the second nitride semiconductor layer is constituted of an AlGaN layer, and the nitride semiconductor gate layer is constituted of a p type GaN layer.
- A9. The nitride semiconductor device according to “A6.,” where the first nitride semiconductor layer is constituted of a GaN layer, the second nitride semiconductor layer is constituted of an AlGaN layer, the nitride semiconductor gate layer is constituted of a p type GaN layer, and the third nitride semiconductor layer is constituted of an AlGaN layer.
- A10. The nitride semiconductor device according to “A8.” or “A9.,” where the acceptor type impurity is magnesium or iron.
- A preferred embodiment of the second invention shall be described in detail with reference to
FIG. 27 toFIG. 35 . The symbols used inFIG. 27 toFIG. 35 are in no relationship with the symbols ofFIG. 1 toFIG. 26 used above in the description of the first invention. -
FIG. 27 is a sectional view for describing the arrangement of a nitride semiconductor device according to the preferred embodiment of the second invention. - The
nitride semiconductor device 1 includes asubstrate 2, abuffer layer 3, formed on a front surface of thesubstrate 2, a firstnitride semiconductor layer 4, grown epitaxially on thebuffer layer 3, and a secondnitride semiconductor layer 5, grown epitaxially on the firstnitride semiconductor layer 4. Further, thenitride semiconductor device 1 includes agate portion 20 formed on the secondnitride semiconductor layer 5. - Further, the
nitride semiconductor device 1 includes apassivation film 9, covering the secondnitride semiconductor layer 5 and thegate portion 20, and abarrier metal film 10, laminated on thepassivation film 9. Further, thenitride semiconductor device 1 includes asource electrode 13 and adrain electrode 14, which penetrate through a sourceelectrode contact hole 11 and a drainelectrode contact hole 12, formed in the laminated film of thepassivation film 9 and thebarrier metal film 10, and are in ohmic contact with the secondnitride semiconductor layer 5. Thesource electrode 13 anddrain electrode 14 are disposed across an interval. Thesource electrode 13 is formed so as to cover thegate portion 20. Further, thenitride semiconductor device 1 includes aninterlayer insulating film 15, covering thesource electrode 13 and thedrain electrode 14. - The
substrate 2 may, for example, be a low-resistance silicon substrate. The low-resistance silicon substrate may have an impurity concentration, for example, of 1×1017 cm−3 to 1×1020 cm−3 (more specifically, approximately 1×1018 cm−3). Also, besides a low-resistance silicon substrate, thesubstrate 2 may be a low-resistance GaN substrate or a low-resistance SiC substrate, etc. Thesubstrate 2 has a thickness of approximately 650 μm. - In the present preferred embodiment, the
buffer layer 3 is constituted from a multilayer buffer layer in which a plurality of nitride semiconductor films are laminated. In the present preferred embodiment, thebuffer layer 3 is constituted from afirst buffer layer 3A, constituted of an AlN film in contact with the front surface of thesubstrate 2, and asecond buffer layer 3B, constituted of an AlGaN film laminated on a front surface of thefirst buffer layer 3A (the front surface at the side opposite thesubstrate 2 side). Thefirst buffer layer 3A has a film thickness of approximately 100 nm to 300 nm. Thesecond buffer layer 3B has a film thickness of approximately 100 nm to 5 μm. - The first
nitride semiconductor layer 4 constitutes an electron transit layer. In the present preferred embodiment, the firstnitride semiconductor layer 4 is constituted of a GaN layer doped with an acceptor type impurity and has a thickness of approximately 100 nm to 5 μm. The concentration of the acceptor type impurity is preferably not less than 4×1016 cm−3. In the present preferred embodiment, the acceptor type impurity is C (carbon). - The second
nitride semiconductor layer 5 constitutes an electron supply layer. The secondnitride semiconductor layer 5 is constituted of a nitride semiconductor with a larger bandgap than the firstnitride semiconductor layer 4. Specifically, the secondnitride semiconductor layer 5 is constituted of a nitride semiconductor with a higher Al composition than the firstnitride semiconductor layer 4. In a nitride semiconductor, the higher the Al composition, the larger the bandgap. In the present preferred embodiment, the secondnitride semiconductor layer 5 is constituted of an Alx1Ga1−x1N layer (0<x1<1) and has a thickness of approximately 10 nm to 30 nm. - The first nitride semiconductor layer 4 (electron transit layer) and the second nitride semiconductor layer 5 (electron supply layer) are thus constituted of nitride semiconductors that differ in bandgap (Al composition) and a lattice mismatch occurs therebetween. Due to spontaneous polarizations of the first
nitride semiconductor layer 4 and the secondnitride semiconductor layer 5 and a piezo polarization due to the lattice mismatch between the two, an energy level of a conduction band of the firstnitride semiconductor layer 4 at an interface of the firstnitride semiconductor layer 4 and the secondnitride semiconductor layer 5 is made lower than a Fermi level. A two-dimensional electron gas (2DEG) 16 is thereby made to spread at a position close to the interface of the firstnitride semiconductor layer 4 and the second nitride semiconductor layer 5 (for example, at a distance of only several A from the interface). - The
gate portion 20 includes a nitridesemiconductor gate layer 6, grown epitaxially on the secondnitride semiconductor layer 5, agate insulating film 7, formed on the nitridesemiconductor gate layer 6, and agate electrode 8, formed on thegate insulating film 7. The nitridesemiconductor gate layer 6 is constituted of a nitride semiconductor doped with an acceptor type impurity. In the present preferred embodiment, the nitridesemiconductor gate layer 6 is constituted of a GaN layer (p type GaN layer) doped with the acceptor type impurity and has a thickness of approximately 10 nm to 100 nm. The film thickness of the nitridesemiconductor gate layer 6 is preferably not more than 100 nm. The reason for this shall be described later. In the present preferred embodiment, the film thickness of the nitridesemiconductor gate layer 6 is 60 nm. - The concentration of the acceptor type impurity implanted in the nitride
semiconductor gate layer 6 is preferably not less than 3×1017 cm−3. In the present preferred embodiment, the acceptor type impurity is Mg (magnesium). The acceptor type impurity may be Fe or other acceptor type impurity besides Mg. The nitridesemiconductor gate layer 6 is disposed the two-dimensional electron gas 16 generated in the interface of the first nitride semiconductor layer 4 (electron transit layer) and the second nitride semiconductor layer 5 (electron supply layer). A front surface (upper surface) of the nitridesemiconductor gate layer 6 is a c plane of a GaN crystal and a side surface of the nitridesemiconductor gate layer 6 is an m plane of the GaN crystal. - The
gate insulating film 7 is formed to be in contact with the front surface (c plane) of the nitridesemiconductor gate layer 6. In the present preferred embodiment, thegate insulating film 7 is constituted of in-situ SiN, formed as a film in-situ with the nitridesemiconductor gate layer 6. Thegate insulating film 7 has a thickness of approximately 3 nm to 30 nm. The film thickness of thegate insulating film 7 is preferably not less than 3 nm. In the present preferred embodiment, the film thickness of thegate insulating film 7 is 30 nm. Besides in-situ SiN, thegate insulating film 7 may be constituted from SiN (other than in-situ SiN), SiO2, SiON, Al2O3, AlN, AlON, HfO, HfN, HfON, HfSiON, AlON, etc. - In the present preferred embodiment, a carbon concentration of the interface of the nitride
semiconductor gate layer 6 and thegate insulating film 7 is not more than 1×1013 cm−2. - The
gate electrode 8 is formed to be in contact with a front surface of thegate insulating film 7. In the present preferred embodiment, thegate electrode 8 is constituted from a TiN layer and has a thickness of approximately 50 nm to 200 nm. Thegate electrode 8 is disposed biasedly toward the sourceelectrode contact hole 11. - The
passivation film 9 covers a front surface of the second nitride semiconductor layer 5 (with the exception of regions facing the contact holes 11 and 12) and a side surface and a front surface of thegate portion 20. In the present preferred embodiment, thepassivation film 9 is constituted of an SiN film and has a thickness of approximately 50 nm to 200 nm. In the present preferred embodiment, the thickness of thepassivation film 9 is 50 nm. - The
barrier metal film 10 is laminated on thepassivation film 9. In the present preferred embodiment, thebarrier metal film 10 is constituted of a TiN film and has a thickness of approximately 10 nm to 50 nm. In the present preferred embodiment, the thickness of thebarrier metal film 10 is 25 nm. - In the present preferred embodiment, the
source electrode 13 and thedrain electrode 14 are constituted of lower layers (ohmic metal layers) 13A and 14A, in contact with the secondnitride semiconductor layer 5, intermediate layers (main electrode metal layers) 13B and 14B, laminated on thelower layers intermediate layers lower layers intermediate layers upper layers - The
interlayer insulating film 15 is constituted, for example, of SiO2. Theinterlayer insulating film 15 has a thickness of approximately 1 μm. - With the
nitride semiconductor device 1, a heterojunction is formed by the second nitride semiconductor layer 5 (electron supply layer), differing in bandgap (Al composition) from the first nitride semiconductor layer 4 (electron transit layer), being formed on the firstnitride semiconductor layer 4. The two-dimensional electron gas 16 is thereby formed inside the firstnitride semiconductor layer 4 near the interface of the firstnitride semiconductor layer 4 and the secondnitride semiconductor layer 5, and an HEMT making use of the two-dimensional electron gas 16 as a channel is formed. Thegate electrode 8 faces the secondnitride semiconductor layer 5 across thegate insulating film 7 and the nitridesemiconductor gate layer 6, constituted of the p type GaN layer. - Below the
gate electrode 8, energy levels of the firstnitride semiconductor layer 4 and the secondnitride semiconductor layer 5 are pulled up by the ionized acceptors contained in the nitridesemiconductor gate layer 6, constituted of the p type GaN layer, and therefore the energy level of the conduction band at the heterojunction interface is made higher than the Fermi level. Therefore, the two-dimensional electron gas 16, due to the spontaneous polarizations of the firstnitride semiconductor layer 4 and the secondnitride semiconductor layer 5 and the piezo polarization due to the lattice mismatch of the two layers, is not formed directly below the gate electrode 8 (gate portion 20). Therefore, when a bias is not applied to the gate electrode 8 (zero bias state), the channel due to the two-dimensional electron gas 16 is cut off directly below thegate electrode 8. A normally-off type HEMT is thus realized. When an appropriate on voltage (for example, of 3 V) is applied to thegate electrode 8, a channel is induced inside the firstnitride semiconductor layer 4 directly below thegate electrode 8 and the two-dimensional electron gas 16 at both sides of thegate electrode 8 becomes connected. The source and the drain are thereby made continuous to each other. - For use, for example, a predetermined voltage (for example, of 200 V to 300 V), with which the
drain electrode 14 side becomes positive, is applied across thesource electrode 13 and thedrain electrode 14. In this state, an off voltage (0 V) or an on voltage (3 V) is applied to thegate electrode 8 with thesource electrode 13 being at a reference potential (0 V). -
FIG. 28A toFIG. 28G are sectional views for describing an example of a manufacturing process of thenitride semiconductor device 1 described above and show a cross-sectional structure at a plurality of stages in the manufacturing process. - First, as shown in
FIG. 28A , thebuffer layer 3 and the first nitride semiconductor layer (electron transit layer) 4 are successively grown epitaxially on thesubstrate 2 by an MOCVD (Metal Organic Chemical Vapor Deposition) method. Further, the second nitride semiconductor layer (electron supply layer) 5 is grown epitaxially on the firstnitride semiconductor layer 4 by the MOCVD method. - Next, as shown in
FIG. 28B , a gatelayer material film 31, which is a material film of the nitridesemiconductor gate layer 6, is formed on the secondnitride semiconductor layer 5 by the MOCVD method. Next, an insulatingmaterial film 32, which is a material film of thegate insulating film 7, is formed on the gatelayer material film 31. If, as in the preferred embodiment described above, thegate insulating film 7 is constituted of SiN, film formation of thegate insulating film 32 may be performed in succession to and using the same MOCVD device used in film formation of the gatelayer material film 31. In this case, the insulatingmaterial film 32 becomes in-situ SiN, which is formed as a film in-situ with the gatelayer material film 31. - If the
gate insulating film 7 is SiN, the insulatingmaterial film 32 may also be formed as a film on the gatelayer material film 31 by a plasma CVD method. Also, if thegate insulating film 7 is constituted of SiO2 or other material besides SiN, the insulatingmaterial film 32 may be formed as a film on the gatelayer material film 31 by the plasma CVD method, an LPCVD (Low Pressure CVD) method, an ALD (Atomic Layer Deposition) method, etc. - Thereafter, a
gate electrode film 33, which is a material film of thegate electrode 8, is formed on the insulatingmaterial film 32 by a sputtering method or a vapor deposition method. Thegate electrode film 33 is constituted, for example, of a metal film of TiN. - Next, as shown in
FIG. 28C , a resistfilm 34, covering a region of a front surface of thegate electrode film 33 at which the preparation of the gate electrode is planned, is formed. Thegate electrode film 33, the insulatingmaterial film 32, and the gatelayer material film 31 are then etched selectively using the resistfilm 34 as a mask. - The
gate electrode film 33 is thereby patterned and thegate electrode 8 is obtained. Also, the insulatingmaterial film 32 and the gatelayer material film 31 are patterned in the same pattern as thegate electrode 8. Thegate portion 20, constituted of the nitridesemiconductor gate layer 6, thegate insulating film 7, and thegate electrode 8, is thereby formed on the secondnitride semiconductor layer 5. - Next, the resist
film 34 is removed. Thereafter, as shown inFIG. 28D , thepassivation film 9 is formed by the plasma CVD method or the LPCVD method so as to cover entireties of exposed front surfaces. Thebarrier metal film 10 is then formed on the front surface of thepassivation film 9 by the sputtering method. Thepassivation film 9 is constituted, for example, of an SiN layer. Thebarrier metal film 10 is constituted, for example, of a TiN layer. - Next, as shown in
FIG. 28E , the sourceelectrode contact hole 11 and the drainelectrode contact hole 12 are formed, in the laminated film of thepassivation film 9 and thebarrier metal film 10. - Next, as shown in
FIG. 28F , a source/drain electrode film 35 is formed so as to cover entireties of exposed front surfaces. The source/drain electrode film 35 is constituted of a laminated metal film, in which are laminated aTi layer 35A as a lower layer, anAl layer 35B as an intermediate layer, and aTiN layer 35C as an upper layer, and is formed by vapor depositing the respective layers successively. - Next, as shown in
FIG. 28G , the source/drain electrode film 35 and thebarrier metal film 10 are patterned by etching and further subject to an annealing processing to form thesource electrode 13 and thedrain electrode 14 in ohmic contact with the secondnitride semiconductor layer 5. In this process, thesource electrode 13 is constituted from a lower-layer 13A, constituted of theTiN layer 35A, anintermediate layer 13B, constituted of theAl layer 35B, and anupper layer 13C, constituted of theTiN layer 35C. Also, thedrain electrode 14 is constituted from alower layer 14A, constituted of theTiN layer 35A, anintermediate layer 14B, constituted of theAl layer 35B, and anupper layer 14C, constituted of theTiN layer 35C. - Thereafter, the
interlayer insulating film 15 is formed so as to cover thesource electrode 13, thedrain electrode 14, and thebarrier metal film 10, and thenitride semiconductor device 1 with the structure such as shown inFIG. 27 is thereby obtained. - In the following description, a nitride semiconductor device with an arrangement not provided with the
gate insulating film 7 shall be referred to as a comparative example with respect to thenitride semiconductor device 1 ofFIG. 27 .FIG. 29 is a sectional view of the arrangement of thenitride semiconductor device 101 according to the comparative example. With thenitride semiconductor device 101 according to the comparative example, agate portion 20 is constituted of a nitridesemiconductor gate layer 6, formed on a secondnitride semiconductor layer 5, and agate electrode 8, formed on the nitridesemiconductor gate layer 6. In the comparative example, thegate electrode 8, constituted of TiN, is in Schottky junction with the nitridesemiconductor gate layer 6, constituted of p type GaN. The nitridesemiconductor gate layer 6 of the comparative example has a film thickness of 80 nm. The nitridesemiconductor gate layer 6 of thenitride semiconductor device 1 described above has a film thickness of 60 nm and thegate insulating film 7 has a film thickness of 30 nm. - With the
nitride semiconductor device 101 according to the comparative example, thegate electrode 8 is in Schottky junction with the nitride semiconductor gate layer 6 and therefore the gate leak current is large. The nitridesemiconductor gate layer 6 thus degrades readily. - With the nitride semiconductor device 1 (hereinafter referred to as the “present preferred embodiment”) according to the preferred embodiment described above, the
gate insulating film 7 is formed on the nitridesemiconductor gate layer 6 and thegate electrode 8 is formed on thegate insulating film 7. That is, with the present preferred embodiment, thegate insulating film 7 is interposed between the nitridesemiconductor gate layer 6 and thegate electrode 8, and therefore the gate leak current can be made small in comparison to the comparative example. The nitridesemiconductor gate layer 6 is thereby made unlikely to degrade. With the present preferred embodiment, the gate leak current is not more than 1 nA/mm. - Also, as shall be described later, with the present preferred embodiment, a threshold voltage Vth can be made high in comparison to the comparative example. Also, with the present preferred embodiment, it is possible to make the nitride
semiconductor gate layer 6 thin in comparison to the comparative example, and it is therefore possible to reduce the electric field intensity of the nitridesemiconductor gate layer 6 and the nitridesemiconductor gate layer 6 is made unlikely to undergo time dependent dielectric breakdown (TDDB). Further, with the present preferred embodiment, the threshold voltage Vth can be stabilized in comparison to the comparative example. - The reason why, with the present preferred embodiment, the threshold voltage Vth can be made high in comparison to the comparative example and the reason why the nitride
semiconductor gate layer 6 can be made thin in comparison to the comparative example shall now be described. -
FIG. 30 is an energy band diagram showing an energy distribution of the comparative example.FIG. 31 is an electric field intensity distribution diagram showing an electric field intensity distribution of the comparative example. InFIG. 30 andFIG. 31 , GaN indicates the firstnitride semiconductor layer 4, AlGaN indicates the secondnitride semiconductor layer 5, P-GaN indicates the nitridesemiconductor gate layer 6, and Metal indicates thegate electrode 8. InFIG. 30 , EC is the energy level of the conduction band, EV is the energy level of the valence band, and EF is the Fermi level. - In the comparative example, the
gate electrode 8 is put in Schottky junction with the nitridesemiconductor gate layer 6. A potential barrier (Schottky barrier) ΦB at the interface of thegate electrode 8 and the nitridesemiconductor gate layer 6 influences the threshold voltage Vth. - With the example of
FIG. 30 , the threshold voltage Vth is 2[V]. The threshold voltage Vth of a nitride semiconductor device is small in comparison to the threshold, voltage Vth of an Si semiconductor device and therefore it is important to make the threshold voltage Vth large. To increase the threshold voltage Vth in the comparative example, the film thickness of the nitridesemiconductor gate layer 6 must be increased. Mg and Fe, which are acceptors in p-GaN, have a memory effect, and therefore as can be understood fromFIG. 31 , when the film thickness of the nitridesemiconductor gate layer 6 is made large, the electric field intensity in the interior of the nitridesemiconductor gate layer 6 increases as a portion at the boundary with thegate electrode 8 is approached. Also, a nitride semiconductor is low in the tolerable electric field intensity in comparison to an insulating film. The film thickness of the nitridesemiconductor gate layer 6 thus cannot be increased and it is thus difficult to increase the threshold voltage Vth. The film thickness of the nitridesemiconductor gate layer 6 is ordinarily set to not more than 100 nm. -
FIG. 32 is an energy band diagram showing an energy distribution of the present preferred embodiment.FIG. 33 is an electric field intensity distribution diagram showing an electric field intensity distribution of the present preferred embodiment. InFIG. 32 andFIG. 33 , GaN indicates the firstnitride semiconductor layer 4, AlGaN indicates the secondnitride semiconductor layer 5, P-GaN indicates the nitridesemiconductor gate layer 6, SiN indicates thegate insulating film 7, and Metal indicates thegate electrode 8. InFIG. 32 , EC is the energy level of the conduction band, EV is the energy level of the valence band, and EF is the Fermi level. - In the present preferred embodiment, the
gate insulating film 7 is formed on the nitridesemiconductor gate layer 6. The electric field intensity distribution in the interior of thegate insulating film 7 is uniform and the insulatingfilm 7 is made thick. Therefore, with the present preferred embodiment, the threshold voltage Vth can be made high (3[V] inFIG. 32 ) while making the film thickness of the nitridesemiconductor gate layer 6 thin in comparison to the film thickness of the nitridesemiconductor gate layer 6 of the comparative example (and therefore keeping small the electric field intensity at the boundary of thegate insulating film 7 with the gate electrode 8). - With the present preferred embodiment, the threshold voltage Vth can be made high by forming the
gate insulating film 7 on the nitridesemiconductor gate layer 6 and therefore there is no need to make the film thickness of the nitridesemiconductor gate layer 6 thick to make the threshold voltage Vth high. Thus, in the present preferred embodiment, the film thickness of the nitridesemiconductor gate layer 6 is made thin in comparison to the comparative example. As shown inFIG. 33 , the electric field intensity at the portion of the nitridesemiconductor gate layer 6 at the boundary with thegate insulating film 7 of the present preferred embodiment is thereby made smaller than the electric field intensity at the portion of the nitridesemiconductor gate layer 6 at the boundary with thegate electrode 8 of the comparative example, and therefore, with the present preferred embodiment, time dependent dielectric breakdown (TDDB) of the nitridesemiconductor gate layer 6 is unlikely to occur in comparison to the comparative example. - Although, in the present preferred embodiment, the electric field intensity at the portion of the
gate insulating film 7 at the boundary with thegate electrode 8 becomes higher than the electric field intensity at the portion of the nitridesemiconductor gate layer 6 at the boundary with thegate insulating film 7, there is no problem because the dielectric breakdown voltage of thegate insulating film 7 is higher than the dielectric breakdown voltage of the nitridesemiconductor gate layer 6. - The reason why, with the present preferred embodiment, the threshold voltage Vth can be stabilized in comparison to the comparative example shall now be described.
- The nitride
semiconductor gate layer 6 constituted of p type GaN is a polarizable material and therefore polarization charges appear at the front surface (c plane) thereof. If, in a process of manufacturing the nitridesemiconductor gate layer 6 is exposed to atmosphere, polar organic molecules (carboxylic acids, siloxanes, etc.) become attached to the front surface so as to cancel out the polarization charges on the front surface. - With the comparative example, after the material film (gate layer material film) of the nitride
semiconductor gate layer 6 is formed by a CVD device, the material film (gate electrode film) of the gate electrode is formed on the gate layer material film by a sputtering device. The front surface of the nitridesemiconductor gate layer 6 is thus exposed to the atmosphere and organic molecules in the atmosphere become attached to the front surface. The magnitude of the Schottky barrier ΦB thereby varies and the threshold voltage Vth becomes unstable. - On the other hand, with the present preferred embodiment, after the material film (gate layer material film 31) of the nitride
semiconductor gate layer 6 is formed by the MOCVD device, the material film (insulating material film 32) of thegate insulating film 7, constituted of in-situ SiN, is formed in succession on the gatelayer material film 31 by the same MOCVD device. Therefore, in the process of manufacturing thenitride semiconductor device 1, the front surface (c plane) of the nitridesemiconductor gate layer 6 is not exposed to the atmosphere. Therefore, with the present preferred embodiment, organic molecules are unlikely to become attached to the front surface (c plane) of the nitridesemiconductor gate layer 6 in comparison to the comparative example. Thereby, with the present preferred embodiment, the potential barrier ΦB at the interface of thegate electrode 8 and thegate insulating film 7 is made stable and the threshold voltage Vth is made stable in comparison to the comparative example. - If the insulating
material film 32 is constituted of a material besides in-situ SiN, that is, for example, SiO2, the front surface of the material film (gate layer material film 31) of the nitridesemiconductor gate layer 6 will be exposed to the atmosphere after it is formed by the MOCVD method. In this case, it suffices to form the insulatingmaterial film 32 after removing the organic molecules attached to the front surface of the gatelayer material film 31 by heating the gatelayer material film 31 to not less than 400° C. inside an insulating film forming device, such as a plasma CVD device, an LPCVD device, an ALD device, etc. - An energy distribution and an electric field intensity distribution in a case where the
gate insulating film 7 is constituted of SiO2 are shown inFIG. 34 andFIG. 35 . In the example ofFIG. 34 andFIG. 35 , the gate insulating film (SiO2) 7 has a film thickness of 30 nm and the nitride semiconductor gate layer (p-GaN) 6 has a film thickness of 50 nm. - Although the preferred embodiment of the second invention has been described above, the second invention may be implemented in yet other modes. For example, although with the preferred embodiment described above, an example where the first nitride semiconductor layer (electron transit layer) 4 is constituted of a GaN layer and the second nitride semiconductor layer (electron supply layer) 5 is constituted of an AlGaN layer was described, it suffices that the first
nitride semiconductor layer 4 and the secondnitride semiconductor layer 5 differ in bandgap (for example, in Al composition), and other combinations are also possible. As examples of the firstnitride semiconductor layer 4/secondnitride semiconductor layer 5 combination, GaN/AlN, AlGaN/AlN, etc., can be cited. - Also, although with the preferred embodiment described above, silicon was taken up as an example of the material of the
substrate 2, besides this, any substrate material, such as a sapphire substrate, a GaN substrate, etc., may be applied. - Also, with the preferred embodiment described above, an example where if the
gate electrode 8 is put in junction with the nitridesemiconductor gate layer 6, thegate electrode 8 is constituted from a material such that the two will be in a Schottky junction was described. However, the second invention may also be applied to a case where if thegate electrode 8 is put in junction with the nitridesemiconductor gate layer 6, thegate electrode 7 is constituted from a material such that the two will be in a ohmic junction. - The present application corresponds to Japanese Patent Application No. 2016-163743, filed on Aug. 24, 2016 in the Japan Patent Office, Japanese Patent Application No. 2017-006779, filed on Jan. 18, 2017 in the Japan Patent Office, Japanese Patent Application No. 2017-057830, filed on Mar. 23, 2017 in the Japan Patent Office, and Japanese Patent Application No. 2017-132170, filed on Jul. 5, 2017 in the Japan Patent Office, and the entire disclosures of these applications are incorporated herein by reference.
- While preferred embodiments of the present invention have been described above, it is to be understood that variations and modifications will be apparent to those skilled in the art without departing the scope and spirit of the present invention. The scope of the present invention, therefore, is to be determined solely by the following claims.
Claims (20)
1. A nitride semiconductor device comprising:
an electron transit layer;
an electron supply layer, in contact with the electron transit layer and constituted of a nitride semiconductor composition differing from that of the electron transit layer;
a gate layer, formed selectively on the electron supply layer and constituted of a nitride semiconductor composition effectively not containing an acceptor type impurity; and
a gate electrode, formed on the gate layer, and
wherein the following formula (1) is satisfied:
with the definitions of the respective symbols in the formula (1) being as follows.
dG: thickness (cm) of the gate layer
dB: thickness (cm) of the electron supply layer
P: polarization (C/cm2) of the electron supply layer
q: elementary charge (C)
ΦB: work function (eV) of the gate electrode−electron affinity (3.6 eV) of GaN
NDA+NA−NDD−ND: effective acceptor concentration of the electron transit layer
εC: relative permittivity of the electron transit layer
εB: relative permittivity of the electron supply layer
ε0: permittivity of vacuum
EF: energy difference (eV) between a Fermi level and a lower end of a conduction band (EC) of the electron transit layer
2. The nitride semiconductor device according to claim 1 , wherein the electron transit layer and the gate layer contain GaN and
the electron supply layer contains AlGaN.
3. The nitride semiconductor device according to claim 1 , wherein the effective acceptor concentration NDA+NA−NDD−ND of the electron transit layer is not less than 5×1016 cm−3,
the thickness dG of the gate layer is not less than 80 nm,
an Al composition of the electron supply layer is not more than 25%, and
the thickness dB of the electron supply layer is not more than 20 nm.
4. The nitride semiconductor device according to claim 1 , wherein the electron transit layer contains Mg in a region with 150 nm from an interface with the electron supply layer.
5. The nitride semiconductor device according to claim 1 , wherein the electron transit layer contains Mg as a deep acceptor.
6. The nitride semiconductor device according to claim 1 , wherein the electron transit layer contains C as a deep acceptor.
7. The nitride semiconductor device according to claim 1 , wherein that the gate layer effectively does not contain an acceptor type impurity signifies that a concentration of the acceptor type impurity in the gate layer is less than 1×1017 cm−3.
8. The nitride semiconductor device according to claim 7 , wherein the concentration of the acceptor type impurity in the gate layer is less than 1×1016 cm−3.
9. A nitride semiconductor device comprising:
an electron transit layer, constituted of a nitride semiconductor;
an electron supply layer, constituted of AlxGa1−xN (x≦1) on the electron transit layer;
a gate layer, constituted of a nitride semiconductor formed selectively on the electron supply layer; and
a gate electrode formed on the gate layer; and
wherein the Al composition x of the electron supply layer is such that x≧0.3.
10. The nitride semiconductor device according to claim 9 , wherein a thickness of the electron supply layer is not more than 10 nm.
11. The nitride semiconductor device according to claim 9 , wherein the Al composition x of the electron supply layer is such that x=1.
12. The nitride semiconductor device according to claim 9 , further comprising: an etching stop layer, constituted of Alx′Ga1−x′N (x′≦1) on the electron supply layer; and
wherein a relationship x<x′ holds between the electron supply layer and the etching stop layer.
13. The nitride semiconductor device according to claim 12 , wherein the electron supply layer includes an AlN electron supply layer and
the Al composition x′ of the etching stop layer is such that 0.1≦x′≦0.2.
14. The nitride semiconductor device according to claim 13 , wherein the electron supply layer includes an AlN electron supply layer with a thickness of not more than 2 nm,
the etching stop layer has a thickness of not more than 10 nm, and
the Al composition x′ of the etching stop layer is such that x′=0.1.
15. The nitride semiconductor device according to claim 13 , comprising: a source electrode and a drain electrode disposed to sandwich the gate electrode; and
wherein portions or entireties of the electron supply layer and the etching stop layer are removed selectively in formation regions of the source electrode and the drain electrode.
16. A nitride semiconductor device comprising:
an electron transit layer, constituted of a nitride semiconductor;
an electron supply layer, constituted of AlxInyGa1−x−yN (1≧x+y) on the electron transit layer;
a gate layer, constituted of a nitride semiconductor formed selectively on the electron supply layer; and
a gate electrode formed on the gate layer; and
wherein the Al composition x of the electron supply layer is such that x≧0.3 and the In composition y of the electron supply layer is such that 0.02≧y≧0.
17. The nitride semiconductor device according to claim 9 , wherein the electron transit layer contains Mg as an impurity.
18. The nitride semiconductor device according to claim 17 , wherein a concentration of Mg in the electron transit layer is not less than 1×1016 cm−3 and not more than 1×1017 cm−3.
19. The nitride semiconductor device according to claim 1 , wherein the gate electrode contains Ni, Pt, Mo, W, or TiN.
20. A nitride semiconductor package comprising:
the nitride semiconductor device according to claim 1 ;
a terminal frame, on which the nitride semiconductor device is installed; and
a resin package, sealing the nitride semiconductor device and the terminal frame.
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP3561880A1 (en) * | 2018-04-25 | 2019-10-30 | Commissariat à l'Énergie Atomique et aux Énergies Alternatives | Hemt and manufacturing method favouring smaller gate length and leakage |
CN111681958A (en) * | 2020-05-29 | 2020-09-18 | 华南理工大学 | Method for preparing normally-off HEMT device by novel heterostructure magnesium diffusion |
US20220102543A1 (en) * | 2019-02-01 | 2022-03-31 | Rohm Co., Ltd. | Nitride semiconductor device |
US11600721B2 (en) * | 2019-07-02 | 2023-03-07 | Rohm Co., Ltd. | Nitride semiconductor apparatus and manufacturing method thereof |
US11699749B2 (en) * | 2018-07-12 | 2023-07-11 | Namlab Ggmbh | Heterostructure of an electronic circuit having a semiconductor device |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080073652A1 (en) * | 2004-07-20 | 2008-03-27 | Masahiro Sugimoto | III-V Hemt Devices |
US8072002B2 (en) * | 2008-03-31 | 2011-12-06 | Furukawa Electric Co., Ltd. | Field effect transistor |
US20120119219A1 (en) * | 2010-11-16 | 2012-05-17 | Rohm Co., Ltd. | Nitride semiconductor element and nitride semiconductor package |
US8405126B2 (en) * | 2009-02-13 | 2013-03-26 | Panasonic Corporation | Semiconductor device |
US20130075785A1 (en) * | 2011-09-28 | 2013-03-28 | Fujitsu Limited | Semiconductor device and fabrication method |
US20140346615A1 (en) * | 2013-05-21 | 2014-11-27 | Massachusetts Institute Of Technology | Enhancement-mode transistors with increased threshold voltage |
US20160172476A1 (en) * | 2012-09-28 | 2016-06-16 | Transphorm Japan, Inc. | Semiconductor device and manufacturing method of semiconductor device |
Family Cites Families (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS475412U (en) | 1971-02-10 | 1972-09-18 | ||
US6503769B2 (en) * | 1998-10-26 | 2003-01-07 | Matsushita Electronics Corporation | Semiconductor device and method for fabricating the same |
US7525130B2 (en) * | 2004-09-29 | 2009-04-28 | The Regents Of The University Of California | Polarization-doped field effect transistors (POLFETS) and materials and methods for making the same |
JP4705412B2 (en) | 2005-06-06 | 2011-06-22 | パナソニック株式会社 | Field effect transistor and manufacturing method thereof |
JP4810904B2 (en) * | 2005-07-20 | 2011-11-09 | ソニー株式会社 | High frequency device having high frequency switch circuit |
WO2009001888A1 (en) * | 2007-06-27 | 2008-12-31 | Nec Corporation | Field-effect transistor and multilayer epitaxial film for use in fabrication of the filed-effect transistor |
JP2009054623A (en) | 2007-08-23 | 2009-03-12 | Toshiba Corp | Semiconductor device |
JP2009081177A (en) * | 2007-09-25 | 2009-04-16 | Nec Electronics Corp | Field-effect transistor, semiconductor chip, and semiconductor device |
JP2009200395A (en) * | 2008-02-25 | 2009-09-03 | Sanken Electric Co Ltd | Hfet, and manufacturing method thereof |
JP2009206163A (en) * | 2008-02-26 | 2009-09-10 | Oki Electric Ind Co Ltd | Heterojunction-type field effect transistor |
JP2009246227A (en) * | 2008-03-31 | 2009-10-22 | Toshiba Corp | Semiconductor device |
DE112010001589T5 (en) | 2009-04-08 | 2012-06-28 | Efficient Power Conversion Corporation | Compensated GATE MISFET and process for its production |
JP5562579B2 (en) | 2009-05-12 | 2014-07-30 | 日本碍子株式会社 | Method for producing epitaxial substrate for semiconductor device |
US20110210377A1 (en) * | 2010-02-26 | 2011-09-01 | Infineon Technologies Austria Ag | Nitride semiconductor device |
JP5214652B2 (en) | 2010-03-10 | 2013-06-19 | 株式会社東芝 | Semiconductor device |
US8853709B2 (en) * | 2011-07-29 | 2014-10-07 | Hrl Laboratories, Llc | III-nitride metal insulator semiconductor field effect transistor |
JP5845568B2 (en) * | 2010-11-02 | 2016-01-20 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
WO2012106352A1 (en) * | 2011-01-31 | 2012-08-09 | Efficient Power Conversion Corporation | Ion implanted and self aligned gate structure for gan transistors |
KR101813177B1 (en) | 2011-05-06 | 2017-12-29 | 삼성전자주식회사 | High electron mobility transistor and method of manufacturing the same |
JP5784440B2 (en) | 2011-09-28 | 2015-09-24 | トランスフォーム・ジャパン株式会社 | Semiconductor device manufacturing method and semiconductor device |
JP6014984B2 (en) | 2011-09-29 | 2016-10-26 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
JP5825017B2 (en) | 2011-09-29 | 2015-12-02 | 富士通株式会社 | Compound semiconductor device and manufacturing method thereof |
US8946771B2 (en) * | 2011-11-09 | 2015-02-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Gallium nitride semiconductor devices and method making thereof |
US9269801B2 (en) | 2011-12-27 | 2016-02-23 | Sharp Kabushiki Kaisha | Normally-off-type heterojunction field-effect transistor |
JP6017248B2 (en) | 2012-09-28 | 2016-10-26 | トランスフォーム・ジャパン株式会社 | Semiconductor device manufacturing method and semiconductor device |
US9570600B2 (en) | 2012-11-16 | 2017-02-14 | Massachusetts Institute Of Technology | Semiconductor structure and recess formation etch technique |
JP6119215B2 (en) | 2012-12-03 | 2017-04-26 | 日亜化学工業株式会社 | Field effect transistor |
US10164038B2 (en) * | 2013-01-30 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of implanting dopants into a group III-nitride structure and device formed |
JP2014222724A (en) | 2013-05-14 | 2014-11-27 | 三菱電機株式会社 | Transistor using nitride semiconductor and manufacturing method of the same |
JP6318474B2 (en) * | 2013-06-07 | 2018-05-09 | 住友電気工業株式会社 | Manufacturing method of semiconductor device |
JP6368197B2 (en) | 2014-08-29 | 2018-08-01 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method of semiconductor device |
JP6404697B2 (en) * | 2014-12-10 | 2018-10-10 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method of semiconductor device |
JP6468886B2 (en) | 2015-03-02 | 2019-02-13 | ルネサスエレクトロニクス株式会社 | Semiconductor device manufacturing method and semiconductor device |
CN107924845A (en) * | 2015-08-28 | 2018-04-17 | 夏普株式会社 | Nitride compound semiconductor device |
-
2017
- 2017-08-22 US US15/683,130 patent/US20180061975A1/en not_active Abandoned
-
2019
- 2019-05-07 US US16/405,417 patent/US11233144B2/en active Active
-
2021
- 2021-12-10 US US17/643,761 patent/US11769825B2/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080073652A1 (en) * | 2004-07-20 | 2008-03-27 | Masahiro Sugimoto | III-V Hemt Devices |
US8072002B2 (en) * | 2008-03-31 | 2011-12-06 | Furukawa Electric Co., Ltd. | Field effect transistor |
US8405126B2 (en) * | 2009-02-13 | 2013-03-26 | Panasonic Corporation | Semiconductor device |
US20120119219A1 (en) * | 2010-11-16 | 2012-05-17 | Rohm Co., Ltd. | Nitride semiconductor element and nitride semiconductor package |
US20130075785A1 (en) * | 2011-09-28 | 2013-03-28 | Fujitsu Limited | Semiconductor device and fabrication method |
US20160172476A1 (en) * | 2012-09-28 | 2016-06-16 | Transphorm Japan, Inc. | Semiconductor device and manufacturing method of semiconductor device |
US20140346615A1 (en) * | 2013-05-21 | 2014-11-27 | Massachusetts Institute Of Technology | Enhancement-mode transistors with increased threshold voltage |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP3561880A1 (en) * | 2018-04-25 | 2019-10-30 | Commissariat à l'Énergie Atomique et aux Énergies Alternatives | Hemt and manufacturing method favouring smaller gate length and leakage |
FR3080710A1 (en) * | 2018-04-25 | 2019-11-01 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | HEMT TRANSISTOR AND METHODS OF MANUFACTURING ENABLING LENGTH AND REDUCED GRADE LEAKAGE |
US10879383B2 (en) | 2018-04-25 | 2020-12-29 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | High electron mobility transistor and method of fabrication having reduced gate length and leak current |
US11699749B2 (en) * | 2018-07-12 | 2023-07-11 | Namlab Ggmbh | Heterostructure of an electronic circuit having a semiconductor device |
US12094964B2 (en) | 2018-07-12 | 2024-09-17 | Namlab Ggmbh | Heterostructure of an electronic circuit having a semiconductor device |
US20220102543A1 (en) * | 2019-02-01 | 2022-03-31 | Rohm Co., Ltd. | Nitride semiconductor device |
US11600721B2 (en) * | 2019-07-02 | 2023-03-07 | Rohm Co., Ltd. | Nitride semiconductor apparatus and manufacturing method thereof |
CN111681958A (en) * | 2020-05-29 | 2020-09-18 | 华南理工大学 | Method for preparing normally-off HEMT device by novel heterostructure magnesium diffusion |
Also Published As
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US20190267483A1 (en) | 2019-08-29 |
US11769825B2 (en) | 2023-09-26 |
US11233144B2 (en) | 2022-01-25 |
US20220102545A1 (en) | 2022-03-31 |
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