CN1885527A - 薄膜晶体管及有机发光显示装置的制造方法 - Google Patents
薄膜晶体管及有机发光显示装置的制造方法 Download PDFInfo
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Abstract
提供了TFT和采用所述TFT的OLED的制造方法。所述CMOS TFT的制造方法包括:制备具有第一和第二薄膜晶体管区域的基板;在所述基板上形成栅电极;在包括所述栅电极的所述基板的整个表面上形成栅极绝缘层;在所述栅极绝缘层的预定区域上利用掩模形成半导体层;利用所述栅电极对所述掩模的背部曝光;利用受到背部曝光的掩模向所述第一和第二薄膜晶体管区域的所述半导体层内注入n型杂质离子,形成沟道区以及源极区和漏极区;对所述背部曝光掩模的两侧进行灰化;利用所述灰化掩模向所述第一和第二薄膜晶体管区域的所述半导体层内注入低浓度杂质离子,形成LDD区;以及向所述第二薄膜晶体管区域的半导体层内注入p型杂质离子,形成源极区和漏极区。
Description
技术领域
本发明涉及薄膜晶体管(TFT)以及采用所述薄膜晶体管的有机发光显示装置(OLED)的制造方法,更具体而言,涉及能够降低制造CMOS TFT的时间和成本的TFT以及采用所述TFT的OLED的制造方法。
背景技术
在平板显示装置(FPD)中,有机发光显示装置(OLED)是一种具有宽视角和小于等于1ms的快速响应速度的发光装置。而且,能够以低成本制造具有薄厚度和良好对比度的OLED,因此,其作为下一代平板显示器吸引了大量的注意。
通常,根据以矩阵形式设置的N×M像素的驱动方式将OLED划分为无源矩阵OLED和有源矩阵OLED。
在有源矩阵型OLED中,在单元像素区内设置界定发射区的像素电极和用于向像素电极施加电流或电压的单元像素驱动电路。单元像素驱动电路包括至少一个用于提供与OLED内的像素数量无关的预定电流的TFT,因此OLED可以具有稳定的亮度,并消耗低功率。因此,可以将有源矩阵型OLED有利地应用到具有高分辨率的大尺寸显示器中。
同时,CMOS TFT包括PMOS和NMOS TFT,因此其能够实现各种仅通过NMOS或PMOS TFT难以实现的电路和系统。但是,CMOS TFT的NMOS TFT应当具有轻掺杂漏极(LDD)区,以减少漏电流,并解决诸如由TFT的收缩而引起的热载流子效应的可靠性问题。
图1A到图1D是说明底部栅极型CMOS TFT的常规制造方法的截面图。
参考图1A,基板100包括第一TFT区域a、第二TFT区域b、像素区c和互连区d,利用第一掩模(未示出)在第一和第二TFT区域a和b的预定区域内的基板上形成栅电极110。
此外,在包括栅电极110的基板的整个表面上形成栅极绝缘层120,利用第二掩模(未示出)在栅极绝缘层120的预定区域内形成半导体层130A和130B。
在半导体层130A和130B上形成与栅电极110相对应的第三掩模135,之后,将低浓度杂质离子注入到设置在第一和第二TFT区域内的半导体层130A和130B内。于是,半导体层130A和130B具有注入了低浓度杂质离子的区域130a、130c、130f和130h,以及沟道区130b和130g。
参考图1B,在第一TFT区域a的半导体层130a上形成比沟道区130b宽的第四掩模140a,形成另一第四掩模140b,从而完全覆盖第二TFT区域b的半导体层130b。
接下来,利用第四掩模140a和140b向所得结构内注入高浓度n型杂质离子,从而在第一TFT区域a内形成源极区和漏极区130d和130e。
于是,在第一TFT区域a内形成了底部栅极型NMOS晶体管,其包括源极区和漏极区130d和130e、LDD区130a和130c以及沟道区130b。
参考图1C,形成第五掩模145a,从而完全覆盖第一TFT区域a内的半导体层130A,在第二TFT区域b内形成与沟道区130g相对应的另一第五掩模145b。
接下来,利用第五掩模145a和145b向所得结构内注入p型杂质离子,从而在第二TFT区域b内形成源极区和漏极区130f和130h′。于是,在第二TFT区域b内形成了底部栅极型PMOS晶体管,其包括源极区和漏极区130f′和130h′,以及沟道区130g。
通过上述过程,制作了一种互补金属氧化物半导体(CMOS)TFT,使其具有带有LDD区的NMOS晶体管和PMOS晶体管。
参考图1D,利用第六掩模形成分别与半导体层130A和130B的源极区和漏极区130d、130e、130f′和130h′接触的源电极和漏电极150a、150b、150c和150d,同时在互连区d的栅极绝缘层120上形成公共电源线150e。
源电极和漏电极150a、150b、150c和150d由具有低电阻的材料形成,以降低线路电阻,并且其由MoW、Ti、Al或Al合金构成的多层结构形成。所述多层可以是MoW/Al/MoW、MoW/Al-Nd/MoW、Ti/Al-Nd/Ti或Ti/Al/Ti的三层,优选为MoW/Al/MoW。
接下来,在包括源电极和漏电极150a、150b、150c和150d以及公共电源线150e的基板的整个表面上形成绝缘层160。绝缘层160起着对随后将由源电极和漏电极150a、150b、150c和150d形成的第一电极绝缘的作用,并可以将绝缘层160用作钝化层或平面化层。
利用第七掩模(未示出)在绝缘层160内形成局部暴露源电极/漏电极150d的通路孔165。
之后,在绝缘层160上叠置作为第一电极材料的反射层和透明导电层,利用第八和第九掩模(未示出)形成与通过通路孔165暴露的源电极/漏电极150d连接的第一电极170a。
在包括第一电极170a的基板的整个表面上,利用第十掩模(未示出)形成具有局部暴露第一电极170a的开口185的像素界定层180。
在开口185内形成有机发射层190,在有机发射层190上形成第二电极200。
利用上部基板对所述基板密封,于是完成了OLED的制作。
为了实施如上所述的具有CMOS TFT的OLED,应当在一个基板上形成PMOS和NMOS TFT,因此需要较多的工序和10道掩模。
具体而言,由于CMOS TFT的NMOS TFT应当具有LDD区,以减少漏电流并解决诸如由TFT的收缩而引起的热载流子效应等可靠性问题,因此,使工艺变得复杂,从而延长了工艺的节拍时间(tact time),而且由于掩模数量的增加提高了材料和制造成本。
发明内容
本发明提供了制造CMOS TFT以及采用所述CMOS TFT的OLED的方法,其能够降低时间和成本。
在本发明的示范性实施例中,一种制造CMOS TFT的方法包括:制备具有第一和第二薄膜晶体管区域的基板;在所述基板上形成栅电极;在包括所述栅电极的所述基板的整个表面上形成栅极绝缘层;在所述栅极绝缘层的预定区域上利用掩模形成半导体层;利用所述栅电极对所述掩模的背部曝光;利用受到背部曝光的掩模向所述第一和第二薄膜晶体管区域的所述半导体层内注入n型杂质离子,形成沟道区以及源极区和漏极区;对所述背部曝光掩模的两侧进行灰化;利用所述灰化掩模向所述第一和第二薄膜晶体管区域的所述半导体层内注入低浓度杂质离子,形成LDD区;以及向所述第二薄膜晶体管区域的半导体层内注入p型杂质离子,形成源极区和漏极区。
在本发明的另一示范性实施例中,提供了一种制造OLED的方法,其中,由设置成矩阵的多个信号线界定单元像素区,所述方法包括:制备具有第一和第二薄膜晶体管区域、像素区和互连区的基板;同时形成位于第一和第二薄膜晶体管区域内的基板上的栅电极和位于互连区内的信号线;在包括所述栅电极和所述信号线的基板的整个表面上形成栅极绝缘层;在第一薄膜晶体管区域内的所述栅极绝缘层上形成半导体层,其具有注入了n型杂质离子的源极区和漏极区、沟道区和LDD区;在第二薄膜晶体管区域内的所述栅极绝缘层上形成半导体层,其具有注入了p型杂质离子的源极区和漏极区以及沟道区;在包括所述半导体层的基板上形成绝缘层;在所述绝缘层内形成局部暴露所述源极区和漏极区以及所述信号线的接触孔;以及同时形成:第一电极,其通过所述像素区内的所述接触孔与所述第二薄膜晶体管区域的所述源极区和漏极区的一端连接;第一源电极和漏电极,其与所述第二薄膜晶体管区域的源极区和漏极区的另一端,以及所述第一薄膜晶体管区域的源极区和漏极区的一端连接;以及第二源电极和漏电极,其与所述信号线中的任何一个,以及所述第一薄膜晶体管区域的源极区和漏极区的另一端连接。
附图说明
将参考附图,参照本发明的某些示范性实施例对本发明的上述和其他特征予以说明,其中:
图1A到图1D是说明OLED的常规制造方法的截面图;
图2A到图2C是说明根据本发明的示范性实施例的CMOS TFT的制造方法的截面图;以及
图3A到图3F是说明根据本发明的示范性实施例的采用CMOS TFT的OLED的制造方法的截面图。
具体实施方式
现在将参考附图更为充分地描述本发明,附图中展示了本发明的示范性
实施例。
图2A到图2C是说明根据本发明的示范性实施例的CMOS TFT的制造方法的截面图。
参考图2A,提供具有第一TFT区域a和第二TFT区域b的基板200。利用第一掩模(未示出),在第一和第二TFT区域a和b的预定区域内形成栅电极210。
基板200是由以玻璃、塑料或石英为例的材料形成的透明基板。通过溅射或真空淀积由MoW、Mo、W、WSi2、MoSi2和Al之一形成栅电极210。
在包括栅电极210的基板的整个表面上形成栅极绝缘层220。
栅极绝缘层220可以是利用等离子增强化学气相淀积(PECVD)、低压化学气相淀积(LPCVD)等淀积的氧化硅层、氮化硅层或其组合层。
此外,利用第二掩模(未示出)在第一和第二TFT区域a和b内的栅极绝缘层220上形成半导体层240A和240B。
半导体层240A和240B由非晶硅或多晶硅形成,优选由多晶硅形成。
之后,曝光第二掩模(未示出)的后部,从而形成与栅电极210相对应的第2a掩模250。
这里,由光致抗蚀剂形成第二掩模(未示出),所述光致抗蚀剂由调整粘滞度的溶剂、与紫外光反应的光敏化合物、诸如化学键接(chemical bonding)材料的聚合树脂等组成。当所述光致抗蚀剂为正型时,将曝光部分转换为能够在显影剂中分解并被蚀刻的材料。
因此,在第二掩模(未示出)上进行背部曝光时,将未与栅电极210相对应的,即能够透射从基板200的底部入射的光的半导体层240A和240B内的第二掩模部分转化为能够在显影剂中分解的材料,之后对其进行蚀刻,而光不能穿过与栅电极210相对应的第二掩模部分,因而形成了与栅电极210类似的第2a掩模250。通过实施背部曝光可以在无需额外掩模的情况下形成第2a掩模,由此减少了一道掩模。之后,利用第2a掩模向半导体层240A和240B内注入n型杂质离子,从而形成源极区和漏极区240a、240c、240f和240h,以及沟道区240b和240g。
所述n型杂质可以从下述集合中选出:磷(P)、砷(As)、锑(Sb)和铋(Bi)。
参考图2B,通过在第2a掩模250的两侧实施灰化处理,形成比沟道区240b和240g短的第2b掩模250′。
通常,灰化处理是在光刻工艺之后去除所采用的光致抗蚀剂(PR)的工艺过程,其包括采用氧等离子体或臭氧的干灰化,以及采用热硫酸和过氧化物的混合溶液的湿灰化。这里,根据本发明的灰化可以是干灰化或湿灰化。
在掩模的临界尺寸(CD)损失(loss)小于0.3μm时,所形成的LDD区可能过小,因此,劣化了薄膜特性,当掩模的CD损失大于等于1μm时,沟道的长度短,因此,电子和空穴不能平稳流动。因此,实施灰化,使其具有0.3到1μm的CD损失。
这里,通过对第2a掩模灰化形成第2b掩模250′,由此减少了一道掩模。
利用第2b掩模250’注入低浓度杂质离子,从而形成插置在源极区和漏极区240a、240c、240f和240h与沟道区240b和240g之间的LDD区240d、240e、240i和240j。
利用第2b掩模250′形成LDD区240d、240e、240i和240j,使其具有0.3到1μm的长度。
形成LDD区240d、240e、240i和240j,以改善TFT的特性,其通常由以PH3为例的n型杂质离子形成。与n型杂质离子相比,注入到LDD区内的杂质离子具有低浓度,因此几乎不影响以高浓度n型杂质离子注入的半导体层240A和240B的源极区和漏极区240a、240c、240f和240h。
于是,在第一和第二TFT区域内形成了底部栅极型NMOS晶体管,其包括源极区和漏极区240a、240c、240f和240h、沟道区240b和240g,以及LDD区240d、240e、240i和240j。
参考图2C,形成第3a掩模260a,从而整个覆盖第一TFT区域,在第二TFT区域的沟道区上形成第3b掩模260b。
利用第3a和3b掩模,将p型杂质离子注入到第二TFT区域b的半导体层240B内。
也就是说,将浓度高于n型杂质离子的p型杂质离子注入到注入了n型杂质离子的LDD区以及源极区和漏极区内,从而形成源极区和漏极区240k和2401,于是,在第二TFT区域内形成了PMOS晶体管。
因此,利用三个掩模形成了具有NMOS和PMOS的CMOS TFT,所述NMOS和PMOS具有LDD区。
接下来,现在将对采用所述CMOS TFT的有机发光显示装置(OLED)的制造方法予以说明。
图3A到图3F是说明根据本发明的示范性实施例的采用CMOS TFT的OLED的制造方法的截面图。
参考图3A,提供基板300,其具有第一TFT区域a、第二TFT区域b、开口区域c和互连区d。之后,利用第一掩模(未示出)在第一TFT区域、第二TFT区域和互连区a、b和d内形成栅电极310,同时,在互连区d内形成公共电源线315、数据线(未示出)和扫描线(未示出)。
利用溅射或真空淀积,由MoW、Mo、W、WSi2、MoSi2和Al之一形成栅电极310、公共电源线315等。
接下来,在包括栅电极310和公共电源线315等的基板的整个表面上形成栅极绝缘层320。
利用第二掩模(未示出)在第一和第二TFT区域a和b的栅极绝缘层320上形成半导体层340A和340B,之后,对所述第二掩模(未示出)背部曝光,从而形成与栅电极310相对应的的第2a掩模350。
这里,通过实施背部曝光可以在无需额外掩模的情况下形成第2a掩模,由此能够减少一道掩模。
之后,利用第2a掩模向半导体层340A和340B内注入n型杂质离子,从而形成源极区和漏极区340a、340c、340f和340h,以及沟道区340b和340g。
参考图3B,对第2a掩模350的两侧进行灰化处理,从而形成长度小于沟道区340b和340g的第2b掩模350′。
这里,对第2a掩模进行灰化处理,从而形成第2b掩模350′,由此减少一道掩模。
利用第2b掩模350′注入低浓度杂质离子,从而形成插置在源极区和漏极区340a、340c、340f和340h与沟道区340b和340g之间的LDD区340d、340e、340i和340j。
因此,在第一和第二TFT区域内形成了底部栅极型NMOS晶体管,其包括源极区和漏极区340a、340c、340f和340h、沟道区340b和340g,以及LDD区340d、340e、340i和340j。
参考图3C,形成第3a掩模360a,从而完全覆盖第一TFT区域,在第二TFT区域的沟道区上形成第3b掩模360b。
之后,利用第3a和第3b掩模在第二TFT区域b内向半导体层340B注入p型杂质离子。
也就是说,将浓度高于n型杂质离子的p型杂质离子注入到注入了n型杂质离子的LDD区以及源极区和漏极区内,从而形成源极区和漏极区340k和3401,于是,在第二TFT区域内形成了PMOS晶体管。
参考图3D,在具有半导体层340A和340B的基板上形成绝缘层370。
绝缘层370可以是钝化层,形成其的目的在于保护CMOS TFT免受污染,其由诸如氮化硅层、氧化硅层或其组合层的无机绝缘层形成。
而且,绝缘层370可以是平面化层。形成平面化层370以补偿台阶,平面化层370通常由从下述集合中选出的以有机物为基础的材料形成:苯并环丁烯(BCB)、聚酰亚胺(PI)、聚酰胺(PA)、丙烯酸树脂和酚醛树脂。
此外,利用第四掩模(未示出)对绝缘层370蚀刻,从而形成局部暴露公共电源线315,以及源极区和漏极区340a、340c、340k和3401的接触孔375。
参考图3E,在基板的整个表面上设置第一电极材料,之后利用第五掩模(未示出)对其构图,从而形成第一电极390a,同时形成第一和第二源电极和漏电极390b和390c。
在像素区c内的绝缘层370上设置第一电极,所述第一电极延伸至第二TFT区域b,从而通过接触孔375与源极区和漏极区的一端3401接触。
第一源电极/漏电极390b设置在绝缘层370上,并且通过接触孔375接触第二TFT区域b内的源极区和漏极区的另一端340k,其还延伸至第一TFT区域a,从而通过接触孔375接触源极区和漏极区的一端340c。
第二源电极/漏电极390c设置在绝缘层370上,并且通过接触孔375接触第一TFT区域内的源极区和漏极区的另一端340a,其还延伸至互连区d,从而通过接触孔375接触公共电源线315。
由包括反射层的透明导电层形成第一电极390a以及第一和第二源电极/漏电极390b和390c。
透明导电层由ITO或IZO形成,反射层可以由从下述集合中选出的一种具有高反射率属性的材料形成:Al、Al合金、银和银合金。优选地,可以由银或银合金形成所述反射层。
这里,由于所述反射层由具有高反射率的银或银合金形成,因此,可以提高所述第一电极的反射效率。
而且,当反射层由银或银合金形成时,能够对反射层和透明导电层进行毯式蚀刻(blanket-etched),因此,与常规工艺相比能够减少一道掩模。
参考图3F,在具有第一电极390a以及第一和第二源电极/漏电极390b和390c的基板上利用第六掩模(未示出)形成像素界定层(PDL)400,使其包括局部暴露第一电极390a的表面的开口405。
此外,在通过开口405暴露的第一电极390a上形成至少包括有机发射层的有机层410和第二电极420。
所述有机发射层可以由小分子材料或聚合物形成。所述小分子材料可以从下述集合中选出:Alq3、蒽、环戊二烯、ZnPBO、Balq和DPVBi,所述聚合物可以从下述集合中选出:聚噻吩(PT)、聚(p-亚苯基乙烯撑)(poly(p-phenylenevinylene),PPV)、聚苯撑(PPP)及其衍生物。
除了所述有机发射层之外,所述有机层还可以至少包括电子注入层EIL、电子输运层ETL、空穴输运层HTL和空穴注入层HIL之一。
第二电极是由从下述集合中选出的材料通过真空淀积形成的薄透射电极:Mg、Ca、Al、Ag及其合金。
接下来,利用上部基板对所述基板密封,于是完成了OLED的制作。
如上所述,在根据本发明的OLED的制造方法中,对用来形成半导体层的掩模进行背部曝光和灰化,从而在无需其他掩模的情况下形成CMOSTFT,因而减少了两道掩模。
此外,本发明采用了具有低电阻率的银或银合金以及透明导电层作为第一电极材料,从而同时形成第一电极和第一和第二源电极和漏电极,因此,可以减少一道掩模。
而且,有可能对银或银合金以及透明导电层进行毯式蚀刻,从而又减少了一个掩模。
因此,与常规工艺相比,本发明能够通过简化常规工艺提高成品率,通过减少四道掩模降低生产成本。
如上所述,在根据本发明的CMOS TFT以及采用所述CMOS TFT的OLED的制造方法中,简化了工艺,减少了掩模数量,由此提高了成品率,降低了生产成本。
尽管已经参考本发明的示范性实施例进行了说明,但是本领域的普通技术人员的将要理解,可以在其中做出多种形式和细节上的变化而不脱离由权利要求所限定的本发明的精神和范围。
本申请要求于2005年6月23日提交的韩国专利申请No.2005-54657的优先权和权益,在此将其全文引入以供参考。
Claims (18)
1.一种制造互补金属氧化物半导体薄膜晶体管的方法,包括:
制备具有第一和第二薄膜晶体管区域的基板;
在所述基板上形成栅电极;
在包括所述栅电极的所述基板的整个表面上形成栅极绝缘层;
利用掩模在所述栅极绝缘层的预定区域上形成半导体层;
利用所述栅电极对所述掩模的背部曝光;
利用受到背部曝光的掩模向所述第一和第二薄膜晶体管区域的所述半导体层内注入n型杂质离子,形成沟道区以及源极区和漏极区;
对所述背部曝光的掩模的两侧进行灰化;
利用所述灰化的掩模向所述第一和第二薄膜晶体管区域的所述半导体层内注入低浓度杂质离子,形成轻掺杂漏极区;以及
向所述第二薄膜晶体管区域的半导体层内注入p型杂质离子,形成源极区和漏极区。
2.根据权利要求1所述的方法,其中,所述栅电极材料是从下述集合中选出的一种:MoW、Mo、W、WSi2、MoSi2和Al。
3.根据权利要求1所述的方法,其中,实施所述灰化,使得所述背部曝光的掩模的临界尺寸损失处于0.3到1μm的范围内。
4.根据权利要求1所述的方法,其中,所述n型杂质离子是从下述集合中选出的一种:P、As、Sb和Bi。
5.根据权利要求1所述的方法,其中,所述p型杂质离子是从下述集合中选出的一种:B、Al、Ga和In。
6.根据权利要求1所述的方法,其中,所述p型杂质离子的剂量高于所述n型杂质离子的剂量。
7.一种制造有机发光显示装置的方法,在该有机发光显示装置中,由多个设置成矩阵的信号线界定单元像素区域,所述方法包括:
制备具有第一和第二薄膜晶体管区域、像素区和互连区的基板;
同时形成位于所述第一和第二薄膜晶体管区域内的基板上的栅电极和位于所述互连区内的信号线;
在包括所述栅电极和所述信号线的基板的整个表面上形成栅极绝缘层;
在第一薄膜晶体管区域内的所述栅极绝缘层上形成半导体层,其具有注入了n型杂质离子的源极区和漏极区、沟道区和轻掺杂漏极区;
在第二薄膜晶体管区域内的所述栅极绝缘层上形成半导体层,其具有注入了p型杂质离子的源极区和漏极区,以及沟道区;
在包括所述半导体层的基板上形成绝缘层;
在所述绝缘层内形成局部暴露所述源极区和漏极区以及所述信号线的接触孔;以及
同时形成:第一电极,其通过所述像素区内的所述接触孔与所述第二薄膜晶体管区域的所述源极区和漏极区的一端连接;第一源电极和漏电极,其与所述第二薄膜晶体管区域的源极区和漏极区的另一端,以及所述第一薄膜晶体管区域的源极区和漏极区的一端连接;以及第二源电极和漏电极,其与所述信号线中的任何一个,以及所述第一薄膜晶体管区域的源极区和漏极区的另一端连接。
8.根据权利要求7所述的方法,其中,所述栅电极是由从下述集合中选出的一种材料形成的:MoW、Mo、W、WSi2、MoSi2和Al。
9.根据权利要求7所述的方法,其中,所述信号线是由与所述栅电极相同的材料形成的。
10.根据权利要求7所述的方法,其中,所述第一薄膜晶体管区域内的所述源极区和漏极区是通过利用所述栅电极凭借所述背部曝光的掩模注入n型杂质离子形成的。
11.根据权利要求7所述的方法,其中,所述第一薄膜晶体管区域内的所述轻掺杂漏极区是通过利用掩模注入低浓度杂质离子形成的,所述掩模是通过对背部曝光掩模的两侧灰化形成的。
12.根据权利要求11所述的方法,其中,实施所述灰化,使得所述背部曝光的掩模的临界尺寸损失处于0.3到1μm的范围内。
13.根据权利要求7所述的方法,其中,所述n型杂质离子是从下述集合中选出的一种:P、As、Sb和Bi。
14.根据权利要求7所述的方法,其中,所述p型杂质离子是从下述集合中选出的一种:B、Al、Ga和In。
15.根据权利要求7所述的方法,其中,所述p型杂质离子的剂量高于所述n型杂质离子的剂量。
16.根据权利要求7所述的方法,其中,所述第一电极以及所述第一和第二源电极和漏电极包括反射层和透明导电层。
17.根据权利要求14所述的方法,其中,所述反射层由银或银合金形成。
18.根据权利要求14所述的方法,其中,所述反射层和所述透明导电层是利用干法蚀刻或湿法蚀刻通过毯式蚀刻形成的。
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Cited By (3)
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---|---|---|---|---|
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Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
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JP5720816B2 (ja) * | 2011-06-24 | 2015-05-20 | 三菱マテリアル株式会社 | 導電性膜 |
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US8796682B2 (en) * | 2011-11-11 | 2014-08-05 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing a semiconductor device |
US8841657B2 (en) * | 2012-08-06 | 2014-09-23 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Organic display device and manufacturing method thereof |
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CN105097827A (zh) * | 2015-06-08 | 2015-11-25 | 深圳市华星光电技术有限公司 | Ltps阵列基板及其制造方法 |
KR102446828B1 (ko) * | 2017-06-16 | 2022-09-26 | 삼성디스플레이 주식회사 | 표시 장치 및 그 제조 방법 |
CN112259703B (zh) * | 2020-10-21 | 2023-12-01 | 安徽熙泰智能科技有限公司 | 一种硅基oled微显示器的制备方法 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4767723A (en) | 1987-10-30 | 1988-08-30 | International Business Machines Corporation | Process for making self-aligning thin film transistors |
CN1033252C (zh) | 1992-12-29 | 1996-11-06 | 株式会社金星社 | 制造薄膜晶体管的方法 |
CN1095204C (zh) | 1993-03-12 | 2002-11-27 | 株式会社半导体能源研究所 | 半导体器件和晶体管 |
JP3137797B2 (ja) | 1993-03-12 | 2001-02-26 | 株式会社半導体エネルギー研究所 | 薄膜トランジスタおよびその作製方法 |
KR100265553B1 (ko) * | 1997-05-23 | 2000-09-15 | 구본준 | 박막트랜지스터의 제조방법 |
JP4094179B2 (ja) | 1998-08-21 | 2008-06-04 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
JP4202502B2 (ja) * | 1998-12-28 | 2008-12-24 | 株式会社半導体エネルギー研究所 | 半導体装置 |
JP4801238B2 (ja) | 1999-03-23 | 2011-10-26 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
KR20020032580A (ko) * | 1999-09-16 | 2002-05-03 | 모리시타 요이찌 | 박막트랜지스터 및 그 제조방법 |
JP2002014628A (ja) | 2000-04-27 | 2002-01-18 | Semiconductor Energy Lab Co Ltd | 半導体装置およびその作製方法 |
SG103846A1 (en) * | 2001-02-28 | 2004-05-26 | Semiconductor Energy Lab | A method of manufacturing a semiconductor device |
KR100543061B1 (ko) | 2001-06-01 | 2006-01-20 | 엘지.필립스 엘시디 주식회사 | 구동회로부 일체형 액정표시장치용 어레이 기판의 제조방법 |
KR100441435B1 (ko) * | 2002-05-31 | 2004-07-21 | 삼성에스디아이 주식회사 | 액티브 매트릭스 타입의 유기전계발광표시장치의 제조방법 |
JP3499860B2 (ja) | 2003-03-07 | 2004-02-23 | 三菱電機株式会社 | 薄膜トランジスタおよびその製法 |
KR100560782B1 (ko) | 2003-08-25 | 2006-03-13 | 삼성에스디아이 주식회사 | 유기 전계 발광 표시 장치 |
CN100568457C (zh) * | 2003-10-02 | 2009-12-09 | 株式会社半导体能源研究所 | 半导体装置的制造方法 |
KR100560402B1 (ko) | 2003-11-04 | 2006-03-14 | 엘지.필립스 엘시디 주식회사 | 수평 전계 인가형 박막 트랜지스터 기판 및 그 제조 방법 |
KR100579184B1 (ko) * | 2003-11-24 | 2006-05-11 | 삼성에스디아이 주식회사 | 유기전계발광표시장치 |
KR100611147B1 (ko) * | 2003-11-25 | 2006-08-09 | 삼성에스디아이 주식회사 | 유기전계발광표시장치 |
-
2005
- 2005-06-23 KR KR1020050054657A patent/KR100731750B1/ko active IP Right Grant
-
2006
- 2006-06-22 US US11/473,455 patent/US7915102B2/en active Active
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101997025A (zh) * | 2009-08-25 | 2011-03-30 | 三星移动显示器株式会社 | 有机发光二极管显示器及其制造方法 |
CN101997025B (zh) * | 2009-08-25 | 2013-05-08 | 三星显示有限公司 | 有机发光二极管显示器及其制造方法 |
CN104882415A (zh) * | 2015-06-08 | 2015-09-02 | 深圳市华星光电技术有限公司 | Ltps阵列基板及其制造方法 |
CN104882415B (zh) * | 2015-06-08 | 2019-01-04 | 深圳市华星光电技术有限公司 | Ltps阵列基板及其制造方法 |
WO2017107268A1 (zh) * | 2015-12-22 | 2017-06-29 | 深圳市华星光电技术有限公司 | 互补金属氧化物半导体器件及其制备方法 |
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