CN1846304B - 用于形成具有隔离区的半导体器件的方法 - Google Patents

用于形成具有隔离区的半导体器件的方法 Download PDF

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Publication number
CN1846304B
CN1846304B CN2004800250641A CN200480025064A CN1846304B CN 1846304 B CN1846304 B CN 1846304B CN 2004800250641 A CN2004800250641 A CN 2004800250641A CN 200480025064 A CN200480025064 A CN 200480025064A CN 1846304 B CN1846304 B CN 1846304B
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China
Prior art keywords
layer
current electrode
forming
dielectric
semiconductor
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Expired - Fee Related
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CN2004800250641A
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English (en)
Chinese (zh)
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CN1846304A (zh
Inventor
马里乌斯·K·奥尔沃夫斯基
亚历山大·L·巴尔
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NXP USA Inc
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Freescale Semiconductor Inc
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Publication of CN1846304A publication Critical patent/CN1846304A/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/608—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having non-planar bodies, e.g. having recessed gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0145—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations of trenches having shapes other than rectangular or V-shape
    • H10W10/0147—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations of trenches having shapes other than rectangular or V-shape the shapes being altered by a local oxidation of silicon process, e.g. trench corner rounding by LOCOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Element Separation (AREA)
  • Thin Film Transistor (AREA)
CN2004800250641A 2003-09-23 2004-09-10 用于形成具有隔离区的半导体器件的方法 Expired - Fee Related CN1846304B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/668,714 2003-09-23
US10/668,714 US6964911B2 (en) 2003-09-23 2003-09-23 Method for forming a semiconductor device having isolation regions
PCT/US2004/029381 WO2005034186A2 (en) 2003-09-23 2004-09-10 Method for forming a semiconductor device having isolation regions

Publications (2)

Publication Number Publication Date
CN1846304A CN1846304A (zh) 2006-10-11
CN1846304B true CN1846304B (zh) 2012-01-11

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN2004800250641A Expired - Fee Related CN1846304B (zh) 2003-09-23 2004-09-10 用于形成具有隔离区的半导体器件的方法

Country Status (7)

Country Link
US (1) US6964911B2 (https=)
EP (1) EP1668691A2 (https=)
JP (1) JP5068074B2 (https=)
KR (1) KR101120770B1 (https=)
CN (1) CN1846304B (https=)
TW (1) TWI364813B (https=)
WO (1) WO2005034186A2 (https=)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040242015A1 (en) * 2003-03-04 2004-12-02 Kyoung-Chul Kim Etching compositions for silicon germanium and etching methods using the same
KR100583725B1 (ko) * 2003-11-07 2006-05-25 삼성전자주식회사 부분적으로 절연된 전계효과 트랜지스터를 구비하는반도체 장치 및 그 제조 방법
KR100598098B1 (ko) * 2004-02-06 2006-07-07 삼성전자주식회사 매몰 절연 영역을 갖는 모오스 전계 효과 트랜지스터 및그 제조 방법
US7256077B2 (en) * 2004-05-21 2007-08-14 Freescale Semiconductor, Inc. Method for removing a semiconductor layer
KR100555569B1 (ko) * 2004-08-06 2006-03-03 삼성전자주식회사 절연막에 의해 제한된 채널영역을 갖는 반도체 소자 및 그제조방법
JP4888118B2 (ja) * 2004-09-16 2012-02-29 富士通セミコンダクター株式会社 半導体装置の製造方法及び半導体装置
WO2007027924A1 (en) * 2005-08-31 2007-03-08 Spinnaker Semiconductor, Inc. Metal source/drain schottky barrier silicon-on-nothing mosfet device and method thereof
US7326601B2 (en) * 2005-09-26 2008-02-05 Advanced Micro Devices, Inc. Methods for fabrication of a stressed MOS device
JP2007165677A (ja) * 2005-12-15 2007-06-28 Seiko Epson Corp 半導体基板の製造方法及び半導体装置
JP2007201003A (ja) * 2006-01-24 2007-08-09 Seiko Epson Corp 半導体基板の製造方法及び半導体装置の製造方法、半導体装置
JP2007207960A (ja) * 2006-02-01 2007-08-16 Seiko Epson Corp 半導体基板、半導体基板の製造方法及び半導体装置
FR2901058A1 (fr) * 2006-08-29 2007-11-16 St Microelectronics Crolles 2 Dispositif a fonction dissymetrique et procede de realisation correspondant.
US7521314B2 (en) * 2007-04-20 2009-04-21 Freescale Semiconductor, Inc. Method for selective removal of a layer
US8866254B2 (en) * 2008-02-19 2014-10-21 Micron Technology, Inc. Devices including fin transistors robust to gate shorts and methods of making the same
US20120146175A1 (en) * 2010-12-09 2012-06-14 Nicolas Loubet Insulating region for a semiconductor substrate
US9196522B2 (en) 2013-10-16 2015-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with buried insulator layer and method for forming

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1184328A (zh) * 1996-10-25 1998-06-10 国际整流器公司 带有自对准单元的mos栅极器件的制造方法
US6091076A (en) * 1996-06-14 2000-07-18 Commissariat A L'energie Atomique Quantum WELL MOS transistor and methods for making same
US6352903B1 (en) * 2000-06-28 2002-03-05 International Business Machines Corporation Junction isolation
CN1440079A (zh) * 2002-02-20 2003-09-03 台湾积体电路制造股份有限公司 可避免产生漏电流的mos管结构及具有该结构的cmos影像管

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Publication number Priority date Publication date Assignee Title
JPH077773B2 (ja) * 1989-03-01 1995-01-30 工業技術院長 半導体装置の製造方法
JPH0521465A (ja) * 1991-07-10 1993-01-29 Fujitsu Ltd 半導体装置及びその製造方法
US6015917A (en) * 1998-01-23 2000-01-18 Advanced Technology Materials, Inc. Tantalum amide precursors for deposition of tantalum nitride on a substrate
FR2799307B1 (fr) * 1999-10-01 2002-02-15 France Telecom Dispositif semi-conducteur combinant les avantages des architectures massives et soi, procede de fabrication
FR2812764B1 (fr) * 2000-08-02 2003-01-24 St Microelectronics Sa Procede de fabrication d'un substrat de type substrat-sur- isolant ou substrat-sur-vide et dispositif obtenu
FR2821483B1 (fr) * 2001-02-28 2004-07-09 St Microelectronics Sa Procede de fabrication d'un transistor a grille isolee et a architecture du type substrat sur isolant, et transistor correspondant
US6551937B2 (en) * 2001-08-23 2003-04-22 Institute Of Microelectronics Process for device using partial SOI
JP4546021B2 (ja) * 2002-10-02 2010-09-15 ルネサスエレクトロニクス株式会社 絶縁ゲート型電界効果型トランジスタ及び半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6091076A (en) * 1996-06-14 2000-07-18 Commissariat A L'energie Atomique Quantum WELL MOS transistor and methods for making same
CN1184328A (zh) * 1996-10-25 1998-06-10 国际整流器公司 带有自对准单元的mos栅极器件的制造方法
US6352903B1 (en) * 2000-06-28 2002-03-05 International Business Machines Corporation Junction isolation
CN1440079A (zh) * 2002-02-20 2003-09-03 台湾积体电路制造股份有限公司 可避免产生漏电流的mos管结构及具有该结构的cmos影像管

Also Published As

Publication number Publication date
WO2005034186A3 (en) 2005-11-03
CN1846304A (zh) 2006-10-11
WO2005034186A2 (en) 2005-04-14
KR101120770B1 (ko) 2012-03-23
JP2007507092A (ja) 2007-03-22
KR20060121883A (ko) 2006-11-29
US6964911B2 (en) 2005-11-15
EP1668691A2 (en) 2006-06-14
US20050064669A1 (en) 2005-03-24
TW200520146A (en) 2005-06-16
JP5068074B2 (ja) 2012-11-07
TWI364813B (en) 2012-05-21

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