CN1781187A - 使用非对称导电隔离体的半导体制造工艺 - Google Patents

使用非对称导电隔离体的半导体制造工艺 Download PDF

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CN1781187A
CN1781187A CNA200480011412XA CN200480011412A CN1781187A CN 1781187 A CN1781187 A CN 1781187A CN A200480011412X A CNA200480011412X A CN A200480011412XA CN 200480011412 A CN200480011412 A CN 200480011412A CN 1781187 A CN1781187 A CN 1781187A
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里奥·马修
姆拉利德哈·拉玛钱德兰
詹姆斯·W.·米勒
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NXP USA Inc
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Abstract

一种半导体工艺和所得到的晶体管包括在栅电极(116)的任一侧上形成导电延伸部隔离体(146，150)。对导电延伸部(146，150)和栅电极(116)独立地进行掺杂，使得每一个结构可以是n型或者p型。从侧面对源/漏区(156)进行注入，设置在隔离体(146，150)的任一侧上。可以对隔离体(146，150)独立地进行掺杂：使用第一倾斜注入(132)掺杂第一延伸部隔离体(146)，使用第二倾斜注入(140)对第二隔离体(150)掺杂。在一个实施例中，掺杂不同的延伸部隔离体(146，150)的使用消除了对阈值调整沟道注入的需要。

Description

使用非对称导电隔离体的半导体制造工艺
技术领域
本发明总体上涉及半导体制造领域。具体地，涉及形成具有低泄漏和可接受的阈电压的小型晶体管的工艺。
背景技术
在半导体器件领域，晶体管必须同时具有高性能和低功耗特性。这两个参数一般是相互矛盾的。例如，晶体管沟道长度的降低可提升器件的速度，其它参数比如阈下泄漏(亚阈值泄漏，subthresholdleakage)以及阈电压可能变得更加难以控制。传统上，掺杂晶体管沟道被用来将阈电压控制在所需范围内。常常使用离子注入来实现这些掺杂沟道。
最近，已经用绝缘体上硅(SOI)技术来实现更低的功耗。另外，每有新的工艺技术，栅极长度就会降低。使用传统的沟道掺杂注入难以始终如一地实现SOI所需的浅沟道和深的亚微米器件。但是，如果没有这些掺杂沟道，就难以制造具有充分低的泄漏电流、足够的阈电压和可接受的低阈电压变化的深亚微米器件(deep sub-microndevices)。因此，希望实现一种工艺，其所得到的晶体管具有较短的沟道长度、足够的阈电压以及较低的阈下泄漏，而又不会显著增加工艺的成本或者复杂性。
发明内容
上面提出的问题由一种半导体工艺及其其所得到的晶体管来解决。该工艺包括在栅电极的任一侧形成导电延伸部。所述导电延伸部和栅电极被独立掺杂，使得每一个结构可以是n型、p型或者本征的。源/漏区被从侧面进行离子注入，被设置在所述延伸部的任一侧。所述延伸部可以被独立掺杂：使用第一倾斜注入来对第一延伸部掺杂，使用第二倾斜注入来对第二延伸部掺杂。在一个实施例中，进行了不同的掺杂的延伸部的使用消除了对阈值调整沟道注入的需要，从而晶体管的沟道区基本上没有注入的物质。
附图说明
阅读下面结合附图进行的说明可以最好地理解本发明及其其它优点。附图中：
图1是在半导体衬底上形成栅极电介质的半导体晶片的局部剖视图；
图2图解了图1之后的处理，其中在栅极电介质上形成栅电极膜；
图3图解了图2之后的处理，其中对栅电极膜进行图案化以形成栅电极结构；
图4图解了图3之后的处理，其中，在衬底和栅电极上形成电介质；
图5图解了图4之后的处理，其中，在电介质膜上形成导电膜；
图6图解了图5之后的处理，其中，用第一掺杂剂对导电膜的第一部分进行注入；
图7图解了图6之后的处理，其中，用第二掺杂剂对导电膜的第二部分进行注入；
图8图解了图7之后的处理，其中，对导电膜进行图案化以形成导电延伸部；
图9图解了图8之后的处理，其中，在所述延伸部和栅电极上形成电介质膜；
图10图解了图9之后的处理，其中，对电介质膜进行蚀刻以形成电介质隔离体；
图11图解了图10之后的处理，其中，利用栅电极、延伸部和电介质作为注入掩模，对衬底的源/漏区进行注入；
图12图解了图11之后的处理，其中，在晶片上淀积金属膜；
图13图解了图12之后的处理，其中，通过硅化物的热处理将栅电极和延伸部连接起来；
图14是连接延伸部与晶体管的其余部分的另一种方法的顶视图。
具体实施方式
下面详细描述本发明的在当前为优选的图示于附图中的实施例。应当注意，附图是简化形式的，并且不是精确比例。尽管本发明在这里描述的是特定的图解实施例，但是应当理解这些实施例只是作为例子，而不是限制性的。下面的详细说明的意图是要覆盖落在本发明的权利要求所限定的实质范围内的所有修改、备选方案和等效方案。
应当理解，这里所描述的工艺步骤和结构并未涵盖完整的集成电路制造工艺流程。本发明的实施可以与本领域传统上使用的各种集成电路制造技术结合起来，在本说明书中所包括的通常所采用的工艺步骤只限于那些对本发明的理解来说所需的工艺步骤。
总体来说，本发明考虑使用在晶体管栅电极侧壁上的导电隔离体结构(这里称为延伸部)来形成晶体管。与传统的栅电极结构一起，所述导电隔离体形成一个三部分的晶体管栅极。这三个栅极结构中的每一个的极性都可以单独控制，以使得晶体管例如可以具有一个极性的两个结构和另一个极性的一个结构。这样，能够提供非对称掺杂的延伸部的能力有益地改善了控制非常短沟道的晶体管的阈电压、阈下泄漏和沟道长度的能力。
现在看图1，在半导体晶片100的半导体衬底102上形成栅极电介质膜104。在一个实施例中，栅极电介质104是对半导体衬底102的上表面进行热氧化而形成的二氧化硅膜。如半导体制造工艺领域的人所公知的，衬底102的热氧化是通过在超过900摄氏度的温度下将晶片暴露于氧化氛围(例如O2，H2O)而实现的。在本实施例中，栅极电介质102在任何地方的厚度都是从15到150埃。在其它实施例中，栅极电介质104为介电常数大于4.0的高k电介质。高k电介质适合用于栅极介电膜，以用较厚的膜实现足够大的电容。适合用作电介质104的高k实施例的材料包括各种金属氧化物，比如氧化铪以及其它材料，包括氧化铝、硅酸铪、硅酸锆、铝酸铪、铝酸镧、铝酸锆以及氧化镧。有关高k电介质的另外的信息例如可以在Samavedam，Transistor having a high K dielectric and short gate length and methodtherefor，美国专利6,514,808中找到。
半导体衬底102的上部一般包括单晶半导体材料比如硅，其上形成栅极电介质104。在尤其适合用于低功耗应用比如移动和无线设备的一种实施例中，半导体衬底102是绝缘体上硅(SOI)衬底，其中，单晶硅是是形成在埋置氧化物(厚度大致在1000到20000埃的范围内)上的较薄的膜(也就是小于10000埃)。
现在看图2，在栅极电介质104上形成栅电极膜106。在一个实施例中，栅电极膜106是通过在维持在大约550到650摄氏度范围内的温度的反应室内对硅烷进行热分解而形成的多晶硅膜。该多晶硅膜倾向于沉积为未掺杂的硅，随后使用离子注入，用n型(例如磷、砷)或者p型(例如硼)掺杂剂掺杂。在另外的实施例中，所述多晶硅可以原位掺杂(be doped in-situ)或者通过扩散掺杂。在另外的实施例中，除了多晶硅之外或者取代多晶硅，栅电极膜可以包括下述材料或者化合物：锗、氮化硅钽、氮化钛、氮化钼或者它们的组合。
现在看图3，栅电极膜106被图案化以形成具有基本上竖直的侧壁112的栅电极116。栅电极116的图案化是使用本领域公知的光刻工艺以及各向异性或者干蚀刻技术实现的。光刻工艺可以包括使用减反射镀层(anti-reflective coating(ARC))和光致抗蚀剂构图(图案化)技术。
现在看图4，在栅电极116上形成延伸部电介质膜120。在一个实施例中，电介质膜120是低k电介质，其介电常数小于大约4.0。在另外的实施例中，电介质膜120包括化学蒸汽淀积(chemically vapordeposited(CVD))的氮化硅膜。在该实施例中，可以使二氯甲硅烷或者硅烷和氨在维持在300到800摄氏度温度范围内的反应器中反应而形成CVD氮化硅。可以在淀积氮化硅之前在栅电极116上淀积CVD氧化硅垫层，以缓解当氮化硅接触硅时产生的应力。基本上以共形的方式淀积CVD电介质膜120，使得在晶片表面形态的竖直部分的膜厚大致在晶片表面形态的水平部分的膜厚的至少80％之内。
可以对电介质膜120进行各向异性蚀刻，或者照淀积时的原样留下。如果蚀刻电介质膜120，与栅电极116的侧壁相邻的膜部分留下来，形成栅电极116和随后淀积的导电延伸部结构之间的隔离。还希望将衬底102的未被栅电极116覆盖的部分上的电介质膜留下来，以将导电延伸部结构与衬底102隔离开。如果蚀刻膜120，则可由栅电介质104在蚀刻膜120之后留下的部分提供与衬底之间的隔离。另外，如果膜120包括在氧化硅垫层上的氮化硅，则对膜120的蚀刻最好将氮化硅除去，但留下氧化硅。
在形成电介质膜120之后可以进行一个或者多个注入步骤。在一个实施例中，进行一次或者多次延伸部注入，以在衬底102的未被栅电极116覆盖的那些部分中引入源/漏延伸部区域118。下面将源/漏延伸部区域称为LDD区域118，以避免与上面提及的以及后面要进一步描述的导电延伸部混淆。LDD注入区118可以用来控制所得到的器件的阈电压和有效沟道长度。但是，在衬底102的SOI实施例中，不希望进行高剂量的例子注入，因为那样的话难以将剂量充分地维持在非常浅的硅衬底范围内。为了解决此问题，从工艺的某些实施例中，可以完全取消LDD注入，在这种情况下，阈电压的控制是通过改变延伸部之一的掺杂极性来实现的(下面将详细描述)。
现在看图5，在电介质膜120上淀积导电的延伸部隔离膜124。在一个实施例中，延伸部隔离膜124是与栅电极膜106的多晶硅实施方式(见图2的描述)基本上相同的方式形成的CVD多晶硅。在此实施例中，多晶硅被淀积为未掺杂的膜，使得膜的各个部分随后可以按照需要掺杂。在其它的实施例中，延伸部隔离膜124是另一种导电膜，比如硅锗或者钽或者钛基金属。
现在看图6和图7，执行第一和第二注入132和140。按照一般在6度到60度之间的第一注入角度执行第一注入132，以将第一掺杂剂引入导电延伸部膜124。在第一注入132期间使用的注入角度使得注入物质主要留在导电延伸部124的暴露于注入角度的部分136中。通过使用合适的注入角度，并使晶体管在晶片100上合适地取向(例如相对于晶片平面)，第一注入132在导电延伸部膜124的第一部分136中产生第一掺杂分布，其中，延伸部膜124的第一部分136代表膜124的在栅电极116的第一侧壁112上的部分。
类似地，通过使用第二注入角度，第二注入140主要向延伸部膜124的第二部分142中引入第二掺杂分布。第二注入角度最好与第一注入132期间使用的第一注入角度相反。例如，如果第一注入132的角度是10度，则第二注入140的角度最好是-10度。在一个适合控制晶体管的阈电压和阈下泄漏的实施例中，在第一注入132和第二注入140期间使用的注入物质的极性是相反的。这样，第一注入132可以使用p型物质，比如硼，而第二注入140使用n型物质，比如磷或者砷。在适合制造n沟道晶体管的一个特别实施例中，例如，导电栅极116和延伸部膜124的第二部分142被进行n掺杂，同时延伸部膜124的第一部分136被p掺杂。在该实施例中，当膜124的第一部分136下方的区域被用作器件的漏区，所得到的晶体管与整个栅极结构都用统一的极性掺杂的对应的晶体管相比，具有改善的(提高的)Vt和较低的阈下泄漏(subthreshold leakage)。
第一和第二注入132和140的注入剂量应当分别足以实现延伸部膜124的高度掺杂的第一和第二部分136和142。在一个实施例中，第一注入132是p型注入，第二注入140是n型注入，注入的理想剂量是超过大约1013个离子每平方厘米。注入能量最好足以实现接近延伸部膜124的中心的峰值剂量。用于p型(硼)注入的代表性注入能量在大约10到100keV的范围内，而n型(磷)注入在大约30到100keV的范围内。在另外的实施例中，可以使用另外的或者备选的注入技术，比如等离子体注入和阻挡层(用于细调现有的注入)。
现在看图8，已经对图7中的导电延伸部膜124进行了各向异性蚀刻，以分别产生第一和第二导电延伸部隔离结构146和150。如图8所示，导电延伸部隔离体146和150通过电介质120和104与栅电极116和衬底102电隔离。在一个实施例中，延伸部隔离体146和150的横向厚度大约是栅电极116的横向尺度(L)的1/4到1/2。例如，如果栅电极116的长度L为大约100nm，则延伸部隔离体146和150的横向厚度单独地或者加起来在大约25到50nm的范围内。在另外的实施例中，延伸部隔离体146和150的横向尺度可以在该范围之外。
现在看图9和图10，淀积并蚀刻电介质隔离膜158，以在延伸部隔离体146和150的外侧壁上形成电介质隔离体162。隔离膜158可以是CVD氧化硅、氮化硅或者二者的组合。隔离体结构162有益地防止了所得到的晶体管的源/漏区和栅电极之间的短路。具体地，一种工艺实施例使用硅化物工序短接延伸部隔离体146和150与栅电极116。在该实施例中，隔离体结构162防止硅化物将源/漏区短接到延伸部。
现在看图11，使用栅电极116、延伸部隔离体146和150以及电介质隔离体162作为注入掩模进行源/漏注入154以向衬底102中引入源/漏杂质分布(区)156，使得源/漏区156自对准到隔离体162，并且，由于隔离体162最好相对较薄和均匀，源/漏区156被有效地自对准到延伸部隔离体146和150。在另一个实施例中，在形成电介质隔离体162之前进行注入154，从而将源/漏区156直接自对准到延伸部隔离体146和150。在上面的任一实施例中，将源/漏区156对准到延伸部隔离体146和150。在一种n沟道晶体管实施例中，源/漏注入使用n型物质比如磷或者砷，而在p沟道晶体管实施例中，源/漏注入154使用硼或者另一种p型掺杂剂。杂质分布156最好超过大约1019个原子每平方厘米。
现在看图12和图13，使用硅化物工艺将延伸部隔离体146和150电连接到栅电极116。在图12中，在晶片100上均匀地淀积金属166比如钴。在该淀积之前，清除源/漏区156上的电介质包括电介质膜120以及在栅电极116的上表面上的任何残留电介质，以暴露出衬底102内的掺杂半导体以及多晶硅或者栅电极116的其它材料。在要被清除的电介质包括氧化硅的情况下，可以使用HF浸蚀或者其它合适的湿法工艺，而氮化硅以及其它的电介质可以使用传统的干法蚀刻工艺。
在淀积金属166之后，将晶片100和金属166暴露于加热环境170，以在任何金属166接触硅(或者其它半导体)的地方形成硅化物。金属166与电介质接触的部分，比如隔离体162，在所述热处理步骤之后仍然没有反应，从而，如图13所示，使得未反应的部分能够被选择性地除去。该硅化物工艺产生将第一和第二延伸部隔离体146和156电连接到栅电极116的导电桥174。除了钴之外或者代替钴，金属166可以包括诸如镍、钛、氮化钛等材料或者它们的组合。
所得到的如图13所示的晶体管110包括一个三部分的偏压结构，其包括栅电极116，以及第一和第二导电延伸部隔离体146和150，其中每一个都隔着居间的电介质位于下伏衬底102上方并与之隔离。电介质120介于延伸部隔离体146和150以及栅电极116的侧壁之间。衬底内的源/漏区156在延伸部隔离体146和150所限定的沟道区111的任一侧。施加给延伸部隔离体146和150以及栅电极116的电压调制沟道区111的导电性。
在优选实施例中，偏压结构的部件的极性或者掺杂类型是可以独立地变化。这样，偏压结构的三个部件中的每一个可以是n型、p型或者本征的。由于与不同导电类型相关的功函数差异，施加给栅结构的三个部分中的每一个的公共电压会对下伏的沟道111具有不同的调制效果。
在一个实施例中，在第一延伸部隔离体146下方的区域156被用作晶体管的漏极。在该实施例中，第一延伸部隔离体146被进行p型掺杂，而栅电极116和第二延伸部隔离体150都被进行n型掺杂。这种配置有益地在漏极附近产生了能带间隙峰。这有效地升高了晶体管的阈电压，降低了短沟道效应(短通道效应，short channel effects)，包括阈下泄漏和DIBL(drain induced barrier leakage，漏极导致的势垒泄漏)。
现在看图14，其中图示了用于接触延伸部隔离体146和150并对之施加偏压的另一种装置。不同于上面参照图12和13所述的使用硅化物工艺将延伸部隔离体146和150桥接到栅电极116，这里使用接触体180和184来将延伸部隔离体146和150分别连接到衬底102的p+部分和n+部分。在该实施例中，使用非关键性的掩模和蚀刻工序来形成空隙186，将延伸部结构“分”成两个电隔离的部分。该实施例使得能够对晶体管的偏压结构的各部件独立进行偏压，这对特定应用中控制阈电压是有好处的。
这样，对于阅读了本说明书的本领域普通技术人员来说，本发明显然提供了一种能够能够实现前述优点的制造集成电路的工艺。尽管上面对本发明的说明和图解是针对特定的说明性实施例的，但是不是要将本发明局限于这些说明性的实施例。本领域的普通技术人员会认识到，在不偏离本发明的实质精神的前提下，可以作各种变化和修改。因此，本发明应当包括落在所附权利要求及其等效方案范围内的所有这样的变化和修改。

Claims (20)

1.一种形成晶体管的方法，包括：
在半导体衬底上的栅极电介质上形成栅电极；
与所述栅电极的第一和第二侧壁分别相邻地形成导电的第一和第二延伸部隔离体，在每一个延伸部隔离体及其相应的栅电极侧壁之间设有电介质；
使用第一物质对第一延伸部隔离体掺杂，使用第二物质对第二延伸部隔离体掺杂，其中，第一和第二延伸部隔离体的极性相反；以及
在衬底中形成与延伸部隔离体对准的源/漏区。
2.如权利要求1所述的方法，还包括：使用硅化物将所述栅电极与第一和第二导电延伸部电桥接起来。
3.如权利要求1所述的方法，还包括：使第一延伸部隔离体与衬底的第一部分电接触，使第二延伸部隔离体与衬底的第二部分电接触，从而允许对第一和第二延伸部隔离体独立施加偏压。
4.如权利要求1所述的方法，还包括：在形成所述延伸部隔离体之前，形成与所述栅电极自对准的延伸部注入区。
5.如权利要求1所述的方法，其中，对第一延伸部隔离体掺杂的步骤包括：在将衬底保持在6度到60度范围内的注入角度的同时离子注入第一掺杂剂；对第二延伸部隔离体掺杂的步骤包括：在将衬底保持在-6度到-60度范围内的注入角度的同时离子注入第二掺杂剂。
6.如权利要求1所述的方法，其中，形成所述延伸部隔离体的步骤包括：在衬底和栅电极上淀积导电延伸部隔离体膜，并对延伸部隔离体膜进行各向异性蚀刻。
7.如权利要求6所述的方法，其中，在淀积所述延伸部隔离体膜之后、蚀刻所述膜之前执行对第一延伸部隔离体和第二延伸部隔离体的掺杂。
8.如权利要求6所述的方法，其中，在蚀刻所述延伸部隔离体膜之后执行对第一延伸部隔离体和第二延伸部隔离体的掺杂。
9.如权利要求1所述的方法，其中，形成栅电极的步骤的特征还在于形成n型栅电极；
形成第一延伸部隔离体的步骤的特征还在于形成n型延伸部隔离体；以及
形成第二延伸部隔离体的步骤的特征还在于形成p型延伸部隔离体。
10.一种集成电路中的晶体管，包括：
在衬底上的栅极电介质上的栅电极；
与所述栅电极的相应侧壁分别相邻的第一和第二导电延伸部隔离体，在每一个延伸部隔离体及其相应的栅电极侧壁之间有延伸部电介质，其中，所述栅电极、第一延伸部隔离体和第二延伸部隔离体中的至少一个具有第一导电类型、至少一个具有第二导电类型；以及
所述衬底中的与所述延伸部隔离体对准的源/漏杂质区，从而在所述栅电极和所述第一和第二延伸部隔离体下方形成沟道区。
11.如权利要求10所述的晶体管，其中，第一延伸部隔离体和栅电极具有第一导电类型，第二电极具有不同于第一导电类型的第二导电类型。
12.如权利要求11所述的晶体管，其中，第一延伸部隔离体和栅电极为n型，第二延伸部隔离体为p型，源/漏区为n型。
13.如权利要求12所述的晶体管，其中，邻近第二延伸部隔离体的源/漏区进一步作为漏区。
14.如权利要求10所述的晶体管，还包括将第一延伸部栅极、栅电极和第二电极桥接起来的导电硅化物。
15.如权利要求10所述的晶体管，其中，所述第一延伸部隔离体电接触衬底的n+部分，第二延伸部隔离体接触衬底的p+部分，从而允许对第一和第二延伸部隔离体独立地施加偏压。
16.一种半导体制造方法，包括：
与形成在半导体衬底上的栅电极的相应侧壁相邻地形成第一和第二导电延伸部隔离体，该栅电极具有第一种导电类型；
用第一导电类型的杂质对第一导电隔离体掺杂，用第二导电类型的杂质对第二导电隔离体掺杂；
在衬底中与第一和第二延伸部隔离体横向对准地形成源/漏区，所述源/漏区限定了它们之间的沟道区，其中，该沟道区被施加给栅电极、第一延伸部隔离体或者第二延伸部隔离体的电压所调制。
17.如权利要求16所述的方法，其中，所述栅电极、第一延伸部隔离体和第二延伸部隔离体包括多晶硅。
18.如权利要求16所述的方法，其中，对第一延伸部隔离体掺杂的步骤包括用第一注入角度的第一注入对延伸部隔离体膜进行注入，对第二延伸部隔离体掺杂的步骤包括用第二注入角度的第二注入对延伸部隔离体膜进行注入。
19.如权利要求16所述的方法，还包括使用导电硅化物桥接第一延伸部隔离体、栅电极和第二延伸部隔离体。
20.如权利要求16所述的方法，还包括将第一延伸部隔离体电连接到衬底的第一部分，将第二延伸部隔离体电连接到衬底的第二部分，从而允许对延伸部隔离体独立地施以偏压。
CNB200480011412XA 2003-04-30 2004-04-30 使用非对称导电隔离体的半导体制造工艺 Expired - Fee Related CN100419974C (zh)

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US7109550B2 (en) 2006-09-19
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US7132704B2 (en) 2006-11-07
US6967143B2 (en) 2005-11-22
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