CN107452792A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

Info

Publication number
CN107452792A
CN107452792A CN201610379186.5A CN201610379186A CN107452792A CN 107452792 A CN107452792 A CN 107452792A CN 201610379186 A CN201610379186 A CN 201610379186A CN 107452792 A CN107452792 A CN 107452792A
Authority
CN
China
Prior art keywords
semiconductor fin
semiconductor
grid
fin
threshold voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201610379186.5A
Other languages
English (en)
Inventor
周飞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201610379186.5A priority Critical patent/CN107452792A/zh
Priority to US15/603,768 priority patent/US10026841B2/en
Priority to EP17173744.8A priority patent/EP3252828A1/en
Publication of CN107452792A publication Critical patent/CN107452792A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
    • H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明公开了一种半导体装置及其制造方法，涉及半导体技术领域。其中，所述方法包括：提供衬底结构，所述衬底结构包括：半导体衬底、在所述半导体衬底上的半导体鳍片、在半导体鳍片两侧的隔离区、在半导体鳍片位于隔离区以上的表面上的栅极电介质层；在所述栅极电介质层的一部分上的栅极；对所述半导体鳍片未被栅极覆盖的部分进行阈值电压调整离子注入，以使得注入的杂质扩散到所述半导体鳍片被栅极覆盖的部分。本发明可以降低阈值电压调整离子注入所注入杂质的损失。

Description

半导体装置及其制造方法
技术领域
本发明涉及半导体技术领域，尤其涉及一种半导体装置及其制造方法。
背景技术
随着MOSFET(Metal Oxide Semiconductor Field EffectTransistor，金属氧化物半导体场效应晶体管)关键尺寸的缩小，SCE(Short Channel Effect，短沟道效应)成为一个至关重要的问题。FinFET(Fin Field Effect Transistor，鳍式场效应晶体管)器件具有良好的栅控能力，能够有效地抑制短沟道效应。因此，在小尺寸的半导体元件设计中通常采用FinFET器件。
但是，对于FinFET器件来说，阈值电压(VT)调整离子注入是一个挑战。现有的方案中，在鳍片形成之后对鳍片进行阈值电压调整离子注入，在阈值电压调整离子注入后进行氧化工艺以在鳍片表面形成氧化层。本公开的发明人发现，现有的方案会导致阈值电压调整离子注入所注入的杂质的损失，从而不能将阈值电压调整到期望的阈值电压。
发明内容
本公开的一个实施例的目的在于提出一种新颖的半导体装置的制造方法，能够降低阈值电压调整离子注入所注入的杂质的损失。
根据本公开的一个实施例，提供了一种半导体装置的制造方法，包括：提供衬底结构，所述衬底结构包括：半导体衬底、在所述半导体衬底上的半导体鳍片、在半导体鳍片两侧的隔离区、在半导体鳍片位于隔离区以上的表面上的栅极电介质层；在所述栅极电介质层的一部分上的栅极；对所述半导体鳍片未被栅极覆盖的部分进行阈值电压调整离子注入，以使得注入的杂质扩散到所述半导体鳍片被栅极覆盖的部分。
在一个实施例中，所述阈值电压调整离子注入的离子注入方向与所述半导体鳍片的上表面的法线之间的夹角为10-20度。
在一个实施例中，所述阈值电压调整离子注入的离子注入方向与垂直于所述半导体鳍片的侧面的面基本平行。
在一个实施例中，所述阈值电压调整离子注入的注入条件包括：注入离子为硼离子、注入能量为0.5-5Kev，注入剂量为1×1013/cm2至1×1014/cm2。
在一个实施例中，所述阈值电压调整离子注入的注入条件包括：注入离子为砷离子、注入能量为1-10Kev，注入剂量为5×1012/cm2至5×1013/cm2。
在一个实施例中，所述方法还包括：在所述栅极的侧面形成侧壁间隔物。
在一个实施例中，所述方法还包括：以所述侧壁间隔物为掩模对所述半导体鳍片未被栅极覆盖的部分进行漏极轻掺杂LDD离子注入。
在一个实施例中，所述阈值电压调整离子注入的注入剂量小于所述LDD离子注入的注入剂量。
在一个实施例中，LDD离子注入的注入剂量为5×1014/cm2至1×1015/cm2。
在一个实施例中，所述方法还包括：对所述半导体鳍片未被栅极覆盖的部分进行刻蚀以形成凹陷；在形成的凹陷中外延生长半导体材料以形成源区和漏区。
在一个实施例中，所述栅极上具有硬掩模；所述方法还包括：在形成源区和漏区后，去除所述栅极上的硬掩模。
在一个实施例中，所述半导体材料包括：SiGe、SiC或Si。
在一个实施例中，所述提供衬底结构的步骤包括：提供半导体衬底；在所述半导体衬底上形成半导体鳍片；在所述半导体鳍片两侧的半导体衬底上形成隔离区；在半导体鳍片位于隔离区以上的部分的表面上形成栅极电介质层；在所述栅极电介质层的一部分上形成栅极。
在一个实施例中，所述在所述半导体衬底上形成半导体鳍片的步骤包括：在所述半导体衬底上形成图案化的硬掩模；以所述图案化的硬掩模为掩模对所述半导体衬底进行刻蚀，从而形成半导体衬底和在所述半导体衬底上的半导体鳍片；所述方法还包括：在所述半导体鳍片两侧的半导体衬底上形成隔离区后，去除所述半导体鳍片上的硬掩模。
在一个实施例中，所述在所述半导体鳍片两侧的半导体衬底上形成隔离区包括：沉积隔离材料以填充半导体鳍片两侧的空间并覆盖半导体鳍片；对所述隔离材料进行平坦化；去除剩余的隔离材料的一部分以暴露半导体鳍片的一部分，从而形成所述隔离区。
在一个实施例中，所述方法还包括：在沉积隔离材料之前，在所述半导体衬底和半导体鳍片的表面形成衬垫层；在去除剩余的隔离材料的一部分时，还去除剩余的隔离材料的所述一部分的两侧的衬垫层，以暴露半导体鳍片的一部分。
在一个实施例中，所述半导体鳍片的材料为硅；所述在半导体鳍片位于隔离区以上的部分的表面上形成栅极电介质层包括：对半导体鳍片位于隔离区以上的部分的表面进行氧化，以形成硅的氧化物作为所述栅极电介质层。
根据本公开的另一个实施例，提供了一种半导体装置，包括：半导体衬底；在所述半导体衬底上的半导体鳍片；在半导体鳍片两侧的隔离区；在半导体鳍片位于隔离区以上的部分的表面上的栅极电介质层；在所述栅极电介质层的一部分上的栅极；第一杂质区，位于所述半导体鳍片未被栅极覆盖的部分中；第二杂质区，位于所述半导体鳍片被栅极覆盖的部分中；其中，所述第一杂质区是在形成栅极后通过对所述半导体鳍片未被栅极覆盖的部分进行阈值电压调整离子注入形成的；所述第二杂质区是所述阈值电压调整离子注入所注入的杂质扩散到所述半导体鳍片被栅极覆盖的部分中而形成的。
在一个实施例中，所述栅极电介质层中包括所述阈值电压调整离子注入所注入的杂质。
在一个实施例中，所述装置还包括：位于所述半导体鳍片未被栅极覆盖的部分中的源区和漏区。
通过以下参照附图对本公开的示例性实施例的详细描述，本公开的其它特征、方面及其优点将会变得清楚。
附图说明
附图构成本说明书的一部分，其描述了本公开的示例性实施例，并且连同说明书一起用于解释本发明的原理，在附图中：
图1是根据本公开一个实施例的半导体装置的制造方法的流程图；
图2A示出了根据本公开一个实施例的衬底结构的立体示意图；
图2B示出了根据本公开一个实施例的进行阈值电压调整离子注入的立体示意图；
图3示出了根据本公开一个实施例的形成衬底结构的一个阶段的截面示意图；
图4示出了根据本公开一个实施例的形成衬底结构的一个阶段的截面示意图；
图5示出了根据本公开一个实施例的形成衬底结构的一个阶段的截面示意图；
图6A示出了根据本公开一个实施例的形成衬底结构的一个阶段的沿着垂直沟道方向的截面示意图；图6B示出了图6A所示阶段的沿着沟道方向的截面示意图；
图7示出了根据本公开一个实施例的形成衬底结构的一个阶段的截面示意图；
图8是根据本公开另一个实施例的半导体装置的制造方法的流程图；
图9示出了根据本公开另一个实施例的半导体装置的制造方法的一个阶段的截面示意图；
图10示出了根据本公开另一个实施例的半导体装置的制造方法的一个阶段的截面示意图；
图11示出了根据本公开另一个实施例的半导体装置的制造方法的一个阶段的截面示意图。
具体实施方式
现在将参照附图来详细描述本公开的各种示例性实施例。应理解，除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不应被理解为对本发明范围的限制。
此外，应当理解，为了便于描述，附图中所示出的各个部件的尺寸并不必然按照实际的比例关系绘制，例如某些层的厚度或宽度可以相对于其他层有所夸大。
以下对示例性实施例的描述仅仅是说明性的，在任何意义上都不作为对本发明及其应用或使用的任何限制。
对于相关领域普通技术人员已知的技术、方法和装置可能不作详细讨论，但在适用这些技术、方法和装置情况下，这些技术、方法和装置应当被视为本说明书的一部分。
应注意，相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义或说明，则在随后的附图的说明中将不需要对其进行进一步讨论。
本公开的发明人对阈值电压离子注入所注入的杂质损失的问题进行了研究，发现：阈值电压离子注入所注入的杂质分布在鳍片接近表面的位置处，在阈值电压调整离子注入后还需要进行氧化工艺以在鳍片表面形成氧化层作为栅极电介质层，由于注入的杂质在氧化层中的固溶度高于在鳍片中的固溶度，从而注入的杂质在氧化工艺中会很容易扩散到所形成的氧化层中，使得阈值电压离子注入所注入的杂质造成损失。据此，发明人提出了如下技术方案。
图1是根据本公开一个实施例的半导体装置的制造方法的流程图。如图1所示，该方法包括如下步骤：
首先，在步骤101，提供衬底结构。
图2A示出了根据本公开一个实施例的衬底结构的立体示意图。如图2A所示，该衬底结构包括：半导体衬底201、在半导体衬底201上的半导体鳍片202，在半导体鳍片两侧的隔离区203、在半导体鳍片位于隔离区203以上的表面上的栅极电介质层204和在栅极电介质层204的一部分上的栅极205。
然后，在步骤103，对半导体鳍片202未被栅极205覆盖的部分进行阈值电压调整离子注入，以使得注入的杂质扩散到半导体鳍片202被栅极205覆盖的部分，如图2B所示。在进行阈值电压调整离子注入后，所注入的杂质会横向扩散，从而进入半导体鳍片202被栅极205覆盖的部分，也即沟道区中，以便调整装置的阈值电压。
本实施例中，由于阈值电压调整离子注入是在栅极电介质层之后形成的，因此，在阈值电压调整离子注入后不需要再进行氧化工艺来形成栅极电介质层，从而降低了阈值电压调整离子注入所注入杂质的损失。
在一个实施例中，上述阈值电压调整离子注入的离子注入方向与半导体鳍片202的上表面的法线之间的夹角可以为10-20度，例如15度。进一步地，在一个实施例中，阈值电压调整离子注入的离子注入方向可以与垂直于半导体鳍片202的侧面的面基本平行。也即，与半导体鳍片垂直于沟道方向的截面基本平行。
应理解，本文中，半导体鳍片的表面包括上表面和两个侧面。还应理解，术语“基本平行”是指在半导体工艺偏差范围内的平行。
对于NMOS器件和PMOS器件来说，阈值电压调整离子注入的注入条件有所不同。在一个实施例中，半导体装置可以包括NMOS器件，用于NMOS器件的阈值电压调整离子注入的注入条件可以包括：注入离子为硼离子、注入能量为0.5-5Kev，注入剂量为1×1013/cm2至1×1014/cm2。在另一个实施例中，半导体装置可以包括PMOS器件，用于PMOS器件的阈值电压调整离子注入的注入条件可以包括：注入离子为砷离子、注入能量为1-10Kev，注入剂量为5×1012/cm2至5×1013/cm2。
图3至图7示出了根据本公开一个实施例的形成衬底结构的各个阶段的截面示意图。下面结合图3-图7对形成衬底结构的过程进行说明。
首先，如图3所示，提供半导体衬底201并在半导体衬底201上形成半导体鳍片202。这里，半导体衬底201例如可以是诸如硅衬底、锗衬底的元素半导体衬底，或者可以是诸如砷化镓的化合物半导体衬底。然而，本公开并不限于此。在一个实现方式中，可以根据如下方式来形成半导体鳍片202：首先，在半导体衬底201上形成图案化的硬掩模206，该硬掩模例如可以是硅的氮化物、硅的氧化物、硅的氮氧化物等等。在某些实现方式中，在半导体衬底201与硬掩模206之间还形成有缓冲层，例如硅的氧化物。该缓冲层的存在有利于硬掩模与半导体衬底之间的结合。之后，以图案化的硬掩模206为掩模对半导体衬底201进行刻蚀，从而在半导体衬底201上形成半导体鳍片202。
然后，如图4所示，在半导体鳍片202两侧的半导体衬底201上形成隔离区203。在一个实现方式中，可以通过如下方式来形成隔离区：
首先，沉积隔离材料以填充半导体鳍片两侧的空间并覆盖半导体鳍片。例如，可以通过流式化学气相沉积(Flowable Chemical VapourDeposition,FCVD)技术来沉积隔离材料(例如电介质材料)。这里，在半导体鳍片上具有硬掩模的情况下，所沉积的隔离材料填充半导体鳍片两侧的空间并覆盖半导体鳍片上的硬掩模。在一个实施例中，在沉积隔离材料之前，可以在半导体衬底和半导体鳍片的表面形成衬垫层(例如，通过热氧化形成薄的氧化硅层)，以修复在刻蚀形成半导体鳍片时对半导体衬底和半导体鳍片造成的表面损伤。
然后，对隔离材料进行平坦化。例如，可以对隔离材料进行化学机械抛光，以使隔离材料的顶表面与半导体鳍片的顶表面基本齐平。这里，在半导体鳍片上具有硬掩模的情况下，对隔离材料进行平坦化时也可以去除半导体鳍片上的硬掩模，从而使隔离材料的顶表面与半导体鳍片的顶表面基本齐平。
之后，去除剩余的隔离材料的一部分以暴露各半导体鳍片的一部分，从而形成隔离区。这里，在半导体衬底和半导体鳍片的表面形成衬垫层的情况下，在去除剩余的隔离材料的一部分时，还去除剩余的隔离材料的一部分的两侧的衬垫层，以暴露半导体鳍片的一部分。
如上所述，在半导体鳍片202上具有硬掩模206的情况下，可以在对隔离材料进行平坦化的过程中去除硬掩模206；或者在形成隔离区203后通过额外的步骤来去除硬掩模206，从而形成如图5所示的结构。
接下来，如图6A和6B所示，在半导体鳍片202位于隔离区203以上的部分的表面上形成栅极电介质层204。在一个实施例中，半导体鳍片的材料可以为硅；这种情况下，可以对半导体鳍片位于隔离区以上的部分的表面进行氧化，以形成硅的氧化物作为栅极电介质层。
然后，如图7所示，在栅极电介质层204的一部分上形成栅极205，从而形成了图2A所示的衬底结构。这里，栅极205例如可以是多晶硅栅极。在一个实施例中，栅极205上可以具有硬掩模207；在后续形成源区和漏区后，可以去除栅极205上的硬掩模207。
图8是根据本公开另一个实施例的半导体装置的制造方法的流程图。其中，步骤801和步骤803的具体实现可以参见前面对步骤101和步骤103的描述，在此不再赘述。图8所示的半导体装置的制造方法还包括：
步骤805，在栅极205的侧面形成侧壁间隔物901，如图9所示。侧壁间隔物901可以是偏移间隔物(offset spacer)，例如氧化层等。这里，在栅极205上具有硬掩模207的情况下，侧壁间隔物901还形成在硬掩模207的侧面。
步骤807，以侧壁间隔物901为掩模对半导体鳍片未被栅极覆盖的部分进行漏极轻掺杂(LDD)离子注入，如图10所示。在一个实施例中，阈值电压调整离子注入的注入剂量小于LDD离子注入的注入剂量，从而使得阈值电压调整离子注入所注入的杂质不会对LDD区的电阻造成影响。作为一个示例，LDD离子注入的注入剂量可以为5×1014/cm2至1×1015/cm2。对于NMOS器件来说，LDD离子注入的离子可以是砷离子；对于PMOS器件来说，LDD离子注入的离子可以是BF2 +。
步骤809，对半导体鳍片未被栅极覆盖的部分进行刻蚀以形成凹陷。
步骤811，在形成的凹陷中外延生长半导体材料以形成源区1101和漏区1102，如图11所示。外延生长的半导体材料可以向沟道区引入应力，从而提高载流子的迁移率。在一个实施例中，对于NMOS器件来说，外延生长的半导体材料可以包括SiC或Si；对于PMOS器件来说，外延生长的半导体材料可以包括SiGe。
需要指出的是，在其他的一些实施例中，半导体装置的制造方法也可以仅包括图8所示的步骤801至步骤805，或者，包括图8所示的步骤801至步骤807。
本公开还提供了一种半导体装置，参见图2B，该半导体装置包括：半导体衬底201；在半导体衬底上的半导体鳍片202；在半导体鳍片两侧的隔离区203；在半导体鳍片位于隔离区以上的部分的表面上的栅极电介质层204；以及在栅极电介质层204的一部分上的栅极205。
该半导体装置还包括第一杂质区和第二杂质区(图中未示出)，其中：第一杂质区位于半导体鳍片未被栅极覆盖的部分中；第二杂质区位于半导体鳍片被栅极覆盖的部分中。第一杂质区是在形成栅极后通过对半导体鳍片未被栅极覆盖的部分进行阈值电压调整离子注入形成的；第二杂质区是阈值电压调整离子注入所注入的杂质扩散到半导体鳍片被栅极覆盖的部分中而形成的。
在一个实施例中，栅极电介质层204中包括阈值电压调整离子注入所注入的杂质。
在一个实施例中，参见图11，半导体装置还可以包括：位于半导体鳍片未被栅极覆盖的部分中的源区1101和漏区1102。
至此，已经详细描述了根据本公开实施例的半导体装置及其制造方法。为了避免遮蔽本公开的构思，没有描述本领域所公知的一些细节，本领域技术人员根据上面的描述，完全可以明白如何实施这里公开的技术方案。另外，本说明书公开所教导的各实施例可以自由组合。本领域的技术人员应该理解，可以对上面说明的实施例进行多种修改而不脱离如所附权利要求限定的本公开的精神和范围。

Claims (20)

1.一种半导体装置的制造方法，其特征在于，包括：
提供衬底结构，所述衬底结构包括：半导体衬底、在所述半导体衬底上的半导体鳍片、在半导体鳍片两侧的隔离区、在半导体鳍片位于隔离区以上的表面上的栅极电介质层；在所述栅极电介质层的一部分上的栅极；
对所述半导体鳍片未被栅极覆盖的部分进行阈值电压调整离子注入，以使得注入的杂质扩散到所述半导体鳍片被栅极覆盖的部分。
2.根据权利要求1所述的方法，其特征在于，
所述阈值电压调整离子注入的离子注入方向与所述半导体鳍片的上表面的法线之间的夹角为10-20度。
3.根据权利要求2所述的方法，其特征在于，
所述阈值电压调整离子注入的离子注入方向与垂直于所述半导体鳍片的侧面的面基本平行。
4.根据权利要求1所述的方法，其特征在于，
所述阈值电压调整离子注入的注入条件包括：注入离子为硼离子、注入能量为0.5-5Kev，注入剂量为1×1013/cm2至1×1014/cm2。
5.根据权利要求1所述的方法，其特征在于，
所述阈值电压调整离子注入的注入条件包括：注入离子为砷离子、注入能量为1-10Kev，注入剂量为5×1012/cm2至5×1013/cm2。
6.根据权利要求1所述的方法，其特征在于，还包括：
在所述栅极的侧面形成侧壁间隔物。
7.根据权利要求6所述的方法，其特征在于，还包括：
以所述侧壁间隔物为掩模对所述半导体鳍片未被栅极覆盖的部分进行漏极轻掺杂LDD离子注入。
8.根据权利要求7所述的方法，其特征在于，所述阈值电压调整离子注入的注入剂量小于所述LDD离子注入的注入剂量。
9.根据权利要求7所述的方法，其特征在于，LDD离子注入的注入剂量为5×1014/cm2至1×1015/cm2。
10.根据权利要求6所述的方法，其特征在于，还包括：
对所述半导体鳍片未被栅极覆盖的部分进行刻蚀以形成凹陷；
在形成的凹陷中外延生长半导体材料以形成源区和漏区。
11.根据权利要求10所述的方法，其特征在于，所述栅极上具有硬掩模；
所述方法还包括：
在形成源区和漏区后，去除所述栅极上的硬掩模。
12.根据权利要求10所述的方法，其特征在于，所述半导体材料包括：SiGe、SiC或Si。
13.根据权利要求1所述的方法，其特征在于，所述提供衬底结构的步骤包括：
提供半导体衬底；
在所述半导体衬底上形成半导体鳍片；
在所述半导体鳍片两侧的半导体衬底上形成隔离区；
在半导体鳍片位于隔离区以上的部分的表面上形成栅极电介质层；
在所述栅极电介质层的一部分上形成栅极。
14.根据权利要求13所述的方法，其特征在于，所述在所述半导体衬底上形成半导体鳍片的步骤包括：
在所述半导体衬底上形成图案化的硬掩模；
以所述图案化的硬掩模为掩模对所述半导体衬底进行刻蚀，从而形成半导体衬底和在所述半导体衬底上的半导体鳍片；
所述方法还包括：
在所述半导体鳍片两侧的半导体衬底上形成隔离区后，去除所述半导体鳍片上的硬掩模。
15.根据权利要求13所述的方法，其特征在于，所述在所述半导体鳍片两侧的半导体衬底上形成隔离区包括：
沉积隔离材料以填充半导体鳍片两侧的空间并覆盖半导体鳍片；
对所述隔离材料进行平坦化；
去除剩余的隔离材料的一部分以暴露半导体鳍片的一部分，从而形成所述隔离区。
16.根据权利要求15所述的方法，其特征在于，还包括：
在沉积隔离材料之前，在所述半导体衬底和半导体鳍片的表面形成衬垫层；
在去除剩余的隔离材料的一部分时，还去除剩余的隔离材料的所述一部分的两侧的衬垫层，以暴露半导体鳍片的一部分。
17.根据权利要求13所述的方法，其特征在于，所述半导体鳍片的材料为硅；
所述在半导体鳍片位于隔离区以上的部分的表面上形成栅极电介质层包括：
对半导体鳍片位于隔离区以上的部分的表面进行氧化，以形成硅的氧化物作为所述栅极电介质层。
18.一种半导体装置，其特征在于，包括：
半导体衬底；
在所述半导体衬底上的半导体鳍片；
在半导体鳍片两侧的隔离区；
在半导体鳍片位于隔离区以上的部分的表面上的栅极电介质层；
在所述栅极电介质层的一部分上的栅极；
第一杂质区，位于所述半导体鳍片未被栅极覆盖的部分中；
第二杂质区，位于所述半导体鳍片被栅极覆盖的部分中；
其中，所述第一杂质区是在形成栅极后通过对所述半导体鳍片未被栅极覆盖的部分进行阈值电压调整离子注入形成的；
所述第二杂质区是所述阈值电压调整离子注入所注入的杂质扩散到所述半导体鳍片被栅极覆盖的部分中而形成的。
19.根据权利要求18所述的装置，其特征在于，
所述栅极电介质层中包括所述阈值电压调整离子注入所注入的杂质。
20.根据权利要求18所述的装置，其特征在于，还包括：
位于所述半导体鳍片未被栅极覆盖的部分中的源区和漏区。
CN201610379186.5A 2016-06-01 2016-06-01 半导体装置及其制造方法 Pending CN107452792A (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201610379186.5A CN107452792A (zh) 2016-06-01 2016-06-01 半导体装置及其制造方法
US15/603,768 US10026841B2 (en) 2016-06-01 2017-05-24 Semiconductor device and manufacturing method therefor
EP17173744.8A EP3252828A1 (en) 2016-06-01 2017-05-31 Semiconductor device and manufacturing method therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610379186.5A CN107452792A (zh) 2016-06-01 2016-06-01 半导体装置及其制造方法

Publications (1)

Publication Number Publication Date
CN107452792A true CN107452792A (zh) 2017-12-08

Family

ID=59053897

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610379186.5A Pending CN107452792A (zh) 2016-06-01 2016-06-01 半导体装置及其制造方法

Country Status (3)

Country Link
US (1) US10026841B2 (zh)
EP (1) EP3252828A1 (zh)
CN (1) CN107452792A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110047755A (zh) * 2018-01-17 2019-07-23 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110571154B (zh) * 2018-06-05 2023-10-10 中芯国际集成电路制造(上海)有限公司 半导体器件的制造方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW319902B (en) * 1996-09-23 1997-11-11 Mos Electronics Taiwan Inc Manufacturing method of short channel metal oxide semiconductor device
US20020033511A1 (en) * 2000-09-15 2002-03-21 Babcock Jeffrey A. Advanced CMOS using super steep retrograde wells
CN101783299A (zh) * 2009-01-20 2010-07-21 中芯国际集成电路制造(上海)有限公司 Mos晶体管的形成方法及其阈值电压调节方法
US20140187013A1 (en) * 2012-12-28 2014-07-03 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for Forming FinFETs Having Multiple Threshold Voltages
US20140273380A1 (en) * 2013-03-13 2014-09-18 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with Regrown Source/Drain and Methods for Forming the Same
CN105702582A (zh) * 2014-11-27 2016-06-22 中芯国际集成电路制造(上海)有限公司 晶体管的形成方法
CN105990151A (zh) * 2015-03-04 2016-10-05 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制备方法、电子装置

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6967143B2 (en) * 2003-04-30 2005-11-22 Freescale Semiconductor, Inc. Semiconductor fabrication process with asymmetrical conductive spacers
US7214575B2 (en) * 2004-01-06 2007-05-08 Micron Technology, Inc. Method and apparatus providing CMOS imager device pixel with transistor having lower threshold voltage than other imager device transistors
US6872640B1 (en) * 2004-03-16 2005-03-29 Micron Technology, Inc. SOI CMOS device with reduced DIBL
US20060094194A1 (en) * 2004-11-04 2006-05-04 Taiwan Semiconductor Manufacturing Company, Ltd. Advanced disposable spacer process by low-temperature high-stress nitride film for sub-90NM CMOS technology
US7952149B2 (en) * 2005-05-12 2011-05-31 International Business Machines Corporation Anti-halo compensation
KR100668748B1 (ko) * 2005-06-29 2007-01-29 주식회사 하이닉스반도체 게이트-관통 이온주입을 이용한 반도체소자의 제조방법
US7531423B2 (en) * 2005-12-22 2009-05-12 International Business Machines Corporation Reduced-resistance finFETs by sidewall silicidation and methods of manufacturing the same
KR100751803B1 (ko) * 2006-08-22 2007-08-23 삼성전자주식회사 반도체 소자의 제조 방법
US8067803B2 (en) * 2008-10-16 2011-11-29 Micron Technology, Inc. Memory devices, transistor devices and related methods
US8319311B2 (en) * 2009-03-16 2012-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid STI gap-filling approach
US8395191B2 (en) * 2009-10-12 2013-03-12 Monolithic 3D Inc. Semiconductor device and structure
US9953885B2 (en) * 2009-10-27 2018-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. STI shape near fin bottom of Si fin in bulk FinFET
US8778767B2 (en) * 2010-11-18 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuits and fabrication methods thereof
US8772118B2 (en) * 2011-07-08 2014-07-08 Texas Instruments Incorporated Offset screen for shallow source/drain extension implants, and processes and integrated circuits
US8803242B2 (en) * 2011-09-19 2014-08-12 Eta Semiconductor Inc. High mobility enhancement mode FET
US8853761B2 (en) * 2012-01-30 2014-10-07 Synopsys, Inc. Asymmetric dense floating gate nonvolatile memory with decoupled capacitor
US8828813B2 (en) * 2012-04-13 2014-09-09 Taiwan Semiconductor Manufacturing Co., Ltd. Replacement channels
US8883570B2 (en) * 2012-07-03 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate FETs and methods for forming the same
US9093514B2 (en) * 2013-03-06 2015-07-28 Taiwan Semiconductor Manufacturing Co., Ltd. Strained and uniform doping technique for FINFETs
US9837416B2 (en) * 2015-07-31 2017-12-05 Taiwan Semiconductor Manufacturing Company Ltd. Multi-threshold voltage field effect transistor and manufacturing method thereof
US11049939B2 (en) * 2015-08-03 2021-06-29 Semiwise Limited Reduced local threshold voltage variation MOSFET using multiple layers of epi for improved device operation
US9520467B1 (en) * 2015-08-31 2016-12-13 Taiwan Semiconductor Manufacturing Company Ltd. Field effect transistor structure and manufacturing method thereof
US10644153B2 (en) * 2016-02-25 2020-05-05 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method for fabricating the same

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW319902B (en) * 1996-09-23 1997-11-11 Mos Electronics Taiwan Inc Manufacturing method of short channel metal oxide semiconductor device
US20020033511A1 (en) * 2000-09-15 2002-03-21 Babcock Jeffrey A. Advanced CMOS using super steep retrograde wells
CN101783299A (zh) * 2009-01-20 2010-07-21 中芯国际集成电路制造(上海)有限公司 Mos晶体管的形成方法及其阈值电压调节方法
US20140187013A1 (en) * 2012-12-28 2014-07-03 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for Forming FinFETs Having Multiple Threshold Voltages
US20140273380A1 (en) * 2013-03-13 2014-09-18 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with Regrown Source/Drain and Methods for Forming the Same
CN105702582A (zh) * 2014-11-27 2016-06-22 中芯国际集成电路制造(上海)有限公司 晶体管的形成方法
CN105990151A (zh) * 2015-03-04 2016-10-05 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制备方法、电子装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110047755A (zh) * 2018-01-17 2019-07-23 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
CN110047755B (zh) * 2018-01-17 2022-06-28 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法

Also Published As

Publication number Publication date
EP3252828A1 (en) 2017-12-06
US20170352758A1 (en) 2017-12-07
US10026841B2 (en) 2018-07-17

Similar Documents

Publication Publication Date Title
US11195931B2 (en) Gate structure, semiconductor device and the method of forming semiconductor device
US9263549B2 (en) Fin-FET transistor with punchthrough barrier and leakage protection regions
US8647929B2 (en) Semiconductor devices and methods of manufacturing thereof
US8802533B1 (en) Semiconductor device and method of manufacturing the same
US9230828B2 (en) Source and drain dislocation fabrication in FinFETs
US8361895B2 (en) Ultra-shallow junctions using atomic-layer doping
US20140015045A1 (en) Apparatus and Method for Power MOS Transistor
CN103426769B (zh) 半导体器件制造方法
CN103632973B (zh) 半导体器件及其制造方法
CN103426768B (zh) 半导体器件制造方法
US9263585B2 (en) Methods of forming enhanced mobility channel regions on 3D semiconductor devices, and devices comprising same
CN110047754A (zh) 半导体器件及其制造方法
CN110047908A (zh) 半导体器件及其制造方法
US8202782B2 (en) Method of manufacturing transistor
US20150270399A1 (en) Semiconductor structure and method for manufacturing the same
US10361305B2 (en) Semiconductor structure and fabrication method thereof
US9306001B1 (en) Uniformly doped leakage current stopper to counter under channel leakage currents in bulk FinFET devices
CN107452792A (zh) 半导体装置及其制造方法
US20130302954A1 (en) Methods of forming fins for a finfet device without performing a cmp process
CN106158641A (zh) finFET器件及其制作方法
CN103594374B (zh) 半导体器件制造方法
CN107437533B (zh) 半导体结构及其制造方法
US20180323300A1 (en) Finfet device and fabrication method thereof
CN104916540A (zh) 一种应变沟道晶体管及其制备方法
US9502561B1 (en) Semiconductor devices and methods of forming the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20171208

RJ01 Rejection of invention patent application after publication