CN1744296B - 在半导体存储器件中形成隔离层的方法 - Google Patents

在半导体存储器件中形成隔离层的方法 Download PDF

Info

Publication number
CN1744296B
CN1744296B CN2005100057782A CN200510005778A CN1744296B CN 1744296 B CN1744296 B CN 1744296B CN 2005100057782 A CN2005100057782 A CN 2005100057782A CN 200510005778 A CN200510005778 A CN 200510005778A CN 1744296 B CN1744296 B CN 1744296B
Authority
CN
China
Prior art keywords
cleaning
film
dhf
carry out
pad oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2005100057782A
Other languages
English (en)
Other versions
CN1744296A (zh
Inventor
李承撤
朴相昱
宋弼根
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of CN1744296A publication Critical patent/CN1744296A/zh
Application granted granted Critical
Publication of CN1744296B publication Critical patent/CN1744296B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Element Separation (AREA)

Abstract

本发明涉及一种形成半导体存储器件的隔离膜的方法。依据本发明，在形成隧道氧化膜之前所执行的预处理清洗工艺中，在60℃-70℃的温度范围内执行SC-1清洗工艺。因此，即使在SC-1清洗工艺和DHF清洗工艺中，也可使单元区域和周边区域中的氧化膜凹进。因而可减少DHF清洗时间。因此，本发明具有以下优点，即本发明可通过DHF使硅衬底的损失最小化，因而可控制沟的深度。

Description

在半导体存储器件中形成隔离层的方法
技术领域
本发明涉及一种用于形成半导体存储器件的隔离膜的方法。更具体而言，本发明涉及一种用于形成半导体存储器件的隔离膜的方法，其中当执行利用浅沟槽隔离(STI)形成半导体存储器件的隔离膜的工艺时，可缩短从形成沟槽的工艺至形成隔离膜的工艺所执行的使用DHF溶液的清洗工艺时间，从而使形成于隔离膜中的沟(moat)的深度最小化。 
背景技术
通常，在例如快闪存储器件的存储器件中，使用浅沟槽隔离(STI)来作为隔离膜形成工艺。STI已解决在现存LOCOS(硅的局部氧化)方式中所产生的问题，例如鸟嘴现象。STI方法包括：形成沟槽，淀积高密度等离子(HDP)氧化膜以便填充该沟槽，然后使用化学机械抛光(CMP)工艺抛光该氧化膜，以形成隔离膜。 
然而，在使用STI的隔离膜形成工艺中，会产生使隔离膜的边缘部分陷入的沟(或微沟槽)。所述沟由于清洗工艺而产生于沟槽的侧壁与HDP氧化膜之间的界面处，其中清洗工艺在使用STI的隔离膜形成工艺期间会重复执行数次。通常已知的是，因为HDP氧化膜在其结构方面无法充分地填充至上述部分中并因而对清洗工艺期间所使用的清洗溶液是相对较弱的，所以会产生沟。所述沟会导致半导体存储器件的操作特性下降。特别地，在NAND型快闪存储器件中，沟对单元的阈值电压、泄漏电流、有源区的特征尺寸等电特性具有很大影响。最近，控制沟的深度已成为重要的问题。 
通常，在使用STI形成动态随机存取存储器(DRAM)或NAND快闪存储器件的隔离膜的方法中，在沟槽形成工艺之后，执行约10-15次的清洗工艺，直到形成隔离膜。通常，使用稀释氟化氢(DHF)及SC-1(NH4OH/H2O2/H2O)溶液来执行清洗工艺。在NAND型快闪存储器件的情况下，此重复的清洗工艺形成深度约为150埃的沟。在此重复的清洗工艺中，执行在淀积HDP氧化膜之后用于剥离单元区域的垫氧化膜(pad oxide layer)的清洗工艺，从而使高电压区域和作为周边区域的低电压区域的栅极氧化膜以指定的厚度凹进并剥离所述垫氧化膜。在这种情况下，为了使栅极氧化膜以指定的厚度凹进，增大了执行清洗工艺的时间使得所述沟的深度会相应地变深。这会使器件特性变差。 
发明内容
因此，考虑到上述问题而提出本发明，本发明的一个目的在于提供一种用于形成半导体存储器件的隔离膜的方法，在该方法中当执行形成半导体存储器件的隔离膜的工艺时，可缩短从形成沟槽的工艺至形成隔离膜的工艺所执行的使用DHF溶液的清洗工艺的执行时间，由此使形成于隔离膜中的沟的深度最小化。 
为了达到上述目的，依据本发明的一个方面，提供了一种形成隔离膜的方法，其包括下列步骤：提供一半导体衬底，在该半导体衬底中形成有垫氧化膜；在该垫氧化膜上淀积一垫氮化物膜；蚀刻该垫氮化物膜、该垫氧化膜和部分该半导体衬底以形成沟槽；淀积一绝缘膜以填埋所述沟槽；抛光该绝缘膜；剥离该垫氮化物膜；以及执行使用DHF或BOE的清洗工艺以及SC-1清洗工艺，以剥离该垫氧化膜，其中该SC-1清洗工艺是在使该垫氧化膜凹进的温度内执行。 
附图说明
图1至9是说明依据本发明优选实施例的用于形成半导体存储器件隔离膜的方法的剖面图。 
具体实施方式
现将参考附图来描述依据本发明的优选实施例。因为为了使本领域普通技术人员能够理解本发明而提供优选实施例，所以可以以各种方式来修改优选实施例，本发明的范围不限于稍后所描述的优选实施例。 
图1至9是用于说明依据本发明优选实施例的用于形成半导体存储器件隔离膜的方法的剖面图。 
 为了便于说明，将描述形成NAND型快闪存储器件的隔离膜的工艺来作为一个实例。单元区域用″Cell″来表示，高电压区域用″HV″来表示，低电压区域用″LV″来表示。 
参考图1，提供一半导体衬底10，在该半导体衬底10上执行预处理清洗工艺。此时，该预处理清洗工艺可通过使用DHF(例如，使用其中H2O以50∶1的比率来稀释的HF溶液)清洗该半导体衬底、然后使用SC-1(其中NH4OH/H2O2/H2O以给定比率混合的溶液)清洗该半导体衬底来执行，或者使用缓冲氧化物蚀刻剂(BOE)(例如，其中H2O以100∶1或300∶1的比率稀释的HF与NH4F的混合溶液[HF与NH4F的比率为1∶4至1∶7])清洗该半导体衬底、然后使用SC-1清洗该半导体衬底来执行。 
之后，在半导体衬底10上形成屏蔽氧化膜(screen oxide film)(未示出)。在此，形成该屏蔽氧化膜，以防止在后续工艺中所形成的阱以及半导体衬底10的表面在阈值电压离子注入工艺时受到损害。 
然后，执行离子注入工艺，以在半导体衬底10中形成阱(未示出)。在这种情况下，如果半导体衬底10是p型衬底，则所述阱可由TN阱(三重N阱(Triple N-well))和P阱所构成。TN阱是通过使用磷(P)执行离子注入工艺所形成，P阱是通过使用硼(B)执行离子注入工艺所形成。 
接下来，为了形成沟道，在半导体衬底10上执行阈值电压离子注入工艺。然后，在半导体衬底10上形成氧化膜11。在此，氧化膜11形成为在高电压区域HV比在单元区域Cell和低电压区域LV要厚。例如，以下简要描述形成氧化膜11的方法。首先，执行湿式氧化工艺，从而在包括单元区域Cell、低电压区域LV和高电压区域HV的整个表面上形成薄的氧化膜。再次执行湿式氧化工艺，该工艺使用其高电压区域HV敞开的掩模，从而在高电压区域HV中形成厚的氧化膜11。氧化膜11可通过在750℃-800℃的温度范围内执行湿式氧化工艺、然后在900℃-910℃的温度范围内使用N2执行退火工艺来形成。 
同时，尽管为了便于说明并未在所述工艺步骤中描述，但是可在执行所述工艺步骤的工艺期间使用DHF及SC-1执行至少一次清洗工艺。 
为了便于说明，下文中，单元区域Cell中所形成的氧化膜11将称为垫氧化膜11a，低电压区域LV中所形成的氧化膜11将称为低电压栅极氧化膜11b，并且高电压区域HV中所形成的氧化膜11将称为高电压栅极氧化膜11c。 
参考图2，在包括垫氧化膜11a、低电压栅极氧化膜11b及高电压栅极 氧化膜11c的整个表面上淀积垫氮化物膜12。在此，垫氮化物膜12可以由低压化学汽相淀积(LPCVD)方式来淀积。 
参考图3，在将光致抗蚀剂涂敷到包括垫氮化物膜12的整个表面上之后，使用光掩模依序执行曝光工艺及显影工艺，以形成光致抗蚀剂图案(未示出)。 
然后，执行使用光致抗蚀剂图案作为蚀刻掩模的蚀刻工艺，以蚀刻垫氮化物膜12、氧化膜11及半导体衬底10，由此形成沟槽13。由此，在单元区域Cell、低电压区域LV及高电压区域HV中形成沟槽13。在此，沟槽13优选以可确保隔离特性的深度来形成，从而使存储单元和/或晶体管可彼此独立地电隔离。 
参考图4，通过阱氧化工艺(well oxidization process)，在分别形成于单元区域Cell、低电压区域LV及高电压区域HV中的沟槽中形成侧壁氧化膜(wall oxide film)14。在此，阱氧化工艺以干式氧化工艺来执行，从而补偿在沟槽形成工艺中受损的沟槽的侧壁。此外，干式氧化工艺可在700℃-1000℃的温度范围内执行，并将淀积目标设定为50埃-150埃的厚度。 
参考图5，在包括侧壁氧化膜14的整个表面上形成用于隔离膜的绝缘膜15。在此，绝缘膜15使用HDP(高密度等离子)氧化膜形成，并优选经受间隙填充，从而使沟槽13中不产生空洞。绝缘膜15可淀积为约4000埃-10000埃的厚度。 
参考图6，在绝缘膜15上执行抛光工艺，以抛光整个表面。在此，抛光工艺是以CMP(化学机械抛光)方式来执行，但是执行抛光工艺以控制垫氮化物膜12的厚度，从而使垫氮化物膜12以指定的厚度凹进。 
参考图7，在整个已抛光的表面上执行清洗工艺。执行清洗工艺以补偿在抛光工艺中受损的垫氮化物膜12的上表面，或者可使用DHF及SC-1执行清洗工艺，以便去除在表面上存在的不必要的材料等。 
参考图8，使用磷酸(H3PO4)执行蚀刻工艺，以完全地去除在抛光工艺后所残留的垫氮化物膜12。在此，优选使用氧化膜11作为蚀刻终止层来执行蚀刻工艺，以便使半导体衬底10不会受损。 
之后，为了将绝缘膜15的EFT(有效场厚度)控制到约50埃-150埃的厚度，可进一步执行使用DHF和SC-1的清洗工艺。 
参考图9，当剥离在单元区域Cell及低电压区域LV中的氧化膜11a及 11b时，执行清洗工艺，以便使高电压区域HV的氧化膜11c凹进到指定的厚度。在此，清洗工艺可使用其中DHF(稀释的HF)与H2O以50∶1的比率混合的HF溶液(或BOE)和热SC-1来执行。例如，如果执行清洗工艺且将高电压栅极氧化膜11c的凹进目标设定为60埃，清洗工艺优选使用DHF执行25-35秒(优选30秒)，然后使用SC-1在60℃-70℃的温度(优选65℃的温度)下执行1-11分钟(优选10分钟)。即，依据上述工艺条件，在使用DHF的清洗工艺(以下称为″DHF清洗工艺″)中，凹进厚度为30埃，在使用热SC-1的清洗工艺(以下称为″SC-1清洗工艺″)中，凹进厚度变成30埃。在所述工艺条件中，清洗时间依据凹进目标而变化。优选地，在高电压栅极氧化膜11c凹进整个清洗工艺(包括DHF清洗工艺及SC-1清洗工艺)的整个凹进目标的约1/2-3/4期间执行DHF清洗工艺。在高电压栅极氧化膜11c凹进整个凹进目标的约1/4-1/2期间执行SC-1清洗工艺。例如，如果整个凹进目标是60埃-100埃的厚度，则DHF清洗工艺是在约30秒-100秒的范围内执行。 
隔离膜是通过图1至图9的工艺所形成。接下来，通过氧化工艺，在单元区域Cell中形成隧道氧化膜，在低电压区域LV中形成低电压栅极氧化膜，并在高电压区域HV中形成高电压栅极氧化膜。后续工艺与一般的工艺相同。因此，为简化起见省略其说明。 
如上所述，在依据本发明优选实施例的用于形成半导体存储器件的隔离膜的方法中，SC-1清洗工艺是在60℃-70℃的温度范围内执行。这是为了缩短对沟的产生有很大影响的DHF清洗时间。如果SC-1清洗工艺是在60℃-70℃的温度范围内执行，则可完成氧化膜的凹进。然而，如果SC-1清洗工艺是在常温(约25℃)下执行，则氧化膜的凹进很少发生。这是因为，最终凹进的厚度是由使用DHF及SC-1的清洗工艺中的DHF清洗工艺来决定。因此，使DHF清洗时间增加。例如，如果最终的凹进目标设定为60埃，则当SC-1清洗工艺在常温下执行时，DHF清洗时间约为60秒。也就是说，这几乎是与本发明优选实施例的DHF清洗时间相比的2倍。因此，如果应用本发明的优选实施例，则可将整个沟的深度控制到小于50埃，同时使硅衬底10的损失最小化(约小于50埃)。 
为了便于说明已简化了一些描述。然而，本领域技术人员可通过上述用于形成隔离膜的方法来实现依据本发明优选实施例的半导体存储器件的 隔离膜。此外，尽管已参考优选实施例进行了上述说明，但应理解的是，本领域普通技术人员可在不脱离本发明的精神和范围以及所附权利要求的前提下对本发明进行变化和修改。 
如上所述，依据本发明，在形成隧道氧化膜之前所执行的预处理清洗工艺中，SC-1清洗工艺是在60℃-70℃的温度范围内执行。因此，即使在SC-1清洗工艺和DHF清洗工艺中也可使单元区域和周边区域中的氧化膜凹进。因而，可减少DHF清洗时间。因此，本发明具有以下优点：本发明可通过DHF使硅衬底的损失最小化，并因而可控制沟的深度。 

Claims (10)

1.一种形成隔离膜的方法，包括下列步骤：
提供一半导体衬底，在该半导体衬底中形成有一垫氧化膜；
在该垫氧化膜上淀积一垫氮化物膜；
蚀刻该垫氮化物膜、该垫氧化膜和部分该半导体衬底，以形成沟槽；
淀积一绝缘膜，以填埋所述沟槽；
抛光该绝缘膜；
剥离该垫氮化物膜；以及
执行使用DHF或BOE的清洗工艺以及SC-1清洗工艺，以剥离该垫氧化膜，其中该SC-1清洗工艺是在使该垫氧化膜凹进的温度内执行，
其中执行该SC-1清洗工艺，以使形成在该半导体衬底的高电压区域中的垫氧化膜凹进包括所述使用DHF或BOE的清洗工艺以及所述SC-1清洗工艺的整个清洗工艺的整个蚀刻目标的1/4-1/2。
2.如权利要求1所述的方法，其中该SC-1清洗工艺是在60℃-70℃的温度范围内执行。
3.如权利要求1所述的方法，其中执行该DHF清洗工艺，以使形成在该半导体衬底的高电压区域中的垫氧化膜凹进包括所述使用DHF或BOE的清洗工艺以及所述SC-1清洗工艺的整个清洗工艺的整个蚀刻目标的1/2-3/4。
4.如权利要求1所述的方法，其中该DHF清洗工艺执行30-100秒。
5.如权利要求1所述的方法，其中该SC-1清洗工艺执行1-10分钟。
6.如权利要求1、3和4中任何一项所述的方法，其中在该DHF清洗工艺中，DHF是其中H2O以50∶1的比率稀释的HF溶液。
7.如权利要求1所述的方法，其中该垫氧化膜形成为在周边区域的高电压区域中比在该半导体衬底的单元区域中厚。
8.如权利要求7所述的方法，其中通过所述使用DHF或BOE的清洗工艺以及所述SC-1清洗工艺使该高电压区域中所形成的该垫氧化膜凹进到一指定的厚度，而该垫氧化膜的指定厚度保持不变。
9.如权利要求1所述的方法，还包括以下步骤：在抛光该绝缘膜之后，对整个已抛光的表面执行该DHF清洗工艺和该SC-1清洗工艺。
10.如权利要求1所述的方法，还包括以下步骤：在剥离该垫氮化物膜之后，对从其上剥离该垫氮化物膜的整个表面执行该DHF清洗工艺和该SC-1清洗工艺。
CN2005100057782A 2004-09-03 2005-01-25 在半导体存储器件中形成隔离层的方法 Expired - Fee Related CN1744296B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR0070229/04 2004-09-03
KR1020040070229A KR100580117B1 (ko) 2004-09-03 2004-09-03 반도체 메모리 소자의 소자 분리막 형성방법

Publications (2)

Publication Number Publication Date
CN1744296A CN1744296A (zh) 2006-03-08
CN1744296B true CN1744296B (zh) 2012-03-28

Family

ID=36139610

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2005100057782A Expired - Fee Related CN1744296B (zh) 2004-09-03 2005-01-25 在半导体存储器件中形成隔离层的方法

Country Status (5)

Country Link
US (1) US7259078B2 (zh)
JP (1) JP5020469B2 (zh)
KR (1) KR100580117B1 (zh)
CN (1) CN1744296B (zh)
TW (2) TWI309872B (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10306584A1 (de) * 2003-02-17 2004-08-26 Patent-Treuhand-Gesellschaft für elektrische Glühlampen mbH Niederdruckentladungslampe
KR100697283B1 (ko) * 2005-03-29 2007-03-20 삼성전자주식회사 반도체 장치의 소자분리 구조물 및 그 형성방법
KR100811441B1 (ko) * 2006-08-02 2008-03-07 주식회사 하이닉스반도체 플래시 메모리 소자 및 그것의 제조 방법
KR100818425B1 (ko) * 2006-08-29 2008-04-01 동부일렉트로닉스 주식회사 반도체 디스플레이 소자의 셀로우 트렌치 소자분리막 제조방법
KR100870297B1 (ko) * 2007-04-27 2008-11-25 주식회사 하이닉스반도체 반도체 소자의 제조 방법
KR100972881B1 (ko) * 2007-06-28 2010-07-28 주식회사 하이닉스반도체 플래시 메모리 소자의 형성 방법
CN101996873B (zh) * 2009-08-21 2012-07-18 中芯国际集成电路制造(上海)有限公司 氧化物层及包含其的闪存的栅极的制作方法
US8247297B2 (en) * 2009-12-15 2012-08-21 Alpha & Omega Semiconductor Inc. Method of filling large deep trench with high quality oxide for semiconductor devices
JP2012146693A (ja) * 2011-01-06 2012-08-02 Toshiba Corp 半導体記憶装置及びその製造方法
CN107993973B (zh) * 2017-11-23 2020-08-25 长江存储科技有限责任公司 浅沟槽隔离结构的制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1400648A (zh) * 2001-07-30 2003-03-05 旺宏电子股份有限公司 浅槽隔离结构的形成方法
CN1404130A (zh) * 2001-09-06 2003-03-19 旺宏电子股份有限公司 降低浅沟渠隔离侧壁氧化层应力与侵蚀的方法
US6642105B2 (en) * 1999-12-24 2003-11-04 Samsung Electronics Co., Ltd. Semiconductor device having multi-gate insulating layers and methods of fabricating the same
US6737359B1 (en) * 1999-12-13 2004-05-18 Taiwan Semiconductor Manufacturing Company Method of forming a shallow trench isolation using a sion anti-reflective coating which eliminates water spot defects

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5919311A (en) * 1996-11-15 1999-07-06 Memc Electronic Materials, Inc. Control of SiO2 etch rate using dilute chemical etchants in the presence of a megasonic field
KR100283192B1 (ko) * 1998-06-09 2001-04-02 윤종용 반구형결정가입자들을갖는캐패시터의제조방법
US6225167B1 (en) * 2000-03-13 2001-05-01 Taiwan Semiconductor Manufacturing Company Method of generating multiple oxide thicknesses by one oxidation step using NH3 nitridation followed by re-oxidation
JP3551183B2 (ja) * 2001-04-06 2004-08-04 セイコーエプソン株式会社 半導体装置の製造方法
KR100426484B1 (ko) * 2001-12-22 2004-04-14 주식회사 하이닉스반도체 플래쉬 메모리 셀 및 그의 제조방법
KR100426483B1 (ko) * 2001-12-22 2004-04-14 주식회사 하이닉스반도체 플래쉬 메모리 셀의 제조 방법
JP2004039734A (ja) * 2002-07-01 2004-02-05 Fujitsu Ltd 素子分離膜の形成方法
KR100458767B1 (ko) * 2002-07-04 2004-12-03 주식회사 하이닉스반도체 반도체 소자의 소자 분리막 형성 방법
KR100506816B1 (ko) * 2003-01-06 2005-08-09 삼성전자주식회사 반도체 장치 커패시터의 하부 전극 및 이를 형성하기 위한방법
US7508048B2 (en) * 2003-01-16 2009-03-24 Samsung Electronics Co., Ltd. Methods of fabricating a semiconductor device having multi-gate insulation layers and semiconductor devices fabricated thereby
US7091104B2 (en) * 2003-01-23 2006-08-15 Silterra Malaysia Sdn. Bhd. Shallow trench isolation
KR100490288B1 (ko) * 2003-06-30 2005-05-18 주식회사 하이닉스반도체 플래쉬 메모리 소자 제조 방법
US6864148B1 (en) * 2003-09-05 2005-03-08 Mosel Vitelic, Inc. Corner protection to reduce wrap around

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6737359B1 (en) * 1999-12-13 2004-05-18 Taiwan Semiconductor Manufacturing Company Method of forming a shallow trench isolation using a sion anti-reflective coating which eliminates water spot defects
US6642105B2 (en) * 1999-12-24 2003-11-04 Samsung Electronics Co., Ltd. Semiconductor device having multi-gate insulating layers and methods of fabricating the same
CN1400648A (zh) * 2001-07-30 2003-03-05 旺宏电子股份有限公司 浅槽隔离结构的形成方法
CN1404130A (zh) * 2001-09-06 2003-03-19 旺宏电子股份有限公司 降低浅沟渠隔离侧壁氧化层应力与侵蚀的方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
同上.

Also Published As

Publication number Publication date
KR20060021472A (ko) 2006-03-08
TW200903716A (en) 2009-01-16
TWI309872B (en) 2009-05-11
JP5020469B2 (ja) 2012-09-05
JP2006073983A (ja) 2006-03-16
CN1744296A (zh) 2006-03-08
TW200610095A (en) 2006-03-16
KR100580117B1 (ko) 2006-05-12
US7259078B2 (en) 2007-08-21
US20060051930A1 (en) 2006-03-09
TWI313908B (en) 2009-08-21

Similar Documents

Publication Publication Date Title
CN1744296B (zh) 在半导体存储器件中形成隔离层的方法
CN100373593C (zh) 快闪存储器件的制造方法
KR100297737B1 (ko) 반도체소자의 트렌치 소자 분리 방법
JP2006041503A (ja) フラッシュメモリ素子の製造方法
KR100520681B1 (ko) 플래시 메모리 소자의 플로팅 게이트 형성방법
KR100875067B1 (ko) 플래시 메모리 소자의 제조방법
JP2000058635A (ja) 素子間分離絶縁膜の形成方法及び半導体装置
KR101033359B1 (ko) 반도체 소자의 제조 방법
JP2003197734A (ja) 半導体装置の素子分離膜の形成方法
KR100665397B1 (ko) 플래시 메모리 소자의 제조 방법
KR20040003892A (ko) 반도체 소자의 소자분리막 형성 방법
KR100917106B1 (ko) 반도체 소자의 소자 분리막 형성 방법
KR100466188B1 (ko) 플래시 메모리 셀의 플로팅 게이트 제조방법
KR20030043498A (ko) 플래시 메모리 소자의 제조방법
KR100386446B1 (ko) 반도체장치의소자격리막형성방법
KR20010019185A (ko) 트렌치 격리 제조 방법
KR100811438B1 (ko) 반도체 소자의 제조 방법
KR100256821B1 (ko) 반도체 소자의 소자분리막 제조방법
KR100351905B1 (ko) 반도체 소자의 격리막 형성방법
KR101022672B1 (ko) 트렌치형 소자분리를 갖는 반도체소자 및 그의 제조 방법
KR20060072491A (ko) 반도체 소자의 소자분리막 제조 방법
KR20040036800A (ko) 반도체 소자의 소자분리막 형성방법
KR20020010806A (ko) 반도체소자의 소자분리막 형성 방법
KR20050002060A (ko) 선택적 실리콘 리세스로 모우트를 방지한 반도체 소자의제조방법
KR20030000437A (ko) 반도체 소자의 격리막 제조방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20120328

Termination date: 20140125