CN1691308A - 形成半导体器件的接触插塞的方法 - Google Patents

形成半导体器件的接触插塞的方法 Download PDF

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CN1691308A
CN1691308A CNA2005100063459A CN200510006345A CN1691308A CN 1691308 A CN1691308 A CN 1691308A CN A2005100063459 A CNA2005100063459 A CN A2005100063459A CN 200510006345 A CN200510006345 A CN 200510006345A CN 1691308 A CN1691308 A CN 1691308A
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silicon
substrate
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李锡奎
安台恒
朴圣彦
赵俊熙
金一旭
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海力士半导体有限公司
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Abstract

在形成半导体器件的接触插塞的方法中,使用固相外延法形成外延硅以作为接触材料。与使用多晶硅作为接触材料的现有技术相比,该方法可获得减小的接触电阻和改进的刷新特性。此外,该方法使用了SPE法而不是传统的SEG法来形成外延硅,使得其能够通过低温工艺基本降低热预算。本发明还能够使用传统的多晶硅淀积工艺而不用修改,从而简单并多产地形成外延硅。

Description

形成半导体器件的接触插塞的方法

技术领域

本发明涉及一种形成半导体器件的接触插塞的方法,尤其涉及一种使用固相外延法形成外延硅以作为接触材料的方法。

背景技术

随着半导体器件的高度集成,要确保器件的特性变得越发困难。例如,在DRAM单元晶体管的情况下,单元接触区域随着单元晶体管的尺寸逐渐减小而减小。因此,可预期的是,随着接触电阻的迅速增大,单元晶体管的工作电流迅速减少。尽管单元晶体管的尺寸减小,工作电压的向下调整(downward adjustment)进行得非常慢,并且值得关注的是,由于局部电场增加,刷新特性可能会劣化。总之,随着DRAM的高度集成,很难满足单元晶体管的工作电流与刷新特性。

为了增加单元晶体管的工作电流同时保持其阈值电压Vt,以下措施是必要的:第一,增大在结区中的杂质浓度以降低薄层电阻;第二,清洁接触界面;第三,增大用作单元接触下落式插塞(landing plug)的多晶硅中磷(P)的掺杂浓度,以降低结区与下落式插塞之间的接触电阻。

相反,上述用于增加单元晶体管的工作电流的措施,是破坏DRAM的刷新特性的因素。更具体而言,在单元晶体管的工作电流与刷新特性之间存在折衷,同时改善两者比较困难。因此,目前通过恰当地调整工作电流与刷新特性使得它们满足器件的规格,来优化单元晶体管的制造工艺。

为了提高工作电流和刷新特性,尝试将在生长作为下落式插塞材料的多晶硅之前获得清洁接触界面、以尽可能多地去除蚀刻残余物的方法与优化多晶硅和结区内的磷(P)的掺杂浓度和分布的方法相结合。

然而,在小于0.15μm的设计规则中工艺裕度突然变窄,因此新的工艺或材料是必要的。

为了确保单元晶体管的工作电流与刷新特性,已提出了使用新工艺的技术,包括仅对位线接触部分的结区执行硼单元晕影离子注入(boron cellhalo ion injection)的方法和使用RCAT(凹进沟道阵列晶体管)技术的方法,其中源极/漏极的两个结区之间的沟道被制成沟槽形状,以增大沟道长度并减轻局部电场强度。然而,这种新的工艺由于工艺的复杂性,目前没有轻易采用。

为了解决新材料的问题,已提出用外延硅(即单晶硅)替换用作下落式插塞材料的多晶硅。实验显示,在磷(P)的掺杂浓度值对应为多晶硅下落式插塞的磷(P)掺杂浓度的1/5时,外延硅下落式插塞的接触电阻值对应于多晶硅下落式插塞的接触电阻值的2/5(参照图1)。

当外延硅用作下落式插塞材料时,除了低接触电阻的优点外,从下落式插塞向结区中的磷(P)的扩散也会由于低的磷(P)掺杂浓度而减少。这基本减少了泄漏电流同时改善了刷新特性。

为了生长外延硅来作为下落式插塞材料,传统上采用选择性外延生长(下文称为SEG)法。在SEG法中,外延硅选择性地生长在已经过适当预清洁的硅结区上,同时在800-900℃的温度下将作为反应气体的SiH2Cl2、PH3和HCl气体注入氢气气氛中。

随着外延生长的进行,与衬底相同的单晶硅生长在暴露的硅上,然而,因为通过HCl的多晶硅的蚀刻速率比多晶硅的晶核产生和生长速率快,所以在包括氧化硅膜和氮化硅膜的绝缘膜上没有生长硅。因此,外延硅仅在暴露的硅上选择性地生长。

然而,为了使用SEG法生长能生产的薄膜,下列的许多问题仍需解决:第一,由于薄膜生长速率和厚度均匀性的图案相关性,需要设计虚拟图案(dummy pattern);第二,在选择性外延硅生长之前,适当的预清洁是必要的,更具体而言,在选择性外延生长之前的光蚀刻、基于氟化物(HF、BOE、HF蒸汽)的湿式清洁和原位氢焙烤(in-situ hydrogen bake)是必要的;第三,在绝缘表面上的异常生长必须通过精确控制经由金属的污染物来抑制;第四,由高温(800℃或以上)原位氢焙烤和外延硅生长温度所致的短沟道晶体管的特性劣化是一个麻烦;第五,因为晶面的形成,在集成工艺中存在困难;第六,如果外延硅未生长在许多接触(contact)中的某些缺陷接触上,则在后续的工艺中会产生问题。SEG法还需要一些难以使用的特殊设备技术。

总之,尽管当外延硅用作单元接触下落式插塞材料时,接触电阻会下降并同时改善刷新特性,但由于上述问题,这种方法不能在大批量生产中轻易采用。

发明内容

因此,本发明是为了解决现有技术中存在的上述问题而提出的,本发明的一个目的是提供一种形成半导体器件的接触插塞的方法,其通过使用外延硅作为接触材料能够获得低接触电阻和极佳的刷新特性。

本发明的另一个目的是提供一种形成半导体器件的接触插塞的方法,其为了简易且多产的形成外延硅,通过使用传统的工艺而没有修改,就能够生长外延硅以作为接触材料。

为了达到这些目的,提供了一种形成半导体器件的接触插塞的方法,包括下列步骤:提供具有多个导电图案和导电图案之间的结区的硅衬底;在该衬底上形成层间绝缘膜;形成接触孔以暴露衬底的结区;使用固相外延法在包括接触孔的整个衬底上淀积硅膜,使得外延硅生长在衬底的结区上且非晶硅淀积在其上;对所得结构退火从而使非晶硅重新生长(regrow)为外延硅。

淀积硅膜的步骤是在1-100Torr的压力下以及550-650℃的温度下执行的。

淀积硅膜的步骤是以1E19-1E20原子/立方厘米的磷掺杂浓度执行的。

退火以将非晶硅重新生长为外延硅的步骤是于500-700℃的温度下在惰性气体气氛中执行至少30分钟。

而且,为了达到这些目的,提供了一种形成半导体器件的接触插塞的方法,包括下列步骤:提供具有多个栅电极的硅衬底;在所得结构上淀积绝缘膜;在栅电极之间的衬底的区域中形成结区;在所得结构上形成层间绝缘膜;形成接触孔以暴露衬底的结区;清洁该衬底的暴露的结区;使用固相外延法在包括接触孔的整个衬底上淀积硅膜,使得外延硅生长在衬底的结区上且非晶硅淀积在其上;对所得结构退火从而使非晶硅重新生长为外延硅。

淀积硅膜的步骤是在1-100Torr的压力下以及550-650℃的温度下执行的。

淀积硅膜的步骤是以1E19-1E20原子/立方厘米的磷掺杂浓度执行的。

退火以将非晶硅重新生长为外延硅的步骤是于500-700℃的温度下在惰性气体气氛中执行至少30分钟。

此外,为了达到这些目的,提供了一种形成半导体器件的接触插塞的方法,包括下列步骤:提供具有形成于其上的多个栅电极的硅衬底;在包括栅电极的整个衬底上淀积栅极密封绝缘膜;在栅电极之间的衬底区域中形成结区;在所得结构上淀积栅极间隙壁膜与层间绝缘膜;蚀刻层间绝缘膜、栅极间隙壁膜、栅极密封绝缘膜,以形成暴露出多个栅电极和栅电极之间的衬底的结区的下落式插塞接触孔(landing plug contact);在衬底暴露的接触区域上执行预清洁与氢焙烤;使用固相外延方法在包括下落式插塞接触孔的整个衬底上淀积硅膜,使得外延硅生长在衬底的结区上且非晶硅淀积于其上;在所得结构上执行再结晶退火,以将下落式插塞接触孔内的非晶硅重新生长为外延硅;并且从栅电极的顶部去除外延硅。

预清洁步骤包括:在远端(remote)等离子或低功耗等离子状态下使用从基于NF3/He/O2的反应气体、基于CF4/O2的反应气体和基于Ar/O2的反应气体所构成的组中选取的任何一种反应气体进行光蚀刻,并且使用从HF溶液、BOE溶液和HF蒸汽所构成的组中选取的任何一种进行基于氟化物的清洁。

所得结构在预清洁之后被载入淀积设备中至少4小时,在载入期间维持真空,或者,当衬底在大气压力状态下被载入时,用高纯度的氮或氩惰性气体将其净化,同时保持氧浓度在10ppm以下。

淀积硅膜的步骤是在1-100Torr的压力下以及550-650℃的温度下执行的。

淀积硅膜的步骤是以1E19-1E20原子/立方厘米的磷掺杂浓度执行的。

执行再结晶退火以将非晶硅重新生长为外延硅的步骤是于500-700℃的温度下在惰性气体气氛中执行至少30分钟。

附图说明

本发明的以上和其他目的、特征及优点将从以下结合附图的详细描述中变得更加明显,附图中:图1是外延硅和多晶硅的接触电阻与磷(P)掺杂浓度的关系曲线;以及图2A至图2F是根据本发明的实施例用于形成接触插塞的方法的一系列工序的剖面图。

具体实施方式

以下,将参考附图描述本发明的优选实施例。在下面的描述与附图中,相同的附图标记用于标明相同或相似的元件,因而将省略对相同或相似元件的描述。

根据本发明,形成外延硅以作为接触材料,即作为单元接触下落式插塞材料。为了形成外延硅,使用固相外延(以下称为SPE)法,其中在低温下器件所需的具有适当范围磷(P)的非晶硅被淀积在接触界面上,该接触界面经过选择性预清洁,然后在低温下通过再结晶退火形成外延硅。通过在外延硅生长之前获得已被极度清洁的接触界面,本发明能够稳定外延硅的生长。

通过以这样的方式使用外延硅作为接触材料,能够降低接触电阻同时改善刷新特性。此外,使用适合于低温(700℃或更低)的传统工艺而不用修改,可以以高生产率很容易地形成外延硅。

现将参照图2A至2F详细描述根据本发明实施例的形成接触插塞的方法,图2A至2F是该方法一系列工序的剖面图。

参照图2A,使用STI(浅沟槽隔离)工艺在硅衬底1的预定位置中形成器件隔离膜2。接着,连续执行数个离子注入工艺。之后,栅极氧化膜3、栅极导电膜4和硬掩模氮化物膜5相继形成在整个硅衬底1上并被构图,从而形成栅电极6以作为导电图案。

栅极导电膜4可由多晶硅膜4a或金属膜4b所制成的单一膜来构成。可选择地,栅极导电膜4可通过堆叠多晶硅膜4a和金属膜4b来形成。金属膜4b由金属硅化物或在高温下具有极佳稳定性的耐火金属来制成。

参考图2B,执行热氧化或CVD工艺以形成栅极缓冲氧化膜(未示出),并将作为栅极密封绝缘膜的氮化物膜7淀积在所得结构上。然后,执行离子注入以形成结区8。结区8中的杂质掺杂分布变得平缓,在栅电极6端部的电场强度减轻,结区8中的泄漏电流减小。

尽管未在图中示出,使用传统的方法来形成外围电路部分中用于晶体管的结区,并在整个衬底上形成栅极间隙壁氮化物膜9。然后在栅极间隙壁氮化物膜9上淀积层间绝缘膜10。使用下落式插塞接触孔工艺,层间绝缘膜10、栅极间隙壁氮化物膜9、栅极密封氮化物膜7和栅极缓冲氧化膜相继经受干蚀刻以形成接触孔,即下落式插塞接触孔11,其暴露多个栅电极6以及栅电极6之间的衬底的结区8。

参考图2C,在具有形成于其上的下落式插塞接触孔11的所得结构上执行选择性预清洁,以获得清洁的接触界面。然后将所得结构载入能够在真空下载入衬底的硅淀积设备中,并在这一状态下执行原位氢焙烤。

为了完全去除当蚀刻下落式插塞接触孔时出现的蚀刻残余物、去除蚀刻损伤并去除单元接触表面上的天然氧化膜,设定预清洁工艺的工艺条件。更具体而言,蚀刻残余物与蚀刻损伤是通过在远端等离子或低功耗等离子状态下使用基于NF3/He/O2、基于CF4/O2或基于Ar/O2的反应气体的光蚀刻来去除的。在光蚀刻过程中,去除在单元接触蚀刻期间出现的与聚合物相关的包括C-F、C-O和C-C的蚀刻残余物。在光蚀刻之后,由于在光蚀刻期间供应的氧气,约1-4nm的氧化硅膜形成在单元接触硅表面上。因此,光蚀刻之后必须有基于氟化物的预清洁,利如使用HF或BOE溶液的湿式清洁或使用HF蒸汽的蒸汽清洁,以去除形成在单元接触硅表面上的氧化硅膜。

而且,有必要抑制将已经受上述预清洁的衬底载入硅淀积设备所造成的污染物或界面氧化膜,直至淀积。为此,在预清洁之后,衬底必须被载入淀积设备至少4个小时。在载入期间,必须维持真空,或者,如果衬底在大气压力状态下被载入时,用惰性气体、如高纯度的氮或氩将其净化,同时保持氧浓度在10ppm以下。这是因为,当衬底被放入高温(400℃或以上)的反应室中时,如果大气中的氧浓度为10ppm或更高,则0.5nm或更厚的界面氧化膜会形成在接触界面上。在这种情况下,结区中的硅衬底就不能作为用于外延硅生长的后续热工艺中的晶种,且整个单元接触下落式插塞结晶为多晶硅。因此,在硅膜淀积到其上之前,在衬底被装载之后于750℃或以上的温度下执行氢焙烤,以更加确定地去除界面氧化膜。在这种工艺中,在预清洁之后传输衬底时以及将衬底载入淀积设备时所产生的任何界面氧化膜被完全去除。

参考图2D,硅膜12与13淀积在包括下落式插塞接触孔11的层间绝缘膜10上。在接触界面中,衬底的结区8的单晶硅用作晶种并且外延硅12和淀积于其上的非晶硅13一起生长。硅膜的淀积必须在1-100Torr的压力下和550-650℃的温度下执行,使得外延硅12生长在接触界面上,并且非晶硅13淀积在别处。考虑到在后续的器件集成工艺中所供应的热能的总量、即热预算(thermal budget),膜内的磷(P)掺杂浓度必须被调节到1E19-1E20原子/立方厘米的范围内。

参考图2E,在经过以上工艺后,所得结构在700℃或以下、优选500-700℃的温度下,于惰性气氛中经受至少30分钟的再结晶退火。在这样的退火中,当已生长在接触界面上的外延硅用作晶种时,非晶硅再结晶为外延硅12。

在上部非晶硅由于外延硅晶种而再结晶为外延硅时,在栅极间隙壁氮化物膜9或层间氮化物膜10和非晶硅之间的界面处会发生晶核产生与晶体生长。在这种情况下,下落式插塞接触孔中可生长多晶硅,下落式插塞的接触电阻可能增加。因此,再结晶热处理的工艺条件,尤其是再结晶温度与时间,必须适当调节,使得这样的多晶硅的形成可被避免。

参照图2F,所得结构经受回蚀刻(etch-back)或化学机械抛光工艺,以从栅电极6的顶部去除外延硅。结果,形成了由外延硅12制成的本发明的下落式插塞20。

之后,执行一系列传统工艺以完成半导体器件。

如上所述,与使用多晶硅作为接触材料的现有技术相比,本发明使用外延硅来作为接触材料,由此获得了减小的接触电阻和改进的刷新特性。

此外,本发明使用了SPE法而不是传统的SEG法来形成外延硅,从而使其能够通过低温工艺来基本降低热预算。本发明能够使用传统的多晶硅淀积工艺而不用修改,从而简单并多产地形成外延硅。

虽然为了说明的目的描述了本发明的优选实施例,本领域技术人员应理解的是,在不偏离由所附权利要求公开的本发明的主旨和范围的前提下,可进行多种修改、添加和替代。

Claims (14)

1.一种形成半导体器件的接触插塞的方法,包括下列步骤:提供硅衬底,所述硅衬底具有多个导电图案和所述导电图案之间的结区;在所述衬底上形成层间绝缘膜;形成接触孔以暴露所述衬底的所述结区;使用固相外延法在包括所述接触孔的所述整个衬底上淀积硅膜,使得外延硅生长在所述衬底的所述结区上并且非晶硅淀积在其上;以及对所得结构退火以将所述非晶硅重新生长为外延硅。
2.如权利要求1所述的方法,其中淀积硅膜的步骤是在1-100Torr的压力下以及550-650℃的温度下执行的。
3.如权利要求1所述的方法,其中淀积硅膜的步骤是以1E19-1E20原子/立方厘米的磷掺杂浓度执行的。
4.如权利要求1所述的方法,其中退火以将非晶硅重新生长为外延硅的步骤是于500-700℃的温度下在惰性气体气氛中执行至少30分钟。
5.一种形成半导体器件的接触插塞的方法,包括下列步骤:提供具有多个栅电极的硅衬底;在所得结构上淀积绝缘膜;在所述栅电极之间的所述衬底的区域中形成结区;在所得结构上形成层间绝缘膜;形成接触孔以暴露所述衬底的所述结区;清洁所述衬底的所述暴露的结区;使用固相外延法在包括所述接触孔的所述整个衬底上淀积硅膜,使得外延硅生长在所述衬底的所述结区上并且非晶硅淀积在其上;以及对所得结构退火以将所述非晶硅重新生长为外延硅。
6.如权利要求5所述的方法,其中淀积硅膜的步骤是在1-100Torr的压力下以及550-650℃的温度下执行的。
7.如权利要求5所述的方法,其中淀积硅膜的步骤是以1E19-1E20原子/立方厘米的磷掺杂浓度执行的。
8.如权利要求5所述的方法,其中退火以将非晶硅重新生长为外延硅的步骤是于500-700℃的温度下在惰性气体气氛中执行至少30分钟。
9.一种形成半导体器件的接触插塞的方法,包括下列步骤:提供硅衬底,所述硅衬底具有形成于其上的多个栅电极;在包括所述栅电极的所述整个衬底上淀积栅极密封绝缘膜;在所述栅电极之间的所述衬底的区域中形成结区;在所得结构上淀积栅极间隙壁膜与层间绝缘膜;蚀刻所述层间绝缘膜、所述栅极间隙壁膜和所述栅极密封绝缘膜,以形成暴露出所述多个栅电极和所述栅电极之间的所述衬底的结区的下落式插塞接触孔;在所述衬底的暴露的接触区域上执行预清洁和氢焙烤;使用固相外延法在包括所述下落式插塞接触孔的所述整个衬底上淀积硅膜,使得外延硅生长在所述衬底的所述结区上并且非晶硅淀积于其上;在所得结构上执行再结晶退火,以将所述下落式插塞接触孔内的非晶硅重新生长为外延硅;以及从所述栅电极的顶部去除外延硅。
10.如权利要求9所述的方法,其中预清洁步骤包括:在远端等离子或低功耗等离子状态下使用从基于NF3/He/O2的反应气体、基于CF4/O2的反应气体和基于Ar/O2的反应气体所构成的组中选取的任何一种反应气体进行光蚀刻,并且使用从HF溶液、BOE溶液和HF蒸汽所构成的组中选取的任何一种进行基于氟化物的清洁。
11.如权利要求9所述的方法,其中所得结构在预清洁之后被载入淀积设备中至少4小时,并且在载入期间维持真空,或者当所述衬底在大气压力状态下被载入时,用高纯度的氮或氩惰性气体将其净化,同时保持氧浓度在10ppm以下。
12.如权利要求9所述的方法,其中淀积硅膜的步骤是在1-100Torr的压力下以及550-650℃的温度下执行的。
13.如权利要求9所述的方法,其中淀积硅膜的步骤是以1E19-1E20原子/立方厘米的磷掺杂浓度执行的。
14.如权利要求9所述的方法,其中执行再结晶退火以将非晶硅重新生长为外延硅的步骤是于500-700℃的温度下在惰性气体气氛中执行至少30分钟。
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