CN1667801B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN1667801B
CN1667801B CN2004100974363A CN200410097436A CN1667801B CN 1667801 B CN1667801 B CN 1667801B CN 2004100974363 A CN2004100974363 A CN 2004100974363A CN 200410097436 A CN200410097436 A CN 200410097436A CN 1667801 B CN1667801 B CN 1667801B
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insulating film
main surface
semiconductor chip
sealing layer
semiconductor device
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CN2004100974363A
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Chinese (zh)
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CN1667801A (zh
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长崎健二
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Lapis Semiconductor Co Ltd
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Oki Electric Industry Co Ltd
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    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
CN2004100974363A 2004-03-08 2004-11-15 半导体装置及其制造方法 Expired - Lifetime CN1667801B (zh)

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JP64071/2004 2004-03-08
JP2004064071A JP4264823B2 (ja) 2004-03-08 2004-03-08 半導体装置の製造方法
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CN1667801B true CN1667801B (zh) 2013-06-12

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Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006054606A1 (ja) 2004-11-16 2006-05-26 Rohm Co., Ltd. 半導体装置および半導体装置の製造方法
JP4057017B2 (ja) * 2005-01-31 2008-03-05 富士通株式会社 電子装置及びその製造方法
JP4193897B2 (ja) * 2006-05-19 2008-12-10 カシオ計算機株式会社 半導体装置およびその製造方法
KR20080085380A (ko) * 2007-03-19 2008-09-24 삼성전자주식회사 재배선층을 구비하는 반도체 패키지 및 그의 제조방법
KR20090042574A (ko) * 2007-10-26 2009-04-30 삼성전자주식회사 반도체 모듈 및 이를 구비하는 전자 장치
JP5801989B2 (ja) * 2008-08-20 2015-10-28 ラピスセミコンダクタ株式会社 半導体装置および半導体装置の製造方法
JP5135246B2 (ja) 2009-01-30 2013-02-06 三洋電機株式会社 半導体モジュールおよびその製造方法、ならびに携帯機器
US10756040B2 (en) * 2017-02-13 2020-08-25 Mediatek Inc. Semiconductor package with rigid under bump metallurgy (UBM) stack
KR102543869B1 (ko) * 2018-08-07 2023-06-14 삼성전자주식회사 반도체 장치 및 이를 포함하는 반도체 패키지
KR102378837B1 (ko) * 2018-08-24 2022-03-24 삼성전자주식회사 반도체 장치 및 이를 포함하는 반도체 패키지

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1246731A (zh) * 1998-08-28 2000-03-08 三星电子株式会社 芯片尺寸封装和制备晶片级的芯片尺寸封装的方法
CN1276090A (zh) * 1997-10-30 2000-12-06 株式会社日产制作所 半导体装置及其制造方法
US6181569B1 (en) * 1999-06-07 2001-01-30 Kishore K. Chakravorty Low cost chip size package and method of fabricating the same
US6621154B1 (en) * 2000-02-18 2003-09-16 Hitachi, Ltd. Semiconductor apparatus having stress cushioning layer

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0582511A (ja) 1991-09-19 1993-04-02 Oki Electric Ind Co Ltd 半導体素子およびその製造方法
JP2001168126A (ja) 1999-12-06 2001-06-22 Sanyo Electric Co Ltd 半導体装置とその製造方法
JP2001237348A (ja) 2000-02-23 2001-08-31 Hitachi Ltd 半導体装置およびその製造方法
JP3792545B2 (ja) 2001-07-09 2006-07-05 カシオ計算機株式会社 半導体装置の製造方法
JP2003124392A (ja) 2001-10-15 2003-04-25 Sony Corp 半導体装置及びその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1276090A (zh) * 1997-10-30 2000-12-06 株式会社日产制作所 半导体装置及其制造方法
CN1246731A (zh) * 1998-08-28 2000-03-08 三星电子株式会社 芯片尺寸封装和制备晶片级的芯片尺寸封装的方法
US6181569B1 (en) * 1999-06-07 2001-01-30 Kishore K. Chakravorty Low cost chip size package and method of fabricating the same
US6621154B1 (en) * 2000-02-18 2003-09-16 Hitachi, Ltd. Semiconductor apparatus having stress cushioning layer

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
说明书第2栏至第28栏、附图4.

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US7687320B2 (en) 2010-03-30

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