JP4264823B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP4264823B2
JP4264823B2 JP2004064071A JP2004064071A JP4264823B2 JP 4264823 B2 JP4264823 B2 JP 4264823B2 JP 2004064071 A JP2004064071 A JP 2004064071A JP 2004064071 A JP2004064071 A JP 2004064071A JP 4264823 B2 JP4264823 B2 JP 4264823B2
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Prior art keywords
insulating film
forming step
layer
sealing layer
semiconductor device
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Expired - Lifetime
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JP2004064071A
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English (en)
Japanese (ja)
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JP2005252169A (ja
JP2005252169A5 (enExample
Inventor
健二 長崎
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Lapis Semiconductor Co Ltd
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Oki Semiconductor Co Ltd
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Application filed by Oki Semiconductor Co Ltd filed Critical Oki Semiconductor Co Ltd
Priority to JP2004064071A priority Critical patent/JP4264823B2/ja
Priority to US10/980,316 priority patent/US7122910B2/en
Priority to CN2004100974363A priority patent/CN1667801B/zh
Publication of JP2005252169A publication Critical patent/JP2005252169A/ja
Priority to US11/511,267 priority patent/US7687320B2/en
Publication of JP2005252169A5 publication Critical patent/JP2005252169A5/ja
Application granted granted Critical
Publication of JP4264823B2 publication Critical patent/JP4264823B2/ja
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    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
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JP2004064071A 2004-03-08 2004-03-08 半導体装置の製造方法 Expired - Lifetime JP4264823B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2004064071A JP4264823B2 (ja) 2004-03-08 2004-03-08 半導体装置の製造方法
US10/980,316 US7122910B2 (en) 2004-03-08 2004-11-04 Packaged semiconductor device
CN2004100974363A CN1667801B (zh) 2004-03-08 2004-11-15 半导体装置及其制造方法
US11/511,267 US7687320B2 (en) 2004-03-08 2006-08-29 Manufacturing method for packaged semiconductor device

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Application Number Priority Date Filing Date Title
JP2004064071A JP4264823B2 (ja) 2004-03-08 2004-03-08 半導体装置の製造方法

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JP2005252169A JP2005252169A (ja) 2005-09-15
JP2005252169A5 JP2005252169A5 (enExample) 2006-10-05
JP4264823B2 true JP4264823B2 (ja) 2009-05-20

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JP (1) JP4264823B2 (enExample)
CN (1) CN1667801B (enExample)

Families Citing this family (10)

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Publication number Priority date Publication date Assignee Title
WO2006054606A1 (ja) 2004-11-16 2006-05-26 Rohm Co., Ltd. 半導体装置および半導体装置の製造方法
JP4057017B2 (ja) * 2005-01-31 2008-03-05 富士通株式会社 電子装置及びその製造方法
JP4193897B2 (ja) * 2006-05-19 2008-12-10 カシオ計算機株式会社 半導体装置およびその製造方法
KR20080085380A (ko) * 2007-03-19 2008-09-24 삼성전자주식회사 재배선층을 구비하는 반도체 패키지 및 그의 제조방법
KR20090042574A (ko) * 2007-10-26 2009-04-30 삼성전자주식회사 반도체 모듈 및 이를 구비하는 전자 장치
JP5801989B2 (ja) * 2008-08-20 2015-10-28 ラピスセミコンダクタ株式会社 半導体装置および半導体装置の製造方法
JP5135246B2 (ja) 2009-01-30 2013-02-06 三洋電機株式会社 半導体モジュールおよびその製造方法、ならびに携帯機器
US10756040B2 (en) * 2017-02-13 2020-08-25 Mediatek Inc. Semiconductor package with rigid under bump metallurgy (UBM) stack
KR102543869B1 (ko) * 2018-08-07 2023-06-14 삼성전자주식회사 반도체 장치 및 이를 포함하는 반도체 패키지
KR102378837B1 (ko) * 2018-08-24 2022-03-24 삼성전자주식회사 반도체 장치 및 이를 포함하는 반도체 패키지

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0582511A (ja) 1991-09-19 1993-04-02 Oki Electric Ind Co Ltd 半導体素子およびその製造方法
CN1146976C (zh) * 1997-10-30 2004-04-21 株式会社日产制作所 半导体装置及其制造方法
KR100269540B1 (ko) * 1998-08-28 2000-10-16 윤종용 웨이퍼 상태에서의 칩 스케일 패키지 제조 방법
US6181569B1 (en) * 1999-06-07 2001-01-30 Kishore K. Chakravorty Low cost chip size package and method of fabricating the same
JP2001168126A (ja) 1999-12-06 2001-06-22 Sanyo Electric Co Ltd 半導体装置とその製造方法
JP2001230341A (ja) * 2000-02-18 2001-08-24 Hitachi Ltd 半導体装置
JP2001237348A (ja) 2000-02-23 2001-08-31 Hitachi Ltd 半導体装置およびその製造方法
JP3792545B2 (ja) 2001-07-09 2006-07-05 カシオ計算機株式会社 半導体装置の製造方法
JP2003124392A (ja) 2001-10-15 2003-04-25 Sony Corp 半導体装置及びその製造方法

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US7122910B2 (en) 2006-10-17
CN1667801B (zh) 2013-06-12
US7687320B2 (en) 2010-03-30

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