CN1647268A - 载体、制造载体和电子器件的方法 - Google Patents

载体、制造载体和电子器件的方法 Download PDF

Info

Publication number
CN1647268A
CN1647268A CNA038080575A CN03808057A CN1647268A CN 1647268 A CN1647268 A CN 1647268A CN A038080575 A CNA038080575 A CN A038080575A CN 03808057 A CN03808057 A CN 03808057A CN 1647268 A CN1647268 A CN 1647268A
Authority
CN
China
Prior art keywords
carrier
layer
metal layer
intermediate layer
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA038080575A
Other languages
English (en)
Other versions
CN1315185C (zh
Inventor
P·A·J·格罗恩休斯
P·迪克斯特拉
C·G·施里克斯
P·W·M·范德瓦特
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
III Holdings 6 LLC
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of CN1647268A publication Critical patent/CN1647268A/zh
Application granted granted Critical
Publication of CN1315185C publication Critical patent/CN1315185C/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061—Etching masks
    • H05K3/062—Etching masks consisting of metals or alloys or metallic inorganic compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • A—HUMAN NECESSITIES
    • A23—FOODS OR FOODSTUFFS; TREATMENT THEREOF, NOT COVERED BY OTHER CLASSES
    • A23G—COCOA; COCOA PRODUCTS, e.g. CHOCOLATE; SUBSTITUTES FOR COCOA OR COCOA PRODUCTS; CONFECTIONERY; CHEWING GUM; ICE-CREAM; PREPARATION THEREOF
    • A23G3/00—Sweetmeats; Confectionery; Marzipan; Coated or filled products
    • A23G3/34—Sweetmeats, confectionery or marzipan; Processes for the preparation thereof
    • A23G3/36—Sweetmeats, confectionery or marzipan; Processes for the preparation thereof characterised by the composition containing organic or inorganic compounds
    • A23G3/364—Sweetmeats, confectionery or marzipan; Processes for the preparation thereof characterised by the composition containing organic or inorganic compounds containing microorganisms or enzymes; containing paramedical or dietetical agents, e.g. vitamins
    • A23G3/366—Sweetmeats, confectionery or marzipan; Processes for the preparation thereof characterised by the composition containing organic or inorganic compounds containing microorganisms or enzymes; containing paramedical or dietetical agents, e.g. vitamins containing microorganisms, enzymes
    • A—HUMAN NECESSITIES
    • A23—FOODS OR FOODSTUFFS; TREATMENT THEREOF, NOT COVERED BY OTHER CLASSES
    • A23G—COCOA; COCOA PRODUCTS, e.g. CHOCOLATE; SUBSTITUTES FOR COCOA OR COCOA PRODUCTS; CONFECTIONERY; CHEWING GUM; ICE-CREAM; PREPARATION THEREOF
    • A23G4/00—Chewing gum
    • A23G4/06—Chewing gum characterised by the composition containing organic or inorganic compounds
    • A23G4/12—Chewing gum characterised by the composition containing organic or inorganic compounds containing microorganisms or enzymes; containing paramedical or dietetical agents, e.g. vitamins
    • A23G4/123—Chewing gum characterised by the composition containing organic or inorganic compounds containing microorganisms or enzymes; containing paramedical or dietetical agents, e.g. vitamins containing microorganisms, enzymes
    • A—HUMAN NECESSITIES
    • A23—FOODS OR FOODSTUFFS; TREATMENT THEREOF, NOT COVERED BY OTHER CLASSES
    • A23L—FOODS, FOODSTUFFS, OR NON-ALCOHOLIC BEVERAGES, NOT COVERED BY SUBCLASSES A21D OR A23B-A23J; THEIR PREPARATION OR TREATMENT, e.g. COOKING, MODIFICATION OF NUTRITIVE QUALITIES, PHYSICAL TREATMENT; PRESERVATION OF FOODS OR FOODSTUFFS, IN GENERAL
    • A23L33/00—Modifying nutritive qualities of foods; Dietetic products; Preparation or treatment thereof
    • A23L33/10—Modifying nutritive qualities of foods; Dietetic products; Preparation or treatment thereof using additives
    • A23L33/135—Bacteria or derivatives thereof, e.g. probiotics
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61K—PREPARATIONS FOR MEDICAL, DENTAL OR TOILETRY PURPOSES
    • A61K35/00—Medicinal preparations containing materials or reaction products thereof with undetermined constitution
    • A61K35/66—Microorganisms or materials therefrom
    • A61K35/74—Bacteria
    • A61K35/741—Probiotics
    • A61K35/744—Lactic acid bacteria, e.g. enterococci, pediococci, lactococci, streptococci or leuconostocs
    • A61K35/747—Lactobacilli, e.g. L. acidophilus or L. brevis
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61P—SPECIFIC THERAPEUTIC ACTIVITY OF CHEMICAL COMPOUNDS OR MEDICINAL PREPARATIONS
    • A61P1/00—Drugs for disorders of the alimentary tract or the digestive system
    • A61P1/02—Stomatological preparations, e.g. drugs for caries, aphtae, periodontitis
    • C—CHEMISTRY; METALLURGY
    • C12—BIOCHEMISTRY; BEER; SPIRITS; WINE; VINEGAR; MICROBIOLOGY; ENZYMOLOGY; MUTATION OR GENETIC ENGINEERING
    • C12N—MICROORGANISMS OR ENZYMES; COMPOSITIONS THEREOF; PROPAGATING, PRESERVING, OR MAINTAINING MICROORGANISMS; MUTATION OR GENETIC ENGINEERING; CULTURE MEDIA
    • C12N1/00—Microorganisms, e.g. protozoa; Compositions thereof; Processes of propagating, maintaining or preserving microorganisms or compositions thereof; Processes of preparing or isolating a composition containing a microorganism; Culture media therefor
    • C12N1/20—Bacteria; Culture media therefor
    • C12N1/205—Bacterial isolates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • A—HUMAN NECESSITIES
    • A23—FOODS OR FOODSTUFFS; TREATMENT THEREOF, NOT COVERED BY OTHER CLASSES
    • A23V—INDEXING SCHEME RELATING TO FOODS, FOODSTUFFS OR NON-ALCOHOLIC BEVERAGES AND LACTIC OR PROPIONIC ACID BACTERIA USED IN FOODSTUFFS OR FOOD PREPARATION
    • A23V2400/00—Lactic or propionic acid bacteria
    • A23V2400/11—Lactobacillus
    • A23V2400/179—Sakei
    • C—CHEMISTRY; METALLURGY
    • C12—BIOCHEMISTRY; BEER; SPIRITS; WINE; VINEGAR; MICROBIOLOGY; ENZYMOLOGY; MUTATION OR GENETIC ENGINEERING
    • C12R—INDEXING SCHEME ASSOCIATED WITH SUBCLASSES C12C - C12Q, RELATING TO MICROORGANISMS
    • C12R2001/00—Microorganisms ; Processes using microorganisms
    • C12R2001/01—Bacteria or Actinomycetales ; using bacteria or Actinomycetales
    • C12R2001/225—Lactobacillus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01061—Promethium [Pm]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0361—Etched tri-metal structure, i.e. metal layers or metal patterns on both sides of a different central metal layer which is later at least partly etched
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0384—Etch stop layer, i.e. a buried barrier layer for preventing etching of layers under the etch stop layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
    • H05K2203/1469—Circuit made after mounting or encapsulation of the components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning

Landscapes

  • Engineering & Computer Science (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Health & Medical Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microbiology (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Polymers & Plastics (AREA)
  • Food Science & Technology (AREA)
  • Nutrition Science (AREA)
  • Mycology (AREA)
  • Bioinformatics & Cheminformatics (AREA)
  • General Health & Medical Sciences (AREA)
  • Organic Chemistry (AREA)
  • Medicinal Chemistry (AREA)
  • Genetics & Genomics (AREA)
  • Wood Science & Technology (AREA)
  • Zoology (AREA)
  • Inorganic Chemistry (AREA)
  • Biotechnology (AREA)
  • Animal Behavior & Ethology (AREA)
  • Public Health (AREA)
  • Veterinary Medicine (AREA)
  • Pharmacology & Pharmacy (AREA)
  • Metallurgy (AREA)
  • General Engineering & Computer Science (AREA)
  • Molecular Biology (AREA)
  • Tropical Medicine & Parasitology (AREA)
  • Virology (AREA)
  • Biomedical Technology (AREA)
  • Epidemiology (AREA)
  • Biochemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Nuclear Medicine, Radiotherapy & Molecular Imaging (AREA)

Abstract

载体(30)包括第一蚀刻掩模(14)、第一金属层(11)、中间层(12)、第二金属层(13)和第二蚀刻掩模(17)。第一和第二蚀刻掩模(14、17)都可以通过电化学镀附来在一个步骤中设置。在第一金属层(11)和中间层(12)已经通过第一蚀刻掩模(14)构图以后，电元件(20)可以使用导电装置合适地接附到载体(30)。在构图操作中，进一步蚀刻中间层(12)，以便在第一金属层(11)下产生蚀刻不足。在设置封装(40)以后，通过第二蚀刻掩模(17)来构图第二金属层(13)。这样，在组装过程期间不需要光刻步骤的情况下获得了可焊接的器件(10)。

Description

载体、制造载体和电子器件的方法
本发明涉及一种制造设置有电元件和包括第一构图的金属层、构图的中间层和第二金属层的堆叠的具有第一侧和第二侧的载体的电子器件的方法，
该方法包括的步骤为：
将电元件设置在载体的第一侧上，电元件的触点导电地连接到第一金属层；以及
提供围绕电元件的封装。
本发明还涉及具有第一和第二侧的载体，其包括第一金属层、中间层和第二金属层的堆叠。
本分明还涉及制造具有第一侧和相对的第二侧的载体的方法，其包括的步骤为：
提供第一金属层、中间层和第二金属层的堆叠，其中，第一和第二金属层导电地相互连接，其中，第一金属层位于第一侧上；以及
根据需要的图案构图该第一金属层。
这样的载体和这样的制造包括载体的电子器件的方法从EP-A1.160.858已知。该已知的载体是Al、Cu、Fe-Ni合金的载体，或者Cu-Al或者Al-Cu-Al的堆叠的载体。该载体设置在具有需要的图案和金属Ni、Au、Ag和Pd中的至少一种的导电层的第一侧上。在该器件的制造过程中，在设置半导体元件和设置封装以后，其中没有设置图案的载体的部分被去除。随后，掩模光刻地设置在载体的第二侧上，在这之后，形成接触面或者引导管脚。
已知方法的缺点在于，在电元件组装以后需要光刻步骤。这意味着，该步骤必须在组装设备中进行，由于这样的设备中通常流行的条件，所以这是不希望的。
因此，本发明的第一个目的是提供一种制造在开始段落中提到的类型的电子器件的方法，其中，在设置电元件以后，不需要光刻步骤，该方法仍然产生一种紧凑和足够坚固的器件。
该第一目的实现为，该载体包括在第二侧上的蚀刻掩模，以及所述载体的第一金属层导电地连接到第二金属层，且具有相对于中间层突出的部分。在设置最好整个地封装电元件的封装以后，根据由蚀刻掩模限定的图案来从载体的第二侧蚀刻该第二金属层。
在根据本发明的方法中，载体的第二金属层没有完全地被去除，而是用于在其中限定接触面和任何其他图案。有利地，该图案通过蚀刻掩模来固定，该蚀刻掩模在组装过程之前被设置。
第二层没有被去除的事实意味着，载体接附到封装。为了确保载体合适地接附到封装，载体的第一金属层机械地锚定在封装中。为此，第一金属层和中间层构图为使得第一金属层具有相对于该中间层突出的部分。这样，这些部分在平行于载体的侧面的方向上突出。中间层最好通过蚀刻来构图，蚀刻剂使用相对于第一金属层是选择性的。这导致第一金属层一定程度的未蚀刻，发现这对于机械锚定是足够的。
载体的形成在于，每个构成层的厚度可以保持小。毕竟，机械稳定性不是由第一金属层确定，而是由载体整个确定。由于图案的分辨率也由层厚度确定，所以本发明使得可以获得具有带有很高的分辨率的第一金属层的载体。该效果使得可以进一步小型化，以及特殊确定轨道，如对于细小间距和高频应用所需要的。
该方法的优点在于，其使得可以制造多种电子器件。尤其是，该方法适用于半导体器件，而且具有传感器、微型机电系统(MEMS)元件或者显示器件的其他器件也可以通过所述方法来制造。
第一组器件是紧凑的半导体器件，其包括几个到近似四十个接触面。这是这样的情况，尤其是因为在第一金属层中可以限定高分辨率的图案，而第二金属层可以包括接触面，这些接触面足够分开，以能够使用标准的设备将焊料应用到它们上。
第二组器件包括半导体器件，其包括多于一个的电元件，这些电元件必须相互连接。由于第一和第二金属层独立地构图，所以从第一到第二元件的相互连接的轨道可以在第一金属层中限定。这些相互连接的轨道在第二金属层中的图案中没有。这样，在将焊料提供到载体的第二侧上期间，没有在这样的相互连接的轨道和电路板之间的不需要的接触的危险。
这样的应用的尤其有利的例子在这样的器件中找到，即，首先包括集成电路，此外，包括一个或者多个用于保护目的的二极管作为元件。在这样的情况下，二极管可以例如由具有SMD触点的二极管制成。
在该方法的还有的实施例中，电元件位于基片中的腔中，当围绕该元件设置封装时，所述腔被充满。该实施例对于在高功率下操作的器件特别有利，因为所述实施例使得导热层被应用到腔的底部。该实施例还适用于模块，尤其是具有诸如放大器之类的高功率元件的模块。这样，各种部件可以容纳在不同的腔中，且通过三层或者多层载体接触和导电地相互连接。还可以在第一金属层中限定接触面，以接触基片上的导体。
在优选的实施例中，蚀刻掩模具有用于焊料的粘合剂层，该粘合剂层在载体的第一侧上也存在。该实施例的第一优点在于，该粘合剂层可以在制造载体期间被沉积。第二个优点在于，该粘合剂层还可以用作蚀刻掩模。第三个优点在于，该粘合剂层可以在单个过程中设置在载体的第一侧和第二侧上。
第一金属层和中间层的构图可以在设置电元件以前在制造载体期间，以及在组装过程期间进行。如果金属层很薄，通常小于近似30微米，那么如果这些层的构图形成组装过程的一部分是有利的。在这样的情况下，在运输期间，没有载体的折断或者变形的危险。此外，也没有在第一金属层和中间层中的孔被灰尘或者其它东西污染的危险。这样的污染可能减弱载体到封装的附着。
如果在设置电元件以前，液体或者可液化的层施加到载体的第一侧也是有利的。如果使用可液化的层，在已经设置电元件以后进行加热步骤，以液化所述可液化的层。通过使用这样的在未正式出版前的专利申请EP02077228.1(PHNL020471)中描述的层，抵消了焊料或者金属隆起的变形。使用这样的金属或者焊料隆起是已知的，且对相互连接元件和第一金属层的过程具有有利的效果。或者，例如可以使用导电粘合剂或者许多结合导线来建立所述连接。
根据本发明的方法可以有利地应用，尤其是结合本发明的载体应用。
本发明的第二个目的是提供在开始的段落中提到的类型的载体，通过该载体，可以在载体上组装电元件以后，在不需要光刻步骤的情况下制造一种紧凑然而坚固的电子器件。
所述第二目的实现为，该载体包括第一蚀刻掩模、第一金属层、中间层、第二金属层和第二蚀刻掩模的堆叠，该第一蚀刻掩模位于载体的第一侧上，该第二蚀刻掩模位于载体的第二侧上。
根据本发明的载体不同于已知的载体在于，蚀刻掩模存在在第一侧以及第二侧上。由于这样，可以在第一和第二金属层中限定独立的图案。
在有利的实施例中，至少第二蚀刻掩模包括用于焊料的粘合剂层。这样的粘合剂层的例子为，其中，包含金属Ag、Pd、Au和Ni中的至少一种的层。或者，对于低共熔焊接，可以使用具有Au和Ge的合金，诸如Ti-Ni-Au-Ge。蚀刻掩模可以包括粘合剂层，但是，替代的，可以存在另外的层，诸如光致抗蚀剂。这样的光致抗蚀剂具有的优点在于，其在载体的运输期间形成用于粘合剂层的保护层。已经发现，第二金属层，例如Cu，可以以足够好的蚀刻速度和相对于该粘合剂层的蚀刻选择性来蚀刻。对于蚀刻剂，例如使用Na2S2O8/H2SO4的溶液。粘合剂层可以通过电镀之类的镀附过程来有利地根据图案设置。
在还有的实施例中，第一蚀刻掩模也具有用于焊料的粘合剂层，该粘合剂层具有与在第二蚀刻掩模中的粘合剂层相同的成分。这样的载体可以通过将整个载体浸入浴槽中来以一种简单的方式来获得。在该过程中，粘合剂层在所述载体没有被覆盖的位置处沉积在载体的第一和第二侧上。使用相同的粘合剂层的另外的优点在于蚀刻剂的数量是有限的。由于该中间层，在蚀刻第一金属层期间，第二金属层不会被腐蚀。
在特别有利的实施例中，具有Ni、Pd和Au亚层的多个层可以用作粘合剂层。该层适用于设置电元件，以及导电地连接电元件，其还适用于蚀刻掩模和焊接电子器件。
载体的中间层最优选地由可以相对于第一金属层选择性地蚀刻的材料制成。优选的使用是利用金属，其具有中间层不需要单独地构图的优点。合适的金属的例子包括Al、Al合金、FeNi、FeCrNi和不锈钢。优选的，其具有在10到100微米之间的厚度，更加优选的，在20和50微米之间的厚度。优选的，第一和第三金属层具有在5和50微米之间的厚度，进一步优选的，在10和40微米之间的厚度。
如果用作阻焊剂的金属用于中间层，尤其是导电的，但是没有经历焊料的润湿的金属或者合金是特别有利的。当利用Al或者Al的合金作为中间层，且利用Cu作为第一和第二金属层时，获得了特别有利的结果。可以使用的Al合金其中包括AlxSi1-x、AlxCu1-x和AlxGe1-x，其中，优选的，0.5≤x≤0.99。
或者，中间层可以包含绝缘材料，在这样的情况下，导电连接设置在所述中间层中。这样的导电连接这样获得，即，例如通过在构图中间层以后从溶液施加导电层，以及通过镀附过程来加固所述导电层。可以从溶液施加的导电层的例子其中包括一层导电聚合物，诸如聚乙烯二氧噻吩(PEDOT)，以及通过溶胶-凝胶处理形成的银层。该中间层可以替代地包括亚层的堆叠。
本发明的第三个目的在于提供一种制造载体的方法，通过该方法，具有需要图案的层可以以有限数量的步骤设置在两个相对的侧上：
提供第一金属层、中间层和第二金属层的堆叠，其中，第一和第二金属层导电地相互连接，以及其中该中间层包括可以相对于第一金属层选择性地蚀刻的材料，以及其中该第一金属层位于第一侧上；
在第二侧上施加和构图光敏层；以及
在第一和第二侧上为焊料电化学地设置粘合剂层。
在根据本发明的方法中，粘合剂层在单个步骤中电化学地设置在载体的两侧上。这样，具有需要功能的载体以简单的方式获得。如果使用载体，在第二侧上的粘合剂层可以用作蚀刻掩模。
在有利的实施例中，根据第一金属层需要的图案，在光敏层已经施加到所述第一侧以后，粘合剂层施加到第一侧。在施加了粘合剂层以后，去除该光敏层，在这以后，粘合剂层用作第一金属层的蚀刻掩模。该金属层通过蚀刻来构图，在这以后，通过使用相对于第一和第三金属层是选择性的蚀刻剂来蚀刻来构图该中间层。在该过程中，相对于第一金属层出现蚀刻不足。对于光敏层，利用例如Shipley的SP2029-1。在固化以后，该层显示足够的机械稳定性。这样，在将光敏层施加到第二侧期间，可以允许载体没有任何问题地位于第一侧上的显影的和构图的光敏层上。
有利的粘合剂层包括从包括Ni、Pd、Ag和Au的组中选择的一种或者多种金属。这些金属可以呈现为亚层，而且为合金。
从下文中描述的实施例，以及参考下文中描述的实施例阐明的，将明白根据本发明的载体以及制造该载体和电子器件的方法的这些和其它方面。
在附图中：
图1是该电子器件的第一个实施例的示意性的截面图；
图2是该第一实施例的示意性的平面图；
图3是该电子器件的第二个实施例的示意性的截面图；以及
图4-9示出了制造如图3中所示的载体和电子器件的方法的步骤。
这些图不是按比例绘制的。同样的标号指同样的部分。替代的实施例在后附的权利要求书的保护范围内是可能的。
图1是电子器件10的第一个实施例的示意性的截面图。在这样的情况下，所述电子器件是具有五个触点的半离散的半导体器件。然而，这决不是必要的。图2是第一个实施例的示意性平面图，其中，线A-A表示图1的截面。该半导体器件包括具有第一金属层11、中间层12和第二金属层13的载体30。在该例子中，第一和第二金属层11、13包括Cu，中间层包括Al.99Si.01。此外，载体30包括第一蚀刻掩模14和第二蚀刻掩模17。该第一和第二蚀刻掩模14、17每个包括NiPdAu的粘合剂层。载体30通过第一蚀刻掩模14从第一侧构图，从而形成开口15和连接导体31-35。为此，利用蚀刻过程，其中，首先第一金属层11被蚀刻，随后，中间层12被蚀刻，从而在连接导体31-35的侧面中形成凹进16。随后，具有连接区域21的半导体元件20通过连接装置22连接到连接导体31-35，在这样的情况下，该连接导体为Au的隆起。为此，利用倒转芯片技术。随后，设置封装40，由于封装40延伸到载体的凹进16，导致形成机械锚定。随后，第二金属层13通过第二蚀刻掩模17来构图。这通过将该器件放置在蚀刻浴槽中，其选择性地相对于中间层以及相对于第二蚀刻掩模17来去除第二金属层13来实现。开口15随后也用于分离半导体器件10。这具有另外的优点，即，机械锚定大致封闭连接导体31-35，即，不但在半导体元件20的位置，而且超过所述的元件。半导体器件10的尺寸为例如近似1乘1mm。开口15例如具有40-100微米的宽度。第一金属层11、中间层12和第二金属层13的厚度选择为分别为30微米、40微米和30微米。
图3是根据本发明的器件10，在该情况下为半导体器件的第二个实施例的示意性的截面图。该器件10包括半导体元件20，其呈现在载体30上。所述载体30具有第一侧1和第二侧2，且包括多个连接导体31、32、33。具有侧面的所述连接导体31、32、33通过开口15相互隔离。在连接导体31、32、33和在半导体元件20中的连接区域21之间有连接装置，在该情况下为结合导线22。在该例子中，半导体元件20通过粘合剂层23接附到载体30的第一侧1。半导体元件20和结合导线22由封装40来封闭。该封装40延伸到载体30的开口15中。
根据本发明，凹进16存在于连接导体31、32、33的侧面中。这些凹进16充满封装40，其结果为，第一层31由封装40部分地夹住。这确保了封装40机械地锚定在载体30中，导致极好的粘附和机械强度。在这样的情况下，不需要在载体的第一侧1上设置粘附改进装置。该第一侧1还可以优化为放置半导体元件20和结合导线22。
根据本发明的还有的特征，第二粘合剂层17存在于载体30的第二侧上，第二金属层13具有与第二粘合剂层17相同的图案。结果，可以不需要在将电元件20组装在载体30上期间所必需的光刻步骤的情况下制造该器件。第二粘合剂层17也用作用于焊料的粘合剂层，其可以用于将器件10设置在印刷电路板上。
在该实施例中，载体30包括第一金属层11、中间层12和第二金属层13。第一金属层11和第二金属层13主要包括铜，中间层12主要包括铝。在第二层12中的凹进16通过蚀刻形成，如将要参考图4-9说明的。第一和第二粘合剂层包括NiPdAu或者NiPd。如本领域中的普通技术人员可以理解的，粘合剂层14、17还可以包括不同的合适的材料。通过延伸直到载体30的第二侧的开口15，构图第二金属层13，使得形成接触面，在该情况下为双极性晶体管。连接导体32接地，且用作散热器。
图4-12示出了根据本发明的方法中的各个步骤，其导致在图1中显示的第二个实施例。图4和5涉及制造载体30的方法。图7、8和9涉及制造器件10的方法。图6涉及两个步骤，其可以在制造载体30中，以及在制造器件10中进行。这里显示的方法具有这样的优点，即，它们可以在提供封装以后不需要光刻步骤的情况下进行，同时粘附到封装40很好，且在封装步骤以前，载体30不分离。
图4示出了第一个步骤以后的载体30，在该第一个步骤中，Cu的第一金属层11、Al的中间层12和Cu的第二金属层13相互附着。可以使用中间层12作为起始层，以及提供一层Cu在其任一侧上。或者，载体30可以通过将层11、12、13轧制在一起来形成，该技术通常用于形成双层。所述轧制过程也可以在两个步骤中进行。最后形成四层或者多层载体也是可能的。在第一个实验中，层11、12、13具有70微米的厚度。然而，该厚度可以在10微米和1.0毫米之间变化，且层11-13不是必须厚度相同。如果第一金属层11相当薄，其最好由具有大的机械强度和刚性的材料制成，诸如镍铁合金。结合所述材料，铜可以用作用于中间层12的材料。可以进行热处理，以改进层11、12、13之间的粘合，如果这是必要的。
图5示出了第一蚀刻掩模14设置在第一侧1上，以及第二蚀刻掩模17设置在第二侧2上以后的载体30。所述蚀刻掩模通过连续地将光致抗蚀剂(例如，Shipley的SP2029-1)施加到第一侧1和第二侧2上，以及随后构图所述光致抗蚀剂来设置。在构图操作中，光掩模也固化。第一侧1和第二侧2具有不同的图案。在第一侧1上的光致抗蚀剂已经构图以后，载体30颠倒转向，在这之后，光致抗蚀剂施加到第二侧上。随后，Ni、Pd和Au连续地设置在载体上。Ag是替代的。在这以后，载体准备好了。优选的，去除光致抗蚀剂。然而，光致抗蚀剂还可以维持，以用作保护层。
图6示出了已经进行了下面的步骤以后的载体30。首先，去除用作保护层的光致抗蚀剂。随后，载体30在多个浴槽中处理；首先，载体30在Na2S2O4/H2SO4溶液的浴槽中在45℃下蚀刻5到10分钟。结果，根据由第一蚀刻掩模14限定的图案来蚀刻第一金属层。接下来，载体30在浓缩的KOH溶液的浴槽中处理3分钟，其结果为，Al的中间层12被蚀刻，且形成凹进16。在所述的3分钟以后，凹进具有70微米的宽度。10-20微米的宽度足够获得需要的机械锚定。这样的宽度另外具有的优点在于，连接导体可以小型化；对于具有近似100微米的宽度的连接导体，其中，凹进16形成在两侧面上，凹进的宽度最多近似30微米。
图7示出了在半导体元件20接附到载体30，以及结合导线22设置在半导体元件20的连接区域21和连接导体31、33之间以后的载体30。尽管只显示了单个元件20，但是实际上大量元件设置在载体30上，其只在后面阶段分离。
图8示出了在封装40已经设置在第一侧1上以后的载体30。由于第二金属层13还没有构图，其用作封装材料的阻挡物。该材料也进入凹进16，从而引起第一金属层11机械地锚定在封装40中。封装40设置在载体的高度。封装40和载体之间的粘合可以通过使第一金属层11，从而蚀刻掩模14设置有粗糙表面来进一步改进。然而，在必须设置导线结合的位置处，该表面通过平坦化步骤来平坦化。该平坦化步骤在载体30设置有蚀刻掩模14、17以前已经进行。对于平坦化步骤，可以利用例如滚子，其使最外面平滑，而在该表面下保持一些孔开启，用于粘合封装。
图9示出了在构图第二金属层13以后的具有元件20和封装40的载体30。这通过将载体30的第二侧2放置或者浸入Na2S2O4/H2SO4溶液的浴槽中在45℃下持续5到10分钟来实现。图案选择为使得限定分离通道，其中，载体30被完全去除。在例如通过锯沿着这些分离通道切割封装40以后，获得了完成的器件10。

Claims (12)

1.一种制造包括载体的电子器件的方法，该载体在第一和相对的第二侧之间具有第一构图的金属层、构图的中间层和第二构图的金属层以及蚀刻掩模，该第一金属层导电地连接到电元件和第二金属层，且包括相对于中间层突出的部分，
该方法包括的步骤为：
将电元件设置在载体的第一侧上，该电元件的触点导电地连接到第一金属层；
施加封装，第一金属层的突出部分在该封装中锚定，以及
根据由蚀刻掩模限定的图案来从载体的第二侧蚀刻第二金属层。
2.如权利要求1所述的方法，其特征在于，该蚀刻的掩模具有用于焊料的粘合剂层，该粘合剂层也存在于载体的第一侧上。
3.如权利要求2所述的方法，其特征在于，该第一金属层和中间层这样构图：
根据需要的图案来构图第一金属层，粘合剂层根据用作为蚀刻掩模的需要的图案呈现，以及通过蚀刻剂来构图中间层，该蚀刻剂相对于第一和第三金属层是选择性的，相对于第一金属层出现蚀刻不足。
4.一种具有第一和第二侧的载体，其包括的堆叠为：
第一蚀刻掩模，
第一金属层，
中间层，
第二金属层，以及
第二蚀刻掩模，
第一蚀刻掩模位于载体的第一侧上，第二蚀刻掩模位于载体的第二侧上。
5.如权利要求4所述的载体，其特征在于，该第一金属层和中间层构图为使得第一金属层包括相对于中间层突出的部分。
6.如权利要求4或者5所述的载体，其特征在于，该第一和第二蚀刻掩模包括用于焊料的粘合剂层。
7.如权利要求6所述的载体，其特征在于，该用于焊料的粘合剂层包括从Ag、NiPd、NiPdAu中选择的材料。
8.如权利要求4或者5所述的载体，其特征在于，该中间层包括适于用作阻焊剂的导电材料。
9.如权利要求8所述的载体，其特征在于，该中间层包括从Al、Al合金、FeNi、FeCrNi和不锈钢中选择的材料，以及第一和第三金属层包含铜。
10.一种制造具有第一侧和相对的第二侧的载体的方法，其包括的步骤为：
提供第一金属层、中间层和第二金属层的堆叠，其中，第一和第二金属层导电地相互连接，其中，该中间层包括可以相对于第一金属层选择性地蚀刻的材料，以及其中该第一金属层位于第一侧上；
在第二侧上施加和构图光敏层；以及
在第一和第二侧上电化学地设置用于焊料的粘合剂层。
11.如权利要求10所述的方法，其特征在于，在设置粘合剂层以前，光敏层设置在第一侧上，随后构图。
12.如权利要求11所述的方法，其特征在于，其另外包括的步骤为：
根据需要的图案来构图第一金属层，在该过程中，粘合剂层用作蚀刻掩模，以及
使用蚀刻剂构图中间层，该蚀刻剂相对于第一和第三金属层是选择性的，导致相对于第一金属层的蚀刻不足。
CNB038080575A 2002-04-11 2003-04-10 包括载体的电子器件和制造该电子器件的方法 Expired - Lifetime CN1315185C (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
EP02076426.2 2002-04-11
EP02076426 2002-04-11
EP02079544.9 2002-10-30
EP02079544 2002-10-30
PCT/IB2003/001299 WO2003085728A1 (en) 2002-04-11 2003-04-10 Carrier, method of manufacturing a carrier and an electronic device

Publications (2)

Publication Number Publication Date
CN1647268A true CN1647268A (zh) 2005-07-27
CN1315185C CN1315185C (zh) 2007-05-09

Family

ID=28793208

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB038080575A Expired - Lifetime CN1315185C (zh) 2002-04-11 2003-04-10 包括载体的电子器件和制造该电子器件的方法

Country Status (8)

Country Link
US (1) US7247938B2 (zh)
EP (1) EP1500137A1 (zh)
JP (1) JP4526823B2 (zh)
KR (1) KR101009818B1 (zh)
CN (1) CN1315185C (zh)
AU (1) AU2003219354A1 (zh)
TW (1) TWI280646B (zh)
WO (1) WO2003085728A1 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102408090A (zh) * 2010-09-21 2012-04-11 台湾积体电路制造股份有限公司 具有增强锚的微结构
CN108796439A (zh) * 2018-07-26 2018-11-13 京东方科技集团股份有限公司 一种掩膜板及其制作方法
CN109712930A (zh) * 2018-11-27 2019-05-03 合肥鑫晟光电科技有限公司 显示基板及其制作方法、显示装置

Families Citing this family (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8928967B2 (en) 1998-04-08 2015-01-06 Qualcomm Mems Technologies, Inc. Method and device for modulating light
WO1999052006A2 (en) 1998-04-08 1999-10-14 Etalon, Inc. Interferometric modulation of radiation
WO2003007049A1 (en) 1999-10-05 2003-01-23 Iridigm Display Corporation Photonic mems and structures
EP1579502A2 (en) * 2002-12-20 2005-09-28 Koninklijke Philips Electronics N.V. Electronic device and method of manufacturing same
US7626255B2 (en) 2003-10-15 2009-12-01 Koninklijke Philips Electronics N.V. Device, system and electric element
US8070971B2 (en) * 2004-06-04 2011-12-06 Nxp B.V. Etch method
US7944599B2 (en) 2004-09-27 2011-05-17 Qualcomm Mems Technologies, Inc. Electromechanical device with optical function separated from mechanical and electrical function
US7553684B2 (en) 2004-09-27 2009-06-30 Idc, Llc Method of fabricating interferometric devices using lift-off processing techniques
US7893919B2 (en) 2004-09-27 2011-02-22 Qualcomm Mems Technologies, Inc. Display region architectures
US7372613B2 (en) 2004-09-27 2008-05-13 Idc, Llc Method and device for multistate interferometric light modulation
US8008736B2 (en) 2004-09-27 2011-08-30 Qualcomm Mems Technologies, Inc. Analog interferometric modulator device
US7420725B2 (en) 2004-09-27 2008-09-02 Idc, Llc Device having a conductive light absorbing mask and method for fabricating same
US7289259B2 (en) 2004-09-27 2007-10-30 Idc, Llc Conductive bus structure for interferometric modulator array
US7936497B2 (en) 2004-09-27 2011-05-03 Qualcomm Mems Technologies, Inc. MEMS device having deformable membrane characterized by mechanical persistence
US7719500B2 (en) 2004-09-27 2010-05-18 Qualcomm Mems Technologies, Inc. Reflective display pixels arranged in non-rectangular arrays
TWI240400B (en) * 2005-01-04 2005-09-21 Nan Ya Printed Circuit Board C Method for fabricating a packaging substrate
TW200721426A (en) 2005-07-25 2007-06-01 Koninkl Philips Electronics Nv Air cavity package for flip-chip
US7825526B2 (en) 2005-09-30 2010-11-02 Nxp B.V. Fine-pitch routing in a lead frame based system-in-package (SIP) device
US7320901B2 (en) * 2005-10-31 2008-01-22 Taiwan Solutions Systems Corp. Fabrication method for a chip packaging structure
JP2009514241A (ja) * 2005-11-01 2009-04-02 エヌエックスピー ビー ヴィ 半導体ダイの実装方法およびダイパッケージ
JP2009514242A (ja) * 2005-11-01 2009-04-02 エヌエックスピー ビー ヴィ 半導体ダイの実装方法および半導体パッケージ
AU2006311850B2 (en) * 2005-11-02 2011-06-16 Second Sight Medical Products, Inc. Implantable microelectronic device and method of manufacture
TW200737479A (en) * 2005-11-03 2007-10-01 Koninkl Philips Electronics Nv Surface treatments for contact pads used in semiconductor chip packages and methods of providing such surface treatments
US7916980B2 (en) 2006-01-13 2011-03-29 Qualcomm Mems Technologies, Inc. Interconnect structure for MEMS device
US7649671B2 (en) 2006-06-01 2010-01-19 Qualcomm Mems Technologies, Inc. Analog interferometric modulator device with electrostatic actuation and release
US7835061B2 (en) 2006-06-28 2010-11-16 Qualcomm Mems Technologies, Inc. Support structures for free-standing electromechanical devices
US7527998B2 (en) 2006-06-30 2009-05-05 Qualcomm Mems Technologies, Inc. Method of manufacturing MEMS devices providing air gap control
US8120289B2 (en) 2006-12-06 2012-02-21 Nxp B.V. Optical electrical system in package for LED based lighting system
EP2097933A2 (en) * 2006-12-21 2009-09-09 Koninklijke Philips Electronics N.V. Carrier and optical semiconductor device based on such a carrier
US8133764B2 (en) 2007-02-14 2012-03-13 Npx B.V. Embedded inductor and method of producing thereof
WO2008099321A1 (en) 2007-02-14 2008-08-21 Nxp B.V. Dual or multiple row package
EP2137763A2 (en) 2007-04-10 2009-12-30 Nxp B.V. Package, method of manufacturing a package and frame
JP2009135417A (ja) * 2007-11-07 2009-06-18 Sumitomo Metal Mining Co Ltd 半導体素子搭載用基板の製造方法
US8115285B2 (en) 2008-03-14 2012-02-14 Advanced Semiconductor Engineering, Inc. Advanced quad flat no lead chip package having a protective layer to enhance surface mounting and manufacturing methods thereof
US20100044850A1 (en) * 2008-08-21 2010-02-25 Advanced Semiconductor Engineering, Inc. Advanced quad flat non-leaded package structure and manufacturing method thereof
US7719754B2 (en) 2008-09-30 2010-05-18 Qualcomm Mems Technologies, Inc. Multi-thickness layers for MEMS and mask-saving sequence for same
US8124447B2 (en) * 2009-04-10 2012-02-28 Advanced Semiconductor Engineering, Inc. Manufacturing method of advanced quad flat non-leaded package
US8551820B1 (en) 2009-09-28 2013-10-08 Amkor Technology, Inc. Routable single layer substrate and semiconductor package including same
US8669649B2 (en) 2010-09-24 2014-03-11 Stats Chippac Ltd. Integrated circuit packaging system with interlock and method of manufacture thereof
US8963159B2 (en) 2011-04-04 2015-02-24 Qualcomm Mems Technologies, Inc. Pixel via and methods of forming the same
US9134527B2 (en) 2011-04-04 2015-09-15 Qualcomm Mems Technologies, Inc. Pixel via and methods of forming the same
US8617933B2 (en) 2011-05-27 2013-12-31 Stats Chippac Ltd. Integrated circuit packaging system with interlock and method of manufacture thereof
CN103531670B (zh) * 2012-07-06 2016-09-07 哈尔滨化兴软控科技有限公司 发光二极管制造方法
US9911685B2 (en) 2012-11-09 2018-03-06 Amkor Technology, Inc. Land structure for semiconductor package and method therefor
KR20140060390A (ko) 2012-11-09 2014-05-20 앰코 테크놀로지 코리아 주식회사 반도체 패키지의 랜드 및 그 제조 방법과 이를 이용한 반도체 패키지 및 그 제조 방법
EP2884242B1 (en) * 2013-12-12 2021-12-08 ams International AG Sensor Package And Manufacturing Method
US9947636B2 (en) * 2014-06-02 2018-04-17 Stmicroelectronics, Inc. Method for making semiconductor device with lead frame made from top and bottom components and related devices
US9570381B2 (en) 2015-04-02 2017-02-14 Advanced Semiconductor Engineering, Inc. Semiconductor packages and related manufacturing methods
US10573583B2 (en) * 2018-06-20 2020-02-25 Texas Instruments Incorporated Semiconductor device package with grooved substrate
US11002063B2 (en) * 2018-10-26 2021-05-11 Graffiti Shield, Inc. Anti-graffiti laminate with visual indicia
US11887916B2 (en) 2020-09-09 2024-01-30 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor devices and methods of manufacturing semiconductor devices
US20220157707A1 (en) * 2020-11-17 2022-05-19 Panjit International Inc. Thin semiconductor package and manufacturing method thereof

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04328853A (ja) * 1991-04-30 1992-11-17 Mitsubishi Electric Corp リードフレーム材料およびリードフレーム
JP3065415B2 (ja) * 1991-10-09 2000-07-17 新光電気工業株式会社 リードフレーム及びその製造方法
JPH0837272A (ja) * 1994-07-21 1996-02-06 Toppan Printing Co Ltd リードフレーム及びその製造方法
JP3003624B2 (ja) * 1997-05-27 2000-01-31 ソニー株式会社 半導体装置
JPH11163024A (ja) * 1997-11-28 1999-06-18 Sumitomo Metal Mining Co Ltd 半導体装置とこれを組み立てるためのリードフレーム、及び半導体装置の製造方法
JPH11251505A (ja) * 1998-03-04 1999-09-17 Matsushita Electron Corp 半導体装置及びその製造方法
JP3780122B2 (ja) * 1999-07-07 2006-05-31 株式会社三井ハイテック 半導体装置の製造方法
US20020100165A1 (en) * 2000-02-14 2002-08-01 Amkor Technology, Inc. Method of forming an integrated circuit device package using a temporary substrate
US6451627B1 (en) * 1999-09-07 2002-09-17 Motorola, Inc. Semiconductor device and process for manufacturing and packaging a semiconductor device
JP3574026B2 (ja) * 2000-02-01 2004-10-06 三洋電機株式会社 回路装置およびその製造方法
US6306685B1 (en) * 2000-02-01 2001-10-23 Advanced Semiconductor Engineering, Inc. Method of molding a bump chip carrier and structure made thereby
EP1143509A3 (en) * 2000-03-08 2004-04-07 Sanyo Electric Co., Ltd. Method of manufacturing the circuit device and circuit device
JP3561683B2 (ja) * 2000-09-04 2004-09-02 三洋電機株式会社 回路装置の製造方法
JP2002111185A (ja) * 2000-10-03 2002-04-12 Sony Chem Corp バンプ付き配線回路基板及びその製造方法
JP2009156095A (ja) 2007-12-25 2009-07-16 Yamaha Motor Co Ltd 船外機の冷却装置

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102408090A (zh) * 2010-09-21 2012-04-11 台湾积体电路制造股份有限公司 具有增强锚的微结构
CN102408090B (zh) * 2010-09-21 2014-10-29 台湾积体电路制造股份有限公司 具有增强锚的微结构
CN108796439A (zh) * 2018-07-26 2018-11-13 京东方科技集团股份有限公司 一种掩膜板及其制作方法
CN109712930A (zh) * 2018-11-27 2019-05-03 合肥鑫晟光电科技有限公司 显示基板及其制作方法、显示装置
CN109712930B (zh) * 2018-11-27 2020-10-30 合肥鑫晟光电科技有限公司 显示基板及其制作方法、显示装置

Also Published As

Publication number Publication date
EP1500137A1 (en) 2005-01-26
JP2005522860A (ja) 2005-07-28
CN1315185C (zh) 2007-05-09
TW200401416A (en) 2004-01-16
KR101009818B1 (ko) 2011-01-19
WO2003085728A1 (en) 2003-10-16
TWI280646B (en) 2007-05-01
US20050153483A1 (en) 2005-07-14
KR20040106338A (ko) 2004-12-17
US7247938B2 (en) 2007-07-24
JP4526823B2 (ja) 2010-08-18
AU2003219354A1 (en) 2003-10-20

Similar Documents

Publication Publication Date Title
CN1315185C (zh) 包括载体的电子器件和制造该电子器件的方法
CN1215742C (zh) 印刷电路板的焊盘及其形成方法
US7365006B1 (en) Semiconductor package and substrate having multi-level vias fabrication method
US5587342A (en) Method of forming an electrical interconnect
CN1203554C (zh) 具有薄膜电路的模块
US20050151246A1 (en) Multilayer circuit carrier, panel, electronic device, and method for producing a multilayer circuit carrier
WO2006076101A2 (en) A method to manufacture a universal footprint for a package with exposed chip
EP0536418A1 (en) Semiconductor device and manufacturing method therefor
CN1341962A (zh) 半导体装置及其制造方法
JPH098213A (ja) 半導体素子の実装方法およびこの方法により製作されたマルチチップモジュール
CN1591841A (zh) 带式电路基板及使用该带式电路基板的半导体芯片封装
CN1692495A (zh) 半导体集成装置及其制造方法
CN1551344A (zh) 半导体装置和层叠型半导体装置以及它们的制造方法
KR100346899B1 (ko) 반도체장치 및 그 제조방법
CN1172358C (zh) 倒装接合结构的形成方法
CN1301544C (zh) 半导体装置的制造方法
CN100352028C (zh) 半导体装置及其制造方法
US7071571B2 (en) Semiconductor component having a plastic housing and methods for its production
US7105922B2 (en) Electrode-type heat sink
US20110220403A1 (en) Side packaged type printed circuit board
JP3405628B2 (ja) 回路基板上の端子電極とその形成方法、並びに半導体装置の実装体
CN1441470A (zh) 布线基板及其制造方法、半导体装置以及电子机器
DE4038168C2 (de) Verfahren zur Herstellung eines Multichip-Moduls
JP3497774B2 (ja) 配線基板とその製造方法
CN1301044C (zh) 电路装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: NXP CO., LTD.

Free format text: FORMER OWNER: KONINKLIJKE PHILIPS ELECTRONICS N.V.

Effective date: 20071012

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20071012

Address after: Holland Ian Deho Finn

Patentee after: NXP B.V.

Address before: Holland Ian Deho Finn

Patentee before: Koninklijke Philips Electronics N.V.

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20150914

Address after: Delaware

Patentee after: III Holdings 6 LLC

Address before: Holland Ian Deho Finn

Patentee before: NXP B.V.

CX01 Expiry of patent term

Granted publication date: 20070509

CX01 Expiry of patent term