CN1647266A - 半导体器件和半导体器件的组装方法 - Google Patents
半导体器件和半导体器件的组装方法 Download PDFInfo
- Publication number
- CN1647266A CN1647266A CNA038084864A CN03808486A CN1647266A CN 1647266 A CN1647266 A CN 1647266A CN A038084864 A CNA038084864 A CN A038084864A CN 03808486 A CN03808486 A CN 03808486A CN 1647266 A CN1647266 A CN 1647266A
- Authority
- CN
- China
- Prior art keywords
- mentioned
- semiconductor element
- semiconductor device
- resin
- flat board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 253
- 238000000034 method Methods 0.000 title claims description 22
- 229920005989 resin Polymers 0.000 claims abstract description 90
- 239000011347 resin Substances 0.000 claims abstract description 90
- 238000010438 heat treatment Methods 0.000 claims description 19
- 239000011248 coating agent Substances 0.000 claims description 11
- 238000000576 coating method Methods 0.000 claims description 11
- 230000002093 peripheral effect Effects 0.000 claims description 8
- 230000009467 reduction Effects 0.000 claims description 2
- 230000003014 reinforcing effect Effects 0.000 abstract description 10
- 230000002787 reinforcement Effects 0.000 abstract description 4
- 239000011230 binding agent Substances 0.000 abstract 2
- 239000000758 substrate Substances 0.000 description 33
- 238000005520 cutting process Methods 0.000 description 17
- 238000001179 sorption measurement Methods 0.000 description 10
- 238000005452 bending Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- 230000007246 mechanism Effects 0.000 description 6
- 230000009471 action Effects 0.000 description 5
- 238000003466 welding Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000005192 partition Methods 0.000 description 4
- 208000037656 Respiratory Sounds Diseases 0.000 description 3
- 208000034189 Sclerosis Diseases 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 238000010521 absorption reaction Methods 0.000 description 2
- 238000012423 maintenance Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000007405 data analysis Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 229910001651 emery Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 229920005749 polyurethane resin Polymers 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229920005992 thermoplastic resin Polymers 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
- H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01039—Yttrium [Y]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01075—Rhenium [Re]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/959—Mechanical polishing of wafer
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
本发明的目的在于提供在具有薄化的半导体元件的半导体器件中,防止在外缘部分附近产生的半导体元件的破损而可以确保可靠性的半导体器件。为了实现这一目的,本发明是一种在表面形成有多个外部连接用端子并进行了薄化处理的半导体元件的背面上,由树脂粘接了比该半导体元件刚性高的平板的半导体器件,其中,使平板的外形比半导体元件的外形大,并且通过用树脂覆盖半导体元件的侧面而形成加强该半导体元件的边缘部分的加强部分。
Description
技术领域
本发明涉及高可靠性的半导体器件及其组装方法。
背景技术
作为将封装的由半导体元件构成的半导体器件装配到电路基板上的结构,人们已知将在半导体器件上形成的焊料突点(凸块)等的突出电极焊接到基板上的结构。在具有这样的结构的半导体器件中,人们正在尝试尽可能地使半导体元件变薄到150μm或以下。其目的在于通过减小热循环时的应力来实现装配后的焊接可靠性。即,当在装配后环境温度变化时,由于半导体与工件的热膨胀系数之差,在半导体元件与焊料突点之间的焊接部分(结合部分)上就会产生应力。于是就想通过使半导体元件变薄来减小该应力。
下面,对由这样的薄化的半导体元件形成的装配结构参看附图进行说明。图11A是现有的装配结构的剖面图,图11B是表示现有的装配结构中的半导体元件的变形状态的图。在图11A中,在基板10上装配有半导体器件1,在半导体元件2的电路形成面上将焊料作为形成材料而设置的突点3焊接到在基板10的上表面形成的电极10a上。如上所述,以降低在半导体元件与突点的焊接部分上产生的应力为目的,对半导体元件2进行了薄化处理。
图11B表示在将具有这样的薄化处理的半导体元件2的半导体器件1装配到基板10上而形成的装配结构中,在回焊(回流焊接)后的基板10上产生热收缩应力的状态。由于半导体元件2因薄化而易于弯曲,所以半导体元件2就伴随基板10的收缩变形而变形。并且,随着薄化程度的进展在使用150μm或以下的厚度的半导体元件2的装配结构中,如图所示,半导体元件2的弯曲变形就会呈现出在各个突点3之间的半导体元件2成为凹状的弯曲形状(箭头P1的部分),薄化越好就越可以实现良好的随附性。因此,就证实了可以有效地减小在半导体元件2与突点3的焊接部分上产生的应力的程度。
但是,经实证或数据分析发现,在由上述薄化的半导体元件2形成的装配结构中存在以下的问题。如图11B所示,半导体元件2在最外周的突点3的外侧弯曲(用箭头P2表示)急剧地增大。为此,在最外周的突点3的周边处,在该突点3的外侧附近在半导体元件2的下表面会产生裂纹,因而会发生半导体元件2从该裂纹处断裂的现象。即,随着半导体元件的进一步薄化,尽管在焊料突点上产生的应力会降低,但却存在半导体元件的外缘部分附近产生局部性的破损的问题。
发明内容
本发明的目的在于,提供在具有薄化的半导体元件的半导体器件中,防止在外缘部分附近产生的半导体元件的破损而可以确保可靠性的半导体器件。
为了实现上述目的,本发明的半导体器件,是一种在表面形成有多个外部连接用端子的半导体元件的背面上,由树脂粘接比该半导体元件刚性高的结合体的半导体器件,其中,使上述结合体的外形比半导体元件的外形大,并且具有通过用上述树脂覆盖半导体元件的侧面而用于加强该半导体元件的边缘部分的加强部分。
附图说明
图1A是本发明的实施例1的半导体器件的立体图。
图1B是本发明的实施例1的半导体器件的部分剖面图。
图2A-2E是本发明的实施例1的半导体器件的组装方法的工序说明图。
图3是本发明的实施例1的半导体器件所使用的板状部件的立体图。
图4是本发明的实施例1的半导体器件的组装所使用的电子部件装载装置的立体图。
图5是本发明的实施例1的半导体器件的组装所使用的切割装置的立体图。
图6是本发明的实施例1的半导体器件的组装所使用的切割装置的部分剖面图。
图7A是本发明的实施例1的装配结构的剖面图。
图7B是本发明的实施例1的装配结构的部分剖面图。
图8A是本发明的实施例1的半导体器件的立体图。
图8B是本发明的实施例1的半导体器件的平面图。
图9A-9D是本发明的实施例2的半导体器件的组装方法的工序说明图。
图10A是本发明的实施例3的半导体器件的立体图。
图10B是本发明的实施例3的半导体器件的部分剖面图。
图11A是现有的装配结构的剖面图。
图11B是表示现有的装配结构的半导体元件的变形状态的图。
具体实施方式
实施例1.
参看图1A、1B对半导体器件进行说明。在图1A、1B中,半导体器件1具有通过树脂5将平板4(结合体)粘接到半导体元件2的背面(即,第2面)上的结构,在沿着半导体元件2的表面(即,第1面)的边缘部分形成的多个作为外部连接用端子的电极2a上形成有突点3。
在此,半导体元件2处于通过机械研磨或刻蚀等的方法进行薄化处理后的状态。一般地说,在通过突点将半导体元件装配到基板上的状态下,半导体元件的厚度尺寸越小装配后的焊接可靠性就越好。这是由于半导体元件2与基板的应力之差,而即便是应力要集中到突点3的焊接部分上,也会因半导体元件2自身在厚度方向上产生的变形(弯曲)而使应力分散的缘故。为此,在本实施例中,如上所述,对半导体元件2进行薄化处理而将厚度t1设定在10~150μm的范围内,从而使其向厚度方向的变形(弯曲)成为可能。
薄化处理是通过使用砂轮等的机械研磨对半导体元件2的电路形成面(第1面)的相反面进行粗加工,并且用干法刻蚀或用化学药液进行的湿法刻蚀进行精加工。进行机械研磨后在背面上就会形成具有多个微小裂纹的损伤层。虽然该损伤层会成为使半导体元件的抗弯强度降低的原因,但是,通过精加工除去该损伤层可以提高半导体元件2的抗弯强度。
平板4是具有使在半导体器件1的装载时等的拾取处理中容易保持半导体器件1稳定,并且保护装配到基板等上后的半导体器件1免于遭受外力影响的作用的部件。因此,作为平板4是使用金属或陶瓷或树脂等的结构材料,并将其加工成满足上述作用的形状,即,加工成具有比半导体元件2高的刚性的厚度为t2的并且比半导体元件2的外形大的外形形状。
将半导体元件2粘接到平板4上的树脂5使用低弹性系数且可变形的材料。由此,就可以在允许半导体元件2在厚度方向上产生需要量的变形的同时,将半导体元件2粘接到平板4上。即,在将半导体器件1装配到了基板上的状态下,半导体元件2就可以伴随着基板的变形而变形。
如图1所示,树脂5遍及半导体元件2的全周而从元件2的端部伸出而形成。伸出的树脂5a具有沿着半导体元件2的侧面2b向上扩展而至少部分地将侧面2b覆盖的形状。虽然并非一定要将侧面2b的厚度方向的整个面都覆盖起来,但是却要形成为覆盖平板4一侧的边缘。所谓平板4一侧的边缘是由半导体元件1的第2面与侧面2b形成的。这样,覆盖侧面2b的树脂5a起加强半导体元件2的边缘部分的加强部分的作用。
在半导体元件2的边缘部分上,在对半导体晶片进行切割以切成单片的半导体元件2时产生的微小的裂纹容易残留下来,常常会因该裂纹而产生破损。覆盖侧面2b的树脂5a具有加强含有这样的微小的裂纹的边缘部分的效果。此外,如后所述,在将半导体器件1装配到基板10上的状态下,还具有防止由于基板10与半导体元件2的热变形之差产生的应力所引起的半导体元件2过度地变形的作用(图7A、7B)。
其次,参看图2A-2E,对半导体器件1的组装方法进行说明。在图2A中,板状部件6是将构成半导体器件1的一部分的平板4切掉之前的中间部件。如图3所示,在板状部件6的上表面设置有网格状地突出的隔断部分6a,被隔断部分6a包围的凹部6b成为粘接半导体元件2的半导体元件粘接区域。如后所述,隔断部分6a具有在向凹部6b内涂布半导体元件2的粘接用的树脂5时,限制树脂5超过半导体粘接区域向周围扩展的堤坝的作用。
在与板状部件6的下表面与隔断部分6a对应的面上形成有沟部6c。沟部6c是通过在厚度尺寸为t4的板状部件6的下表面一侧切削出网格状的沟而形成的厚度尺寸t3比t4小的薄壁部分。该薄壁部分与从板状部件6分离平板4时的切割位置一致。
其次,如图2B所示,半导体元件2粘接用的树脂5通过加注器7供给板状部件6的各个凹部6b(第1工序)。在该树脂5的涂布中,通过在凹部6b的周围设置作为堤坝部分的隔断部分6a,可以防止树脂5超过半导体粘接区域而向周围扩展。
此外,在进行涂布时,使从加注器7喷出覆盖半导体元件2的侧面2b所需要的适当涂布量的树脂5,以使在涂布后被半导体元件2挤压扩展的树脂5从半导体元件2的端部向外侧延伸出来。
然后,供给了树脂5的板状部件6被送往粘贴半导体元件的第2工序。在第2工序中,如图2C、2D所示,将半导体元件2装载到涂布在板状部件6上的树脂5上(装载工序),接着,通过加热树脂5(加热工序)而使树脂5热硬化,在对准状态下由树脂5将多个半导体元件2的背面一侧粘接到板状部件6的各个凹部6b上。
下面,参看图4对在该装载工序中半导体元件2的装载所使用的电子部件装载装置进行说明。在图4中,将网格状地粘贴了半导体元件2的粘贴片12装设到部件供给工作台11上。在部件供给工作台11的下方,设置半导体元件剥离机构13。当由半导体元件剥离机构驱动部14驱动半导体元件剥离机构13时,弹射针机构13a向上顶压粘贴片12的下表面。由此,半导体元件2就被从粘贴片12的上表面剥离,并由装载头16拾取。
在部件供给工作台11的侧方设置有基板保持部15,供给树脂后的板状部件6被保持在基板保持部15上。在部件供给工作台11和基板保持部15的上方设置有由装载头驱动部19驱动的装载头16。装载头16具有吸附嘴8,其从粘贴片12上拾取半导体元件2并装载到基板保持部15上的板状部件6上。
在部件供给工作台11的上方接地的摄像机17,对粘贴在粘贴片12上的半导体元件2进行拍摄。通过摄像机17拍摄的图像由半导体元件识别部20进行识别处理,以识别粘贴片12上的半导体元件2的位置。位置识别结果被送往控制部21,并且被送往半导体元件剥离机构驱动部14。通过控制部21根据该位置识别结果控制装载头驱动部19,使在由装载头16进行半导体元件2的拾取时,吸附嘴8和弹射针机构13a与作为拾取对象的半导体元件2位置对准。
在基板保持部15的上方具备的摄像机18,对保持在基板保持部15上的板状部件6进行拍摄。通过装载位置识别部22对由摄像机18拍摄的图像进行识别处理,检测板状部件6上的半导体元件装载位置。位置识别结果被送往控制部21,通过控制部21根据该位置识别结果控制装载头驱动部19,使在由装载头16进行半导体元件2的装载时,保持在吸附嘴8上的半导体元件2与所检测出的装载位置对准。
在通过该电子部件装载装置将半导体元件2装载到板状部件6上时,如图2C所示,用吸附嘴8吸附保持半导体元件2的形成突点3的表面(第1面)一侧,将半导体元件2的背面(第2面)推压到树脂5上。这时,通过根据树脂5的涂布量调整吸附嘴8的推压高度,使在各个半导体元件2的边缘部分外侧(箭头P3的部分)延伸出来的树脂5沿着半导体元件2的侧面2b向上扩展以覆盖侧面2b(参看图1B所示的树脂5a)。这时,只要易于残留切割时的损伤的半导体元件2的背面一侧的端部被完全覆盖而得到加强,完全覆盖侧面2b或仅仅部分地覆盖都可以。
在本实施例中,由于用装载头16将半导体元件2一个一个地边推压边装载到树脂5上,故与集中装载(粘贴)时相比可以减小装载负荷(推压力)。因此,作为电子部件装载装置,可以沿用芯片焊接装置或芯片装配机等。
这样,装载了半导体元件2的板状部件6被送往加热炉。然后,通过在这里以指定温度进行加热,如图2D所示,使树脂5热硬化。这时,伸出到各个半导体元件2的边缘部分外侧的树脂5,由于在热硬化的过程中暂时地降低粘度而借助于表面张力进一步地沿着半导体元件2的侧面2b向上扩展,保持覆盖侧面2b的形状而硬化。由此,在树脂5硬化后,就可以形成作为图1B所示的加强部分的树脂5a。于是,第2工序结束。
另外,在上述实施例中,虽然通过在半导体元件2装载后将板状部件6送往加热炉使树脂5热硬化,但是作为装载头16也可以使用内置加热装置的装置,而边装载半导体元件2边进行加热。
即,用内置于装载头16的加热装置加热保持半导体元件2的吸附嘴8,通过吸附嘴8和半导体元件2传导热可以加热树脂5。此外,也可以将从装载头16布设的加热线圈等配置在吸附嘴8的周围而直接加热吸附嘴8。即,通过使由装载头16和吸附嘴8构成的装载装置具备加热装置,同时进行装载工序和加热工序。
在由装载头16进行加热的情况下,也可以省略图2D所示的专用的加热工序,这样,则具有因省略加热炉而可以实现设备的简化的优点。但是,在该情况下,由于装载头16的操作节拍时间会受热硬化时间的制约,故整体的生产性与装载工序和加热工序分别地进行的情况相比降低了。此外,作为树脂5在上述实施例中虽然例示的是使用热硬化性树脂的例子,但是,也可以代之而使用热可塑性树脂。
这样,树脂5硬化后的板状部件6被送往切割工序,如图2E所示,由旋转切割刀片24a在相邻的半导体元件2之间的切割位置处将粘接半导体元件2的板状部件6切割(第3工序)。由此,板状部件6被切割分离成各各半导体元件2的平板4,从而完成半导体器件1的组装。
下面,参看图5、图6对该切割工序进行说明。图5表示在该切割工序所使用的切割装置。在基板固定部23的上表面,装载半导体元件2并且树脂硬化结束后的板状部件6被放置到基板固定部23上。在基板固定部23的上方设置有具备旋转切割刀片24a的切割头24,并通过边使旋转切割刀片24a旋转,边使切割头24在X方向、Y方向上移动,沿着与沟部6c一致的切割位置切割板状部件6。
如图6所示,在基板固定部23的上表面与板状部件6上的半导体元件2对应的每一个位置上都设置有吸引保持部25,在吸引保持部25的上表面形成有吸引沟25a。吸引沟25a与设置在基板固定部23的内部的吸引孔23a连通,吸引孔23a进而与真空吸引源26连接。通过在使板状部件6的下表面与吸引保持部25接触的状态下驱动真空吸引源26,由吸引保持部25吸附保持板状部件6,从而固定板状部件6的位置。
然后,使旋转切割刀片24a定位到位置被固定的板状部件6的隔断部分6a的位置上,并通过使旋转切割刀片24a边旋转边下降,切断沟部6c内的薄壁部分。这时,通过使用刀片宽度比相邻的半导体元件2间的间隔小的旋转切割刀片24a,切割板状部件6以使被分离成单片后的平板4具有从半导件元件2的端面伸出的形状。因此,在分离成单片的半导体器件1上,平板4的外形要比半导体元件2的外形大。
此外,在进行这种切割时,通过预先在下表面形成沟部6c,使旋转切割刀片24a所切割的部分的厚度变小。由此,可以使在切割工序中的旋转切割刀片24a所需要下降量尽可能地减小,从而可以防止在切割刀片下降时因刀刃接触到基板固定部23而引起的破损事故。
其次,参看图7A、7B对将上述的半导体器件1装配到基板上形成的电子部件装配结构进行说明。
如图7A所示,通过以焊料焊接方式将突点3连接到在基板10的上表面形成的电极10a上,半导体器件1被装配到基板10上。图7B表示位于突点3外侧的半导体元件2的变形状态。在通过突点3将本实施例所示的薄化的半导体元件2焊接到基板10上结构中,由于半导体元件2与基板10的热变形差所产生的应力,使突点3外侧的范围倾向于向基板10一侧发生大的弯曲。图7B的虚线示出了弯曲的状态。由于该变形,在突点3的外侧附近在半导体元件2的下表面上就会产生大的表面应力,因而会成为使半导体元件2破损的原因。
对此,如本实施例所示,在将由覆盖半导体元件2的侧面2b的树脂5a加强的半导体器件1装配到基板10上的情况下,可以大幅度地减小突点3的外侧的范围内的半导体元件2向下方的弯曲。即,树脂5a所起的作用是将半导体元件2的侧面2b覆盖以防止半导体元件2的过度的弯曲变形。因此,借助于该作用,可以防止半导体元件2向下方的弯曲变形,从而可以防止半导体元件2因弯曲变形而破损。
另外,如图8A、8B所示的半导体器件101,也可以将从半导体元件2的边缘部分的树脂5a的伸出限定在半导体元件2的对角线方向上,使得仅仅在半导体元件2的角部上形成用树脂5a覆盖半导体元件2的侧面的加强部分。在这种情况下,在图2B中,在由加注器7涂布树脂5时,以使树脂5仅仅涂布在图8B所示的范围内的方式,将加注器7的涂布轨迹设定成X形状,并且控制加注器7的喷出量。这样,通过将加强部分的形成范围限定在半导体元件2的角部,可以重点地加强在半导体器件制成后的装配状态下最易于破损的角部。
实施例2.
下面,参看图9A-9D对实施例2进行说明。
在本发明的实施例2中,在向板状部件供给树脂的第1工序中,不使用加注器而是粘贴预先形成片状的树脂。
在图9A中,板状部件6A处于去除了实施例1所示的板状部件6的上表面的隔断部分6a的状态,在板状部件6A的下表面形成有同样的沟部6c。在板状部件6A的上表面粘贴了树脂片5A。树脂片5A是将与在实施例1中使用的树脂5同样的树脂材料形成为片状的部件,并借助于树脂5自身的粘合性粘贴在板状部件6A上。
然后,粘贴了树脂片5A的板状部件6被送往粘接半导体元件的第2工序。在该第2工序中,如图9B、9C所示,将半导体元件2的第2面装载到粘贴在板状部件6上的树脂片5A上(装载工序),接着加热树脂片5A(加热工序),使树脂片5A的树脂成分热硬化。由此,通过热硬化的树脂片5A将多个半导体元件2的第2面(背面)在对准状态下粘接在板状部件6上。
在上述的加热工序中,通过由加热炉在指定温度进行加热,使树脂片5A的树脂成分热硬化。这时,位于各个半导体元件2的边缘部分外侧的树脂5在热硬化的过程中粘度会暂时地降低,因此其流动性增强而借助于表面张力沿着半导体元件2的侧面2b向上扩展。进而,通过继续加热,树脂片5A的树脂成分就保持将侧面2b覆盖的形状而硬化。由此,在树脂片5A硬化后,就形成图1B所示的作为加强部分的树脂5a。于是,第2工序结束。
这样,树脂片5A完全硬化的板状部件6A被送往切割工序,在这里,在相邻的半导体元件2之间切割粘接了半导体元件2的板状部件6A(第3工序)。由此,板状部件6A被切割分离成各个半导体元件2的平板4,从而完成半导体器件1的组装。
实施例3.
下面,用图10A、10B对实施例3的半导体器件进行说明。在图10A中,半导体器件103具有由树脂5将平板4(结合体)粘接在具有再布线层的半导体元件30的背面(即,第2面)上的结构,在具有再布线层的半导体元件30的表面上网格状地形成有多个突点3。如图10B所示,具有再布线层的半导体元件30具有,在与实施例1所示的半导体元件2同样地进行了薄化处理的半导体元件2A的上表面(电极形成面)形成了再布线层9的结构。
在半导体元件2A的表面(即第1面)的边缘部分上,形成有作为外部连接用端子的电极2a,各个电极2a通过内部布线9b与在再布线层9的表面形成的与电极2a对应个数的电极9a导通。此外,在电极9a上,形成有用来装配半导体器件103的突点3。
在实施例3中,通过设置再布线层9,可以与实施例1所示半导体器件1相比在同一投影面积内形成更多的突点3,从而可以实现更高密度的装配。组装该半导体器件103,只要在实施例1、2所示的半导体器件的组装方法中,将半导体元件2置换成具有再布线层的半导体元件30即可。
由此,在具有再布线层的半导体元件30的侧面30a上,形成伸出的树脂5a覆盖侧面30a的加强部分。在具有这样的结构的半导体器件103中,通过形成覆盖具有再布线层的半导体元件30的侧面30a的加强部分,如上所述,可以防止在装配后在具有再布线层的半导体元件30的边缘部分上产生的弯曲变形,从而可以防止再布线层9内的内部布线9b的断裂。
在以上所说明的实施例中,作为树脂使用市面上销售的环氧树脂、丙烯酸树脂、聚氨酯树脂、硅树脂可以得到同样的效果。但是,本发明并不局限于这些树脂。
本发明的半导体器件具有,使通过树脂粘接到半导体元件上的结合体的外形比半导体元件的外形大,并且,用树脂将半导体元件的侧面覆盖而形成加强半导体元件的边缘部分的加强部分的结构。因此,可以防止在外缘部分附近发生的半导体元件的破损以确保装配后的可靠性。
此外,所使用的组装方法包括:向成为结合体的板状部件供给树脂的工序;由树脂在对准状态下将半导体元件的背面一侧粘接在板状部件上的工序;以及在相邻的半导体元件之间切割粘接了半导体元件的板状部件的工序。这样,可以容易有效地组装将薄化的半导体元件粘接在结合体上的半导体器件。
Claims (20)
1.一种半导体器件,具有:
具有形成了外部连接用端子的第1面和与上述第1面相对的第2面的半导体元件;
与上述第2面相对的平板;以及
粘接上述第2面与上述平板的树脂;
其特征在于:
上述平板具有比上述半导体元件高的刚性;
上述平板的外形比上述半导体元件的外形大;
上述树脂覆盖上述半导体元件的外缘部分。
2.根据要求1所述的半导体器件,其特征在于:
上述树脂覆盖由上述半导体元件的侧面和上述第2面所形成的边缘。
3.根据要求1所述的半导体器件,其特征在于:
上述树脂覆盖上述半导体元件的全周。
4.根据要求1所述的半导体器件,其特征在于:
上述树脂只覆盖上述半导体元件的角部。
5.根据要求1所述的半导体器件,其特征在于:
上述半导体元件的厚度大于等于10μm且小于等于150μm。
6.根据要求1所述的半导体器件,其特征在于:
在上述外部连接端子上形成有突点。
7.根据要求1所述的半导体器件,其特征在于:
在被上述第2面和上述平板所夹的部分,可以允许上述树脂向上述半导体元件的厚度方向变形。
8.根据要求5所述的半导体器件,其特征在于:
在上述外部连接端子上形成有突点,在被上述第2面和上述平板所夹的部分,可以允许上述树脂向上述半导体元件的厚度方向变形。
9.根据要求1所述的半导体器件,其特征在于:
上述半导体元件,在上述第1面上具有再布线层;上述再布线层具有在表面上形成的表面电极和在内部形成的内部电极;上述内部电极将上述表面电极和上述外部连接用电极连接。
10.根据要求9所述的半导体器件,其特征在于:
在上述表面电极上形成有突点。
11.一种半导体器件的组装方法,其用树脂将半导体元件和比上述半导体元件刚性高的平板粘接而形成半导体器件,
其中,上述半导体元件具有形成了外部连接用端子的第1面和与上述第1面相对的第2面,上述第2面与上述平板粘接,
该组装方法包括:
向包含上述平板的板状部件供给上述树脂的第1工序;
在位置对准的状态下用上述树脂粘接上述第2面与上述平板的第2工序;以及
从上述板状部件切割上述平板的第3工序。
12.根据权利要求11所述的半导体器件的组装方法,其特征在于:
在上述第2工序中,上述树脂覆盖上述半导体元件的外缘部分而形成。
13.根据权利要求12所述的半导体器件的组装方法,其特征在于:
利用由加热产生的上述树脂的粘度的降低使上述树脂在上述半导体元件的侧面上扩展而覆盖上述外缘部分。
14.根据权利要求11所述的半导体器件的组装方法,其特征在于:
上述第1工序是供给覆盖上述半导体元件的侧面的所需要量的树脂的工序。
15.根据权利要求11所述的半导体器件的组装方法,其特征在于:
在上述第1工序中所供给的上述树脂为液状,上述板状部件具有包围上述平板的突起部分,向上述突起部分的内侧供给上述液状的树脂。
16.根据权利要求11所述的半导体器件的组装方法,其特征在于:
上述树脂为片状,上述第1工序是在上述板状部件上粘贴上述片状的树脂的工序。
17.根据权利要求11所述的半导体器件的组装方法,其特征在于:
上述板状部件具有多个上述平板,上述第2工序包括:通过上述树脂将上述半导体元件装载到上述板状部件所具有的每一个上述平板上的工序;以及加热装载了上述半导体元件的上述板状部件的工序。
18.根据权利要求17所述的半导体器件的组装方法,其特征在于:
上述第2工序同时进行上述装载的工序和上述加热的工序。
19.根据权利要求18所述的半导体器件的组装方法,其特征在于:
上述第2工序用具有加热装置的上述半导体元件的装载装置进行。
20.根据权利要求11所述的半导体器件的组装方法,其特征在于:
上述半导体元件在上述第1面上具有再布线层。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP114538/2002 | 2002-04-17 | ||
JP114539/2002 | 2002-04-17 | ||
JP2002114539A JP3826831B2 (ja) | 2002-04-17 | 2002-04-17 | 半導体装置の組立方法 |
JP2002114538A JP2003309216A (ja) | 2002-04-17 | 2002-04-17 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1647266A true CN1647266A (zh) | 2005-07-27 |
CN100409430C CN100409430C (zh) | 2008-08-06 |
Family
ID=29253571
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB038084864A Expired - Fee Related CN100409430C (zh) | 2002-04-17 | 2003-04-14 | 半导体器件和半导体器件的组装方法 |
Country Status (7)
Country | Link |
---|---|
US (1) | US7446423B2 (zh) |
EP (1) | EP1487014A4 (zh) |
KR (1) | KR100593407B1 (zh) |
CN (1) | CN100409430C (zh) |
AU (1) | AU2003236251A1 (zh) |
TW (1) | TWI229396B (zh) |
WO (1) | WO2003088355A1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101894819A (zh) * | 2009-05-18 | 2010-11-24 | 富士通株式会社 | 基板结构 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009099838A (ja) * | 2007-10-18 | 2009-05-07 | Nec Electronics Corp | 半導体装置およびその製造方法 |
KR101287582B1 (ko) * | 2008-07-07 | 2013-07-19 | 삼성테크윈 주식회사 | 칩 마운터 및 칩 마운터의 bga 패키지 인식 방법 |
US8022538B2 (en) * | 2008-11-17 | 2011-09-20 | Stats Chippac Ltd. | Base package system for integrated circuit package stacking and method of manufacture thereof |
US8455991B2 (en) * | 2010-09-24 | 2013-06-04 | Stats Chippac Ltd. | Integrated circuit packaging system with warpage control and method of manufacture thereof |
US8746310B2 (en) * | 2011-05-31 | 2014-06-10 | The United States of America, as represented by the Secretary of Commerce, The National Instutute of Standards and Technology | System and method for probe-based high precision spatial orientation control and assembly of parts for microassembly using computer vision |
Family Cites Families (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5521128A (en) * | 1978-08-02 | 1980-02-15 | Hitachi Ltd | Lead frame used for semiconductor device and its assembling |
JPH02192195A (ja) | 1989-01-19 | 1990-07-27 | Sharp Corp | 複数の回路基板の接続構造 |
JPH0737768A (ja) * | 1992-11-26 | 1995-02-07 | Sumitomo Electric Ind Ltd | 半導体ウェハの補強方法及び補強された半導体ウェハ |
DE69534582T2 (de) * | 1994-05-19 | 2006-07-20 | Canon K.K. | Photovoltaisches Bauelement, Elektrodenstruktur desselben und Herstellungsverfahren |
JPH0831872A (ja) | 1994-07-13 | 1996-02-02 | Hitachi Ltd | 半導体装置 |
US5844309A (en) * | 1995-03-20 | 1998-12-01 | Fujitsu Limited | Adhesive composition, semiconductor device using the composition and method for producing a semiconductor device using the composition |
JP2828021B2 (ja) * | 1996-04-22 | 1998-11-25 | 日本電気株式会社 | ベアチップ実装構造及び製造方法 |
JPH10135386A (ja) | 1996-10-29 | 1998-05-22 | Taiyo Yuden Co Ltd | 半導体ベアチップの製造方法 |
JPH10242333A (ja) * | 1997-03-01 | 1998-09-11 | Nitto Denko Corp | 半導体装置及び半導体装置の製造方法 |
JPH10284634A (ja) | 1997-04-03 | 1998-10-23 | Matsushita Electron Corp | 半導体装置およびその製造方法 |
JP3889856B2 (ja) * | 1997-06-30 | 2007-03-07 | 松下電器産業株式会社 | 突起電極付きプリント配線基板の製造方法 |
JP2907195B2 (ja) * | 1997-10-21 | 1999-06-21 | 日本電気株式会社 | 半導体装置の製造方法 |
US6064114A (en) * | 1997-12-01 | 2000-05-16 | Motorola, Inc. | Semiconductor device having a sub-chip-scale package structure and method for forming same |
JPH11251360A (ja) * | 1998-03-04 | 1999-09-17 | Toshiba Corp | 半導体装置およびその製造方法 |
EP0990942A4 (en) * | 1998-03-19 | 2005-07-20 | Matsushita Electric Ind Co Ltd | Liquid crystal display and method for the production thereof |
JP3205536B2 (ja) * | 1998-03-19 | 2001-09-04 | 松下電器産業株式会社 | 液晶表示素子およびその製造方法 |
US6175075B1 (en) * | 1998-04-21 | 2001-01-16 | Canon Kabushiki Kaisha | Solar cell module excelling in reliability |
JP2000100851A (ja) * | 1998-09-25 | 2000-04-07 | Sony Corp | 半導体部品及びその製造方法、半導体部品の実装構造及びその実装方法 |
JP3661444B2 (ja) * | 1998-10-28 | 2005-06-15 | 株式会社ルネサステクノロジ | 半導体装置、半導体ウエハ、半導体モジュールおよび半導体装置の製造方法 |
JP2001203298A (ja) * | 2000-01-19 | 2001-07-27 | Hitachi Ltd | 半導体装置およびその製造方法 |
US6656765B1 (en) * | 2000-02-02 | 2003-12-02 | Amkor Technology, Inc. | Fabricating very thin chip size semiconductor packages |
JP3580244B2 (ja) | 2000-11-02 | 2004-10-20 | 松下電器産業株式会社 | 半導体装置および半導体装置の製造方法 |
JP3580240B2 (ja) | 2000-10-20 | 2004-10-20 | 松下電器産業株式会社 | 半導体装置および半導体装置の製造方法 |
TW522531B (en) | 2000-10-20 | 2003-03-01 | Matsushita Electric Ind Co Ltd | Semiconductor device, method of manufacturing the device and mehtod of mounting the device |
JP2002270638A (ja) * | 2001-03-06 | 2002-09-20 | Nec Corp | 半導体装置および樹脂封止方法および樹脂封止装置 |
US6617655B1 (en) | 2002-04-05 | 2003-09-09 | Fairchild Semiconductor Corporation | MOSFET device with multiple gate contacts offset from gate contact area and over source area |
JP4056854B2 (ja) * | 2002-11-05 | 2008-03-05 | 新光電気工業株式会社 | 半導体装置の製造方法 |
-
2003
- 2003-04-14 AU AU2003236251A patent/AU2003236251A1/en not_active Abandoned
- 2003-04-14 WO PCT/JP2003/004693 patent/WO2003088355A1/ja active IP Right Grant
- 2003-04-14 CN CNB038084864A patent/CN100409430C/zh not_active Expired - Fee Related
- 2003-04-14 KR KR1020047016582A patent/KR100593407B1/ko not_active IP Right Cessation
- 2003-04-14 EP EP03746477A patent/EP1487014A4/en not_active Withdrawn
- 2003-04-14 US US10/509,025 patent/US7446423B2/en not_active Expired - Lifetime
- 2003-04-15 TW TW092108718A patent/TWI229396B/zh not_active IP Right Cessation
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101894819A (zh) * | 2009-05-18 | 2010-11-24 | 富士通株式会社 | 基板结构 |
CN101894819B (zh) * | 2009-05-18 | 2012-07-25 | 富士通株式会社 | 基板结构 |
Also Published As
Publication number | Publication date |
---|---|
US20050116323A1 (en) | 2005-06-02 |
WO2003088355A1 (fr) | 2003-10-23 |
TW200406854A (en) | 2004-05-01 |
TWI229396B (en) | 2005-03-11 |
KR20040105879A (ko) | 2004-12-16 |
CN100409430C (zh) | 2008-08-06 |
EP1487014A1 (en) | 2004-12-15 |
KR100593407B1 (ko) | 2006-06-28 |
AU2003236251A1 (en) | 2003-10-27 |
US7446423B2 (en) | 2008-11-04 |
EP1487014A4 (en) | 2009-12-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101657890B (zh) | 带粘接剂芯片的制造方法 | |
CN100347845C (zh) | 制造半导体器件的方法 | |
CN1591884A (zh) | 固态象传感装置的制造方法 | |
US20060053607A1 (en) | Productoin method for surface-mounted saw device | |
CN1350329A (zh) | 半导体装置及其制造方法和安装方法 | |
CN1203740C (zh) | 柔性基板的制造方法 | |
CN1855363A (zh) | 支承板分离装置及使用该装置的支承板分离方法 | |
CN1622304A (zh) | 倒装芯片接合方法和用于柱型凸起的衬底分层金属架构 | |
JP2830852B2 (ja) | 電子部品実装方法 | |
JP4372605B2 (ja) | 電子部品搭載装置および電子部品搭載方法 | |
WO2005029574A1 (ja) | コレット、ダイボンダおよびチップのピックアップ方法 | |
CN1647266A (zh) | 半导体器件和半导体器件的组装方法 | |
CN1155997C (zh) | 各向异性导电膜、半导体芯片的安装方法和半导体装置 | |
CN1296978C (zh) | 半导体器件的制造方法及半导体制造装置 | |
CN1713346A (zh) | 接合装置、接合方法和用于制造半导体器件的方法 | |
CN1578584A (zh) | 用于结合加强板的方法 | |
JP3894097B2 (ja) | 半導体装置 | |
US7284686B2 (en) | Mounting method of bump-equipped electronic component and mounting structure of the same | |
JP3649129B2 (ja) | 半導体装置の製造方法および半導体装置 | |
CN1564755A (zh) | 印刷用版、电路基板以及对电路基板的印刷方法 | |
JP3826831B2 (ja) | 半導体装置の組立方法 | |
JPS61210650A (ja) | 半導体装置の製造方法 | |
CN101048031A (zh) | 印刷用版、电路基板以及对电路基板的印刷方法 | |
JP2008042430A (ja) | Sawデバイス、及びその製造方法 | |
JP3858719B2 (ja) | 半導体装置用の補強材 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080806 |