CN1531043A - 电子装置的制造方法及芯片载架 - Google Patents

电子装置的制造方法及芯片载架 Download PDF

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CN1531043A
CN1531043A CNA2004100283717A CN200410028371A CN1531043A CN 1531043 A CN1531043 A CN 1531043A CN A2004100283717 A CNA2004100283717 A CN A2004100283717A CN 200410028371 A CN200410028371 A CN 200410028371A CN 1531043 A CN1531043 A CN 1531043A
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chip element
electronic installation
insulation division
substrate
electrode
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CN1300832C (zh
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桥元伸晃
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Seiko Epson Corp
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Seiko Epson Corp
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Abstract

在形成于基板20中的配线图案22中，通过焊剂材料形成外部端子36。之后，将具有电.14的芯片零件10装载在基板20上。以比焊剂材料的熔点低的温度，形成电连接电极14与配线图案22的配线34。

Description

电子装置的制造方法及芯片载架
技术领域
本发明涉及一种电子装置的制造方法及芯片载架。
背景技术
在现有COB(Chip On Board)安装中，因伴随高温加工，所以不能使用热可塑性基板，也难以使用廉价的基板。另外，因对半导体芯片加高温，所以难以消除应力产生所导致的不良影响。而且，因为安装工序包含高温加工，所以使用焊剂材料的外部端子的形成必需最后进行，工序顺序受到限制。
发明内容
本发明的目的在于可减少对基板耐热性的要求，并可减少半导体芯片的应力的产生，使工序顺序具有弹性。
(1)根据本发明的电子装置的制造方法，包括：
在形成于基板中的配线图案中形成外部端子；和
之后，将具有电极的芯片零件装载在所述基板上，以比所述外部端子的熔点低的温度，形成电连接所述电极与所述配线图案的配线。
根据本发明，因为以比焊剂材料的熔点低的温度进行配线形成工序，所以可减少对基板耐热性的要求，并可减少芯片零件的应力的产生。另外，因为在芯片零件的装载工序之前进行使用焊剂材料的外部端子的形成，所以可使工序顺序具有弹性。
(2)在该电子装置的制造方法中，
也可以由包含导电性微粒子的分散液形成所述配线。
(3)在该电子装置的制造方法中，
还包含在所述芯片零件的侧面形成绝缘部，形成所述配线的工序，也可以包括向所述绝缘部及所述配线图案上喷出包含所述导电性微粒子的所述分散液。
(4)在该电子装置的制造方法中，
也可以由树脂形成所述绝缘部。
(5)在该电子装置中，
也可以形成为所述绝缘部具有从所述芯片零件向外下降的倾斜面。
(6)在该电子装置中，
所述芯片零件是半导体元件。
(7)根据本发明的芯片载架，具有
由焊剂材料形成于在基板上形成的配线图案中的外部端子；和与具有电极的芯片零件的所述电极连接的区域。
附图说明
图1是图2的I-I线截面图。
图2是说明根据本发明实施方式的电子装置的平面图。
图3A-图3C是说明根据本发明实施方式的电子装置的制造方法的图。
图4是说明根据本发明实施方式的电子装置的变形例的图。
图5是说明根据本发明实施方式的电子装置的变形例的图。
图6是说明根据本发明实施方式的电子装置的变形例的图。
图7是说明根据本发明实施方式的电子装置的变形例的图。
图8是说明根据本发明实施方式的电子装置的变形例的图。
图9A-图9B是说明图8所示芯片零件的制造方法的图。
图10是说明根据本发明实施方式的电子装置的变形例的图。
图11是说明根据本发明实施方式的电子装置的变形例的图。
图12是说明根据本发明实施方式的电子装置的变形例的图。
图13是说明根据本发明实施方式的电子装置的变形例的图。
图14是表示安装根据本实施方式的电子装置的电路基板图。
图15是表示具有根据本实施方式的电子装置的电子仪器图。
图16是表示具有根据本实施方式的电子装置的电子仪器图。
实施方式
下面，参照附图说明本发明的实施方式。
图1是说明根据本发明实施方式的电子装置图，是图2I-I线截面图。图2是说明根据本发明实施方式的电子装置的平面图。
电子装置具有芯片零件10。芯片零件10可以是半导体零件(例如半导体芯片)等的主动零件(例如集成电路零件等)。在芯片零件10中也可形成未图示的集成电路。在芯片零件10是半导体芯片的情况下，可称电子装置为半导体装置。芯片零件10也可以是被动零件(电阻器、电容器、电感线圈等)。
在芯片零件10的第1面12上，形成多个电极14。第1面12可以是四边形(例如矩形)。多个电极14也可以形成在第1面12的周围部(端部)。例如，可将多个电极14沿第1面12的四边排列，也可以沿二边排列。在第1面12的中央部至少配置1个电极14。
在第1面12上可以形成至少用1层构成的钝化膜16。钝化膜16是电绝缘膜。钝化膜16也可以仅用不是树脂的材料(例如SiO2或SiN)形成，而且在其上还包含用树脂(例如聚酰亚胺树脂)构成的膜。在钝化膜16上，形成使电极14的至少一部分(例如中央部)露出的开口。即，使钝化膜16避开电极14的至少中央部而形成。在电极14的端部也可以安装钝化膜16。钝化膜16也可以覆盖第1面12的全部周围部。
在芯片零件10的第2面(与第1面12相反侧的面)18上，不形成电极。第2面18与未图示的集成电路可电连接，也可不连接。在第2面18上可形成钝化膜(电绝缘膜)，也可不形成。第2面18也可由半导体(或导体)形成。在芯片零件10的侧面(除第1及第2面12、18的面)，可形成钝化膜(电绝缘膜)，也可不形成。在芯片零件10的侧面，不形成电极。芯片零件10的侧面可由半导体(或导体)形成。
电子装置具有基板20。在基板20上形成配线图案22。配线图案22包含在基板20的一面上露出的露出部24。在露出部24上设置用于芯片零件10与配线图案电连接的配线34。露出部24也可具有未图示的岸面(land)(宽度比线宽的部分)。
形成配线图案22的基板20可称作配线基板。配线基板也可以是多层基板(含两面基板)。多层基板包含多层(2层以上-“以上”含义为“大于等于”)的导体模型。此时，配线图案22也可包含在与露出部24露出的面相反侧的第2面露出的第2露出部26。另外，配线图案22也可包含内置于基板20内的导体模型28。配线基板也可是零件内置型配线基板。详细地说，在基板20的内部，在导体模型28上电连接电阻器、电容器、电感线圈等被动零件或集成电路零件等主动零件。或者，通过用高电阻值材料形成导体模型28的一部分，也可形成电阻器。
在基板20上装载芯片零件10。芯片零件10的第2面18与基板20(详细地说为形成其露出部24的面)相向。粘接层29可介于芯片零件10与基板20之间。粘接层29也可由粘接剂形成。粘接层29若具有导电性，则能电连接露出部24与芯片零件10的第2面18。另外，粘接层29若具有电绝缘性，则能电绝缘露出部24与芯片零件10的第2面18。粘接层29也可以由分散导电粒子的电绝缘性树脂形成。
电子装置具有绝缘部30。绝缘部30由具有电绝缘性的材料(例如树脂)形成。绝缘部30也可用与粘接层29不同的材料形成。绝缘部30设置于芯片零件10的附近。绝缘部30也可以围绕芯片零件10设置，也可仅设置于芯片零件10的电极14附近。绝缘部30也可接触芯片零件10的侧面。即，在绝缘部30与芯片零件10之间也可不形成间隙。在图1所示例中，设置绝缘部30不超过芯片10的高度。绝缘部30的上端也可与芯片零件10的上面(钝化膜16的表面)是相同的高度。此时，绝缘部30与芯片零件10没有台阶。绝缘部30也可仅覆盖芯片零件10的侧面中由半导体或导体构成的部分。此时，绝缘部30的上端比钝化膜16的上面还低。
绝缘部30具有从芯片零件10向外下降的倾斜面32。绝缘部30最厚的部分位于最接近芯片零件10的位置，最薄的部分位于离芯片零件10最远的位置。绝缘部30也可形成于配线图案22(详细地说是其露出部24)的一部分上。
电子装置具有配线34。配线34的一部分形成于电极14上。配线34也可以通过钝化膜16上。配线34通过绝缘膜30上。在绝缘部30由树脂形成的情况下，绝缘部30与配线34的密接性比钝化膜16与配线34的密接性高。若芯片零件10(例如其钝化膜16)与绝缘部30的台阶小，则可防止配线34的断路。配线34到达配线图案22(详细地说是其露出部24)上形成。即，配线34电连接电极14与配线图案22。
电子装置也可具有多个外部端子36。已知具有外部端子36的球栅阵列BGA(Ball Grid Array)型封装或CSP(Chip Size Package)等。另外，还已知不设置外部端子36，配线图案22的一部分(例如第2露出部26)变为与外部电连接的LGP(Land Grid Array)型封装。
电子装置也可具有密封材料38。密封材料38至少密封配线34与电极14的电连接部，和配线34与配线图案22的电连接部。密封材料38也密封芯片零件10。
图3A-图3C是说明根据本发明的电子装置的制造方法图。如图3A所示，电子装置的制造方法包含外部端子36的形成。外部端子36由焊剂材料形成。外部端子36可设置在配线图案22(例如第2露出部26)上。外部端子36也可由焊剂材料形成。焊剂材料是具有导电性的金属(例如合金)，是用于使其熔化得到电连接的材料。焊剂材料可以是熔点在450度以下(“以下”含义为“等于小于”)的软焊剂(soft solder)或熔点在450度以上(“以上”含义为“大于等于”)的硬焊剂(hard solder)中的任一种。作为焊剂材料，可使用不含铅的焊锡(下面称为无铅焊锡)。无铅焊锡大多熔点比含铅的焊锡高。作为无铅焊锡，可使用锡—银(Sn-Ag)类、锡—铋(Sn-Bi)类、锡—锌(Sn-Zn)类、或锡—铜(Sn-Cu)类的合金，在这些合金中尤其还可添加银、铋、锌、铜中的至少一种。外部端子36在装载芯片零件10之前设置在基板20上。
另外，如LGA(Land Grid Array面栅阵列)那样，将岸面自身作为外部端子。并且，也可形成导电胶等导电性树脂、AU、Au-Su等岸面并用作外部端子。该结构成为芯片载架，单独构成功能零件。
如图3B所示，在基板20上装载芯片零件10。具体而言，第2面18相对向基板20地装载芯片零件10。也可使粘接剂介于基板20及芯片零件10之间，形成粘接层29。在基板20上装载芯片零件10的工序以比外部端子36的熔点低的温度进行。另外，在芯片零件10附近形成绝缘部30。绝缘部30除形成粘接层29的粘接剂外，也可以另外设置材料而形成。绝缘部30也可由聚酰亚胺树脂、硅变性聚酰亚胺树脂、环氧树脂、硅变性环氧树脂、苯环丁烯(BCB；benzocyclobutene)、聚苯并噁唑(PBO；polybenzoxazole)等树脂形成。形成绝缘部30，使之具有从芯片零件10向外下降的倾斜面32。也可接触芯片零件10的侧面形成绝缘部30。形成绝缘部30的工序最好以比外部端子36的熔点低的温度进行。
如图3C所示，形成配线34。配线34从电极14上通过绝缘部30上后到达配线图案22(例如露出部24)上那样形成。也可由包含导电性微粒子的分散液形成配线34。例如，也可适用喷墨法。详细地说，可向电极14、绝缘部30及配线图案22(例如露出部24)上喷出含有导电性微粒子的分散液而形成配线34。配线34的形成工序可包含将含有导电性微粒子的分散液干燥后除去分散媒。配线34的形成工序还可包含加热分解覆盖导电性微粒子的涂层材料。配线34的形成工序也可包含聚合导电性微粒子彼此。形成配线34的工序最好以比外部端子36的熔点低的温度进行。
在本实施方式中搭载的芯片零件中部分零件事先通过其它方法(例如焊接)安装在基板上。具体而言，通过焊接事先安装被动零件(L-C·R等)，也可由配线来仅安装半导体元件。
如图1所示，可设置密封材料38。密封材料38可通过传递模塑法(transfer-mold)或浇注(potting)封装形成。也可省略密封材料38。设置密封材料38的工序最好以比外部端子36的熔点低的温度进行。
根据本实施方式，因为配线34的形成工序可以比外部端子36的熔点低的温度进行，所以可减少对基板20耐热性的要求，并可减少芯片零件10的应力的产生。另外，若在外部端子的熔点以下进行配线形成，则也可将外部端子自身作为后续工序的保持零件来使用。另外，使用焊剂材料的外部端子的形成在芯片零件10的装载工序之前进行，所以可使工序顺序具有弹性。
根据本实施方式，当电连接电极14与配线图案22时，可避免如在引线接合或表面降低连接中进行的高温加热。因此，可减少对基板20耐热性的要求，并可减少芯片零件10的应力的产生。另外，作为基板20可使用通用基板，并对应于芯片零件10(其电极14的排列等)缠绕配线34。此时，对应于芯片零件10的种类，向配线图案22的不同部分连接配线34。
图4-图13是说明根据本发明实施方式的电子装置的变形例的图。
在图4中，绝缘部40的一部分搭在芯片零件10的第1面12(详细地说是钝化膜16)上而形成。绝缘部40的一部分搭在比芯片零件10的电极14更靠周围部侧的部分。为了防止电极14被绝缘部40覆盖，使绝缘部40可止于离开电极14的位置(比电极更靠周围侧的位置)。或者，也可邻接电极14从钝化膜16的露出部来形成绝缘部40。此时配线42不搭在与绝缘部40紧贴性低的钝化膜16上。绝缘部40具有邻接于芯片零件10从第1面12凸起的部分。其它结构对应于与图1所示的电子装置相同的内容。
在图5中，绝缘部44的一部分不搭在芯片零件10的第1面12上而形成。绝缘部44具有邻接于芯片零件10上从第1面12凸起的部分。绝缘部44在与芯片零件10相反侧具有阶梯状的部分。其它结构对应于与图1所示的电子装置相同的内容。
在图6中，绝缘部50与粘接层52形成一体。粘接层52由与绝缘部50相同材料形成。也可在基板20及芯片零件10之间设置绝缘性的粘接剂，向基板20及芯片零件10之间施加压力，在芯片零件10的邻近挤出粘接剂，由粘接剂形成绝缘部50及粘接层52。绝缘部50的倾斜面54是凹面(例如，在垂直于第1面12的截面中描绘曲线的凹面)。其另外的结构，与图1所示电子装置相同的内容符合。另外，图6所示的形态也适用于其他的实施方式或变形例。
在图7中，绝缘部60与粘接层62形成一体。粘接层62由与绝缘部60相同的材料形成。也可在基板20及芯片零件10之间设置绝缘性的粘接剂，向基板20及芯片零件10之间施加压力，在芯片零件10的邻近挤出粘接剂，由粘接剂形成绝缘部60及粘接层62。绝缘部60的倾斜面64是凸面(例如，在垂直于第1面12的截面中描绘曲线的凸面)。其它结构对应于与图1所示的电子装置相同的内容。另外，图7所示的形态也适用于其他的实施方式或变型例。
在图8中，芯片零件70具有从第1面(形成电极14的面)72向外下降倾斜的侧面74。因为侧面74倾斜，所以在其上容易设置绝缘部75以具有倾斜的面。芯片零件70也可包含从与第1面72相反侧的第2面76垂直上升的侧面78。侧面74、78也可连接。其它结构对应于与图1所示的电子装置相同的内容。另外，图8所示的形态也适用于其他的实施方式或变形例。
侧面74，如图9A所示，也可在切断晶片(例如半导体晶片)80时形成。详细地说，使用角铣刀等2个切刃成角度连接的刀具(例如切片锯)82，在晶片80上形成具有倾斜面的沟(例如V沟)，由倾斜面形成侧面74。在形成沟后，如图9B所示，可由在外周面具有切刃的刀具(例如切片锯)84切断沟的底面。这样，可形成从第2面76垂直上升的侧面78。
在图10中，芯片零件90的侧面94从第1面(形成电极14的面)92向外下降倾斜。侧面94也从与第1面92相反侧的第2面96倾斜。其它结构对应于与图1所示的电子装置相同的内容。另外，图10所示的形态也适用于其他的实施方式或变形例。
在图11中，芯片零件100在其端部具有台阶102。台阶102包含从第1面(形成电极14的面)104下降(例如垂直下降)的面；从与第1面104相反侧的第2面106上升(例如垂直上升)的面；和为连接这些面沿横向(例如与第1或第2面104、106平行的方向)延伸的面。其它结构对应于与图1所示的电子装置相同的内容。另外，图11所示的形态也适用于其他的实施方式或变形例。
在图12中，在基板20上，在与装载芯片零件10的面相反侧的面上，装载第2芯片零件110。将第2芯片零件110电连接于配线图案22(详细地说是第2露出部26)。第2芯片零件110的安装形态可以是倒装焊接及正装焊接之任一种。在倒装焊接中，使第2芯片零件110的电极(突块)与配线图案22相向电连接。在正装焊接中可将引线用于电连接。其它结构对应于与图1所示的电子装置相同的内容。另外，图12所示的形态也适用于其他的实施方式或变形例中。
在图13中，在基板20上，在装载芯片零件10的面上，装载第2芯片零件120。例如，在芯片零件10的上方(或覆盖芯片零件10)配置第2芯片零件120。第2芯片零件120电连接于配线图案22(详细地说是露出部24)。第2芯片零件120的安装形态可是倒装焊接及正装焊接之任一种。在倒装焊接中使第2芯片零件120的电极(突块)与配线图案22相向电连接。在正装焊接中可将引线用于电连接。其它结构对应于与图1所示的电子装置相同的内容。另外，图13所示的形态也适用于其他的实施方式或变形例中。
在图14中表示安装在所述的实施方式中说明的电子装置1的电路基板1000。作为具有该电子装置的电子仪器，在图15中表示笔记本个人电脑2000，在图16中表示移动电话3000。
本发明不只限于所述的实施方式，也可有各种变形。例如，本发明包含实质与在实施方式中说明的结构相同的结构(例如，功能、方法及结果相同的结构，或目的及结果相同的结构)。另外，本发明包含替换在实施方式中说明的结构的非本质的部分的结构。另外，本发明包含能取得与实施方式中说明的结构相同作用效果的结构，或能达到相同目的的结构。另外，本发明包含在实施方式中说明的结构中添加公知技术的结构。

Claims (7)

1、一种电子装置的制造方法，包括：
在形成于基板中的配线图案中形成外部端子；和
之后，将具有电极的芯片零件装载在所述基板上，以比所述外部端子的熔点低的温度，形成电连接所述电极与所述配线图案的配线。
2、根据权利要求1所述的电子装置的制造方法，其特征在于：可由包含导电性微粒子的分散液形成所述配线。
3、根据权利要求2所述的电子装置的制造方法，其特征在于：还包含在所述芯片零件的侧面形成绝缘部，
形成所述配线的工序，包括向所述绝缘部及所述配线图案上喷出包含所述导电性微粒子的所述分散液。
4、根据权利要求3所述的电子装置的制造方法，其特征在于：由树脂形成所述绝缘部。
5、根据权利要求3或4所述的电子装置的制造方法，其特征在于：形成为所述绝缘部，以使具有从所述芯片零件向外下降的倾斜面。
6、根据权利要求1-4中的任意1项所述的电子装置的制造方法，其特征在于：
所述芯片零件是半导体元件。
7、一种芯片载架，具有
由焊剂材料形成于在基板上形成的配线图案中的外部端子；和与具有电极的芯片零件的所述电极连接的区域。
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