CN1491077A - 用于装配电子零件的薄膜承载带及用于涂覆阻焊剂的印网掩模 - Google Patents

用于装配电子零件的薄膜承载带及用于涂覆阻焊剂的印网掩模 Download PDF

Info

Publication number
CN1491077A
CN1491077A CNA031571549A CN03157154A CN1491077A CN 1491077 A CN1491077 A CN 1491077A CN A031571549 A CNA031571549 A CN A031571549A CN 03157154 A CN03157154 A CN 03157154A CN 1491077 A CN1491077 A CN 1491077A
Authority
CN
China
Prior art keywords
solder resist
moving direction
rubber flap
marginal portion
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA031571549A
Other languages
English (en)
Other versions
CN100413385C (zh
Inventor
寺田明弘
山下圭介
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsui Mining and Smelting Co Ltd
Original Assignee
Mitsui Mining and Smelting Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsui Mining and Smelting Co Ltd filed Critical Mitsui Mining and Smelting Co Ltd
Publication of CN1491077A publication Critical patent/CN1491077A/zh
Application granted granted Critical
Publication of CN100413385C publication Critical patent/CN100413385C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452Solder masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4867Applying pastes or inks, e.g. screen printing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985Flexible insulating substrates
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/12Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
    • H05K3/1216Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns by screen printing or stencil printing
    • H05K3/1225Screens or stencils; Holders therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12041LED
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15172Fan-out arrangement of the internal vias
    • H01L2924/15173Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15182Fan-in arrangement of the internal vias
    • H01L2924/15183Fan-in arrangement of the internal vias in a single layer of the multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0393Flexible materials
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05Patterning and lithography; Masks; Details of resist
    • H05K2203/0562Details of resist
    • H05K2203/0594Insulating resist or coating with special shaped edges

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

本发明为用于装配电子零件的薄膜承载带,包括绝缘薄膜,在该绝缘薄膜的表面上形成的布线图,及通过利用前述布线图的印网掩模移动橡胶刮板形成的阻焊层,该阻焊层是按这样一种方式形成的,即布线图的连接端子部分要暴露出来,其中该阻焊层的边缘与在涂覆阻焊剂中使用的橡胶刮板的移动方向基本平行或基本呈直角,阻焊层可通过使用涂覆阻焊剂的印网掩模形成,在涂覆阻焊剂时,要涂覆阻焊剂的未遮蔽的印网的边缘与在涂覆阻焊剂中使用的橡胶刮板的移动方向基本平行或基本呈直角。按照本发明,可降低阻焊剂涂覆的次品率。

Description

用于装配电子零件的薄膜承载带及用于涂覆阻焊剂的印网掩模
技术领域
本发明涉及一种装配电子零件的薄膜承载带,该薄膜承载带在阻焊层的边缘阻焊剂突出的问题更少,还涉及生产这种薄膜承载带的印网掩模。
背景技术
为装配电子零件如集成电路(IC),采用了在绝缘薄膜上具有布线图的用于装配电子零件的薄膜承载带,该用于装配电子零件的薄膜承载带一般通过下述工艺生产,该工艺包括将金属箔如铜箔结合到绝缘薄膜如聚酰亚胺薄膜的表面上、在该金属箔的表面上涂覆光致抗蚀剂、使光致抗蚀剂曝光并显影以形成所需的光致抗蚀剂的图案、应用该图案作为遮蔽材料选择性地蚀刻该金属箔以形成由蚀刻金属箔组成的布线图、及在该布线图上除接线端子部分外的区域形成阻焊层。
在上面所述的用于装配电子零件的薄膜承载带的生产过程中,阻焊剂是按如下方法涂覆的。使用涂覆阻焊剂的印网掩模,其中印网伸展在框架上并遮蔽该印网表面除了要涂覆阻焊剂的区域以外的部分,该印网掩模被叠加到在绝缘薄膜上形成的布线图上,然后阻焊剂被添加到该印网掩模上,并通过移动橡胶刮板涂覆以把阻焊剂挤压到布线图的指定区域上。
经过如上所述的涂覆阻焊剂的步骤,布线图除连接端子部分外可以受到保护。
在常规的用于装配电子零件的薄膜承载带中,焊盘的形成密度不是很高,所以,如图7的50-a所示,阻焊层50经常表现为主要由直线构成的简单形状,如正方形或长方形。但是,由于最近对高集成度的要求,焊盘5 1的形成密度也提高了,例如,如图5中所示。因此,有必要沿着焊盘51的形状(以辅助虚线60表示)形成阻焊层50。例如,阻焊层的拐角部分经常如图7的50-b中所示斜向形成,或者阻焊层的拐角部分经常如图7的50-c中所示形成圆弧状。在这样的装配电子零件的薄膜承载带中,焊盘(连接端子)51如图5中所示沿阻焊层50的边缘62排列形成,这种形状的阻焊层50经常通过移动橡胶刮板利用印网掩模而形成。在这种情况下橡胶刮板移动的方向如图5和图7中的箭头S所示。
但是,当通过橡胶刮板与印网掩模的边缘的倾斜接触而形成阻焊层的圆弧形或斜向的拐角部分时,在印网掩模上的多余的阻焊剂会通过橡胶刮板的移动拐到印网掩模的较低的一侧,因此,在与橡胶刮板的移动方向不垂直或不平行的边缘部分,如圆弧形边缘部分或斜向边缘部分的阻焊剂有时会从印网掩模的涂覆区域突出来,也就是说,涂覆的阻焊剂拐到印网掩模的弯曲部分或倾斜部分的较低的一侧,因此,如图6所示,拐到印网掩模的较低的一侧并向遮蔽区的边缘突出的阻焊剂有时会在阻焊层的边缘形成角状的突出52,如果该角状的突出52到达不允许被阻焊剂覆盖的焊盘51,就会发生焊盘51的接触不良的问题。
发明内容
本发明的目的是提供一种在阻焊剂涂覆层的边缘阻焊剂涂覆失败发生率低的用于装配电子零件的薄膜承载带。
本发明的另一个目的是提供一种用于涂覆阻焊剂的印网掩模,其被用于在装配电子零件的薄膜承载带上形成阻焊剂层,且通过该印网掩模的使用,当橡胶刮板移动时阻焊剂几乎不会拐到印网的背面。
按照本发明的用于装配电子零件的薄膜承载带包括绝缘薄膜、在该绝缘薄膜的表面上形成的布线图及通过移动橡胶刮板使用预定图案的印网掩模形成的阻焊层,该阻焊层是按这样一种方式形成的,即布线图的连接端子部分要暴露出来,其中:
该阻焊层的边缘与在涂覆阻焊剂中使用的橡胶刮板的移动方向基本平行或基本垂直。
按照本发明的用于形成上述的阻焊层的涂覆阻焊剂的印网掩模,包括一框架、在该框架上伸展的印网及为了选择性地涂覆阻焊剂而设置在印网表面上、除了要涂覆阻焊剂的区域以外的遮蔽区,其中:
为了选择性地涂覆阻焊剂而设置的遮蔽区的边缘与在涂覆阻焊剂中使用的橡胶刮板的移动方向基本平行或基本垂直。
在本发明的用于装配电子零件的薄膜承载带中,阻焊层的边缘与橡胶刮板的移动方向基本平行或基本垂直,没有与橡胶刮板的移动方向斜向交叉的边缘部分。通过形成如上所述的与橡胶刮板的移动方向基本平行或基本垂直的阻焊层的边缘,明显地防止被橡胶刮板推动的阻焊剂拐到印网的背面,因此,按照本发明,由于阻焊剂的涂覆失败造成的次品率显著降低。
附图说明
图1为本发明的用于装配电子零件的薄膜承载带的实施例的剖面图。
图2为阻焊层拐角部分的形状的放大平面图。
图3为用于形成阻焊层的阻焊剂涂覆的印网掩模的实施例的平面图。
图4为沿图3中的A-A线获得的剖面图。
图5为传统的用于装配电子零件的薄膜承载带阻焊层的实例的示意图,其中阻焊层的拐角部分为圆弧形。
图6为在传统的用于装配电子零件的薄膜承载带的阻焊层中出现的角状突出的示意图。
图7为阻焊层形状图。
[标号说明]
10:用于装配电子零件的薄膜承载带
11:绝缘薄膜
12:布线图
13:焊盘
15:阻焊层
16:粘结层
18:电子零件
19:突出电极(bump electrode)
20:金线(导电金属线)
25:边缘
25a:与橡胶刮板的移动方向基本垂直的边缘部分
25b:与橡胶刮板的移动方向基本平行的边缘部分
25c:按阶梯状形成的边缘部分
26:辅助虚线
30:印网掩模
31:框架
32:印网
33:遮蔽区
34:边缘
34a:形成与橡胶刮板的移动方向基本垂直的直线的边缘部分
34b:形成与橡胶刮板的移动方向基本平行的直线的边缘部分
34c:拐角部分
34d:与橡胶刮板的移动方向基本垂直的边缘部分
34e:与橡胶刮板的移动方向基本平行的边缘部分
40:橡胶刮板
50:阻焊层
52:角状突出
51:端子部分
50-a,50-b,50-c:阻焊层的形状
60:辅助虚线
62:边缘
S:橡胶刮板的移动方向
具体实施方式
下面将详细说明本发明的用于装配电子零件的薄膜承载带和用于以阻焊剂涂覆薄膜承载带的阻焊剂涂覆印网掩模。
如图1中所示,本发明的用于装配电子零件的薄膜承载带10包括绝缘薄膜11,在绝缘薄膜11的表面上形成的布线图12,和在布线图12上形成的阻焊层15,该阻焊层15是按这样一种方式形成的,即布线图12的焊盘(连接端子)13要显露出来。在阻焊层15上,电子零件18通过,如粘结层16装配。
在电子零件18上,通常具有突出电极19,且该突出电极19可通过金线(导电金属线)20被电性连接到在用于装配电子零件的薄膜承载带10中形成的焊盘13(内部端子)上。
构成用于装配电子零件的薄膜承载带10的绝缘薄膜11是耐热和柔软的树脂薄膜,且该用于形成绝缘薄膜的树脂是,例如,聚酯、聚酰胺或聚酰亚胺。在本发明中,优选使用以聚酰亚胺制造的薄膜。在本发明中可用作绝缘薄膜的聚酰亚胺的实例包括一般由苯均四酸二酐与芳族二胺合成的芳族聚酰亚胺,及具有联苯骨架的由联苯四羧酸二酐与芳族二胺合成的芳族聚酰亚胺。在本发明中,可以使用这些聚酰亚胺中的任何一种。与其它树脂相比,这些聚酰亚胺具有显著较高的耐热性和优良的化学稳定性。
在本发明中,优选用作绝缘薄膜11的聚酰亚胺薄膜通常具有5-150μm的平均厚度,优选为5-125μm,特别优选为5-100μm。
在本发明的用于装配电子零件的薄膜承载带的生产中,可按照要生产的用于装配电子零件的薄膜承载带的类型形成各种不同需要的孔,如导孔、用于嵌入焊球的穿孔、装置孔、定位孔和用于把电子零件中形成的电极电性连接至导线的狭槽。
在绝缘薄膜11的至少一个表面上形成一导电金属层,该导电金属层可通过以下方法形成,例如,通过粘结层将导电金属箔如铝箔或铜箔结合到绝缘薄膜11上,或通过喷涂等方法在绝缘薄膜11的表面上沉积少量的金属如镍或铬,然后通过化学淀积、电镀等方法在以上形成的金属层上涂覆金属如铜。
以上形成的导电金属层通常具有1-35μm的厚度。
可按以下的方式形成布线图12。结合到绝缘薄膜11的表面上的导电金属箔的表面以感光树脂涂覆以形成一感光树脂层,然后该感光树脂层按所需图案的形式曝光并经显影以除去多余的树脂,用具有所需图案的感光树脂作为遮蔽材料选择性蚀刻导电金属箔。
图2是按以上方式形成的布线图的一部分的放大平面示意图。参照图2,数字12表示布线图,数字13表示焊盘(连接端子),而数字15表示阻焊层,其以斜线显示。
在本发明的装配电子零件的薄膜承载带10中,沿着弯曲的(即圆弧形)辅助虚线26形成大量的焊盘13,因此,沿辅助虚线26设置阻焊层的边缘形成的阻焊层15是高效率的,但是,如果阻焊剂是这样涂覆的以使最后获得的阻焊层的边缘沿辅助虚线26设置,印网掩模的边缘与橡胶刮板互相斜向交叉,在交叉点,由于橡胶刮板的压力作用,阻焊剂易于拐到与橡胶刮板呈锐角接触的印网掩模的较低的表面。
因此,在本发明中,如图3中所示,使用遮蔽区33的边缘34与橡胶刮板40的移动方向S基本平行或基本垂直的印网掩模涂覆阻焊剂。
如图3和沿图3中的A-A线获得的剖面图图4中所示,用于形成本发明的装配电子零件的薄膜承载带的阻焊层的用于涂覆阻焊剂的印网掩模30(也称作“阻焊剂涂覆印网掩模30”),具有一框架31、一在该框架31上伸展的印网32和用以选择性地涂覆阻焊剂在印网表面上除了要以阻焊剂涂覆的区域外的遮蔽区33。
在阻焊剂涂覆印网掩模30中,框架31是用坚硬的材料如金属或塑料制成的,而且印网32伸展在该框架上。印网32具有细小的网眼,且通过使用橡胶刮板40,阻焊剂可透入印网32的细小网眼中以在用于装配电子零件的薄膜承载带的表面上形成阻焊层。这种印网可用金属丝布(金属丝网)、丝网等构成。
印网32具有遮蔽区33以使阻焊剂可按所需的形状涂覆,遮蔽区33可通过,例如,按所需的形状曝光感光树脂并显影该树脂而形成,更具体地说,用感光树脂涂覆塑料薄膜的一面以形成一感光树脂层,然后该感光树脂层经曝光和显影而在塑料薄膜上形成所需的图案。这样形成的图案被转移到印网上,因而可在印网32上形成遮蔽区33。遮蔽区33也可以通过在印网表面上涂覆感光树脂,然后按所需图案曝光该感光层并对其显影而直接在印网32上形成。
遮蔽区33的边缘34包括边缘部分34e,该边缘部分34e与橡胶刮板40的移动方向S基本平行,边缘部分34d,该边缘部分34d与橡胶刮板40的移动方向S基本垂直,及四个连接边缘部分34e和边缘部分34d的拐角部分34c。在本发明的印网掩模30中,优选四个拐角部分34c各自形成阶梯状,其中与橡胶刮板40的移动方向S基本垂直的边缘部分34a和与橡胶刮板40的移动方向S基本平行的边缘部分34b交替排列。
通过交替排列边缘部分34a和边缘部分34b以形成阶梯状的拐角部分34c,遮蔽区33没有任何与橡胶刮板40斜向接触的边缘部分,因此,通过橡胶刮板40的移动而上推的阻焊剂很少会拐到遮蔽区33的底面侧。
在本发明中,在遮蔽区33的阶梯状拐角部分34c,由与橡胶刮板40的移动方向S基本垂直的直线构成的边缘部分34a和由与橡胶刮板40的移动方向S基本平行的直线构成的边缘部分34b有时在它们的接触点会接合形成细小的圆弧部分,阻焊剂很少会拐到印网掩模的底面。
在通过使用上述的阻焊剂涂覆印网掩模30形成的阻焊层15中,边缘25具有阶梯状的边缘部分25c,其中对应于形成与橡胶刮板40的移动方向S基本垂直的直线的边缘部分34a和形成与橡胶刮板40的移动方向S基本平行的直线的边缘部分34b的,与橡胶刮板40的移动方向S基本垂直的边缘部分25a和与橡胶刮板40的移动方向S基本平行的边缘部分25b交替排列。在形成阶梯状的边缘部分25c,阻焊剂很少会拐到印网掩模的底面,因此不会在阶梯状的边缘部分形成任何角状突出。通过阶梯状的边缘部分的形成,不仅在初始的涂覆阶段而且在连续涂覆后,边缘部分的最初的阶梯形状不会改变。
阻焊层可由,例如,环氧树脂、聚氨酯树脂或聚酰亚胺树脂形成,由这样的树脂形成的阻焊层的厚度通常在5-60μm的范围内,优选为10-20μm。
在如上所述形成阻焊层15后,对从阻焊层15暴露出来的布线图12的表面再进行电镀。
电镀方法的例子包括镀镍、镀镍/金、镀金、镀锡和焊接镀,可按照最终的薄膜承载带的使用目的选择适宜的电镀方法。虽然如此形成的镀层(未显示)的厚度并没有特别限制,但其通常在0.01-10μm的范围内,优选为0.05-5μm。
上面描述的是在阻焊层形成后进行电镀的实施例,但也可以先在布线图上形成锡镀层后,再形成阻焊层,然后再进行电镀。通过以上所述的多步骤电镀,可有效地防止因为迁移造成的金属须或短路的发生。
电镀之后,可以进行热处理,由此形成电镀层的金属与形成布线图的金属可相互渗透以形成一连续的层。
如图1中所示,本发明的用于装配电子零件的薄膜承载带可被用作装配电子零件(如球栅陈列(BGA)、软膜上封装集成电路(COF))的薄膜承载带,该电子零件采用了电子零件被装配在薄膜承载带阻焊层的表面上的系统,在电子零件上形成的突出电极通过,例如,金线被电性连接到焊盘上,而通过布线图被电性连接到焊盘上的焊球被用作外部连接端子。
当在用于装配电子零件如BGA的薄膜承载带的背面上形成外部连接端子时,焊球被安置在绝缘薄膜上形成的焊球孔中,由此焊球与在绝缘薄膜表面上形成的布线图电性连接。
也可以在本发明的用于装配电子零件的薄膜承载带中形成装置孔并将电子零件安置在该装置孔中。
对于在本发明的用于装配电子零件的薄膜承载带上装配电子零件的方法没有特别限制,可以使用任何常见的方法。
如上所述在电子零件被装配以后,用树脂封焊该电子零件,因而使其与薄膜承载带结合成一体。
                           发明效果
在本发明的用于装配电子零件的薄膜承载带中,阻焊层的边缘如上所述与在阻焊剂涂覆中使用的橡胶刮板的移动方向基本平行或基本垂直,因此,几乎不发生非正常的涂覆,如阻焊剂从边缘的角状突出,因而可降低由于阻焊剂的涂覆失败造成的次品率。
具有低次品率的阻焊层是通过使用其边缘与阻焊剂涂覆中所用的橡胶刮板的移动方向基本平行或基本垂直的用于阻焊剂涂覆的印网掩模形成的,所以阻焊剂很少会拐到印网掩模的背面,因此,几乎不会在阻焊层的边缘形成角状突出。
因此,本发明的用于装配电子零件的薄膜承载带由于阻焊剂的涂覆失败造成的次品率较低。
                             实施例
本发明将参照下述实施例作进一步的说明,但应当认为本发明并不受这些发明的限制。
实施例1
平均厚度为35μm的电积铜箔通过加压加热用厚度为12μm粘结层结合到厚度为75μm的聚酰亚胺薄膜(商品名:Upilex S,Ube Industries,Ltd.提供)上。
随后,将感光树脂涂覆到电积铜箔的表面上,然后曝光并显影以形成由固化的感光树脂构成的所需的图案。
具有如此形成的图案的基膜浸入蚀刻溶液中使用该图案作为遮蔽材料以进行电积铜箔的蚀刻,因此,形成由铜构成的布线图。
另外,将感光树脂涂覆到聚对苯二甲酸乙二醇酯薄膜(PET薄膜)的表面上以使获得的感光树脂层的平均厚度以干后计达到2μm,然后,使遮蔽区的形状生成图象数据,且在该图象数据的基础上,对PET膜上的感光树脂层进行紫外线曝光并按常规方法显影以形成遮蔽区。在这样形成的遮蔽区中,如图3中所示,拐角部分为阶梯状,而且没有与橡胶刮板的移动方向斜向交叉的边缘部分。
如上所述在PET薄膜上形成的遮蔽区被转移到伸展在框架上的印网表面上以构成用于阻焊剂涂覆的印网掩模。
应用该用于阻焊剂涂覆的印网掩模,涂覆环氧树脂阻焊剂,然后固化以形成平均厚度为10μm的阻焊层。
如上形成阻焊层后,在从该阻焊层向外延展的布线图(连接部分)的表面上形成平均厚度为0.5μm的镀镍层,并在该镀镍层上进一步形成平均厚度为0.5μm的镀金层。
按以上方法制备了145760片膜形载体,并对其进行目视检查,结果次品数为5(次品率:34ppm),但这五个次品中没有一个是由于阻焊剂的涂覆失败造成的。
在上述的通过涂覆阻焊剂形成阻焊层的过程中,每200次操作(shots)对印网背面进行清洁,并比较清洁后第一次操作形成的阻焊层和清洁后第200次操作形成的阻焊层,其结果,就阻焊剂的突出而言,在两个阻焊层之间没有差异。
对照实施例1
按实施例1中的相同方法形成阻焊层,只是用于阻焊剂涂覆的是如图7的50-b中所示的拐角部分与橡胶刮板的移动方向倾斜的印网掩模而不是实施例1中的印网掩模,然后,按实施例1中的相同方法制备了327811片膜形载体。
按实施例1中的相同方法对如上所获得的膜形载体进行目视检查,其结果,次品数为1175(次品率:3584ppm),且这些次品中的一些在阻焊层的边缘有角状突出。
在上述的通过涂覆阻焊剂形成阻焊层的过程中,每200次操作对印网背面进行清洁,并比较清洁后第一次操作形成的阻焊层和清洁后第200次操作形成的阻焊层,其结果,因为阻焊剂的突出,与第一次操作形成的阻焊层相比,在第200次操作时形成的阻焊层的边缘向外延展了。
对照实施例2
按实施例1中的相同方法形成阻焊层,只是用于阻焊剂涂覆的是如图7的50-c中所示的拐角部分与橡胶刮板的移动方向呈圆弧形的印网掩模而不是实施例1中的印网掩模,然后,按实施例1中的相同方法制备了258012片膜形载体。
按实施例1中的相同方法对如上所获得的膜形载体进行目视检查,其结果,次品数为1247(次品率:4833ppm),且这些次品中的一些在阻焊层的边缘有角状突出。
在上述的通过涂覆阻焊剂形成阻焊层的过程中,每200次操作对印网背面进行清洁,并比较清洁后第一次操作形成的阻焊层和清洁后第200次操作形成的阻焊层,其结果,因为阻焊剂的突出,与第一次操作形成的阻焊层相比,在第200次操作时形成的阻焊层的边缘向外延展了。

Claims (4)

1、装配电子零件的薄膜承载带,包括绝缘薄膜,在该绝缘薄膜的表面上形成的布线图,及通过利用规定图案的印网掩模移动橡胶刮板形成的阻焊层,该阻焊层是按这样一种方式形成的,即布线图的连接端子部分要暴露出来,其中:
该阻焊层的边缘与在涂覆阻焊剂中使用的橡胶刮板的移动方向基本平行或基本垂直。
2、如权利要求1所述的装配电子零件的薄膜承载带,其中该阻焊层的边缘包括与橡胶刮板的移动方向基本平行的边缘部分、与橡胶刮板的移动方向基本垂直的边缘部分及连接基本平行边缘部分和基本垂直边缘部分的拐角部分,且该拐角部分呈阶梯状,其中的与橡胶刮板的移动方向基本平行的边缘部分和与橡胶刮板的移动方向基本垂直的边缘部分交替排列。
3、涂覆阻焊层的印网掩模,包括一框架、在该框架上伸展的印网及为了选择性地涂覆阻焊剂而设置在印网表面上、除了要涂覆阻焊剂的区域以外的遮蔽区,其中:
为了选择性地涂覆阻焊剂而设置的遮蔽区的边缘与在涂覆阻焊剂中使用的橡胶刮板的移动方向基本平行或基本垂直。
4、如权利要求3所述的涂覆阻焊层的印网掩模,其中为了选择性地涂覆阻焊剂而设置的遮蔽区的边缘包括与橡胶刮板的移动方向基本平行的边缘部分、与橡胶刮板的移动方向基本垂直的边缘部分及连接基本平行边缘部分和基本垂直边缘部分的拐角部分,且该拐角部分呈阶梯状,其中的与橡胶刮板的移动方向基本平行的边缘部分和与橡胶刮板的移动方向基本垂直的边缘部分交替排列。
CNB031571549A 2002-09-18 2003-09-16 用于装配电子零件的薄膜承载带及用于涂覆阻焊剂的印网掩模 Expired - Fee Related CN100413385C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002271864 2002-09-18
JP2002271864 2002-09-18

Publications (2)

Publication Number Publication Date
CN1491077A true CN1491077A (zh) 2004-04-21
CN100413385C CN100413385C (zh) 2008-08-20

Family

ID=32040374

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB031571549A Expired - Fee Related CN100413385C (zh) 2002-09-18 2003-09-16 用于装配电子零件的薄膜承载带及用于涂覆阻焊剂的印网掩模

Country Status (4)

Country Link
US (2) US7158387B2 (zh)
KR (2) KR100772623B1 (zh)
CN (1) CN100413385C (zh)
TW (1) TWI229426B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103025079A (zh) * 2012-12-10 2013-04-03 苏沃智能科技江苏有限公司 嵌入式sim卡在gps中的永久固定方法

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004327920A (ja) * 2003-04-28 2004-11-18 Sharp Corp 半導体装置の製造方法、フレキシブル基板及び半導体装置
JP4625674B2 (ja) * 2004-10-15 2011-02-02 株式会社東芝 プリント配線基板及びこの基板を搭載する情報処理装置
US8633879B2 (en) 2009-02-13 2014-01-21 Apple Inc. Undulating electrodes for improved viewing angle and color shift
US8390553B2 (en) * 2009-02-13 2013-03-05 Apple Inc. Advanced pixel design for optimized driving
US20100208179A1 (en) * 2009-02-13 2010-08-19 Apple Inc. Pixel Black Mask Design and Formation Technique
US8531408B2 (en) * 2009-02-13 2013-09-10 Apple Inc. Pseudo multi-domain design for improved viewing angle and color shift
US9612489B2 (en) * 2009-02-13 2017-04-04 Apple Inc. Placement and shape of electrodes for use in displays
US8587758B2 (en) * 2009-02-13 2013-11-19 Apple Inc. Electrodes for use in displays
US8558978B2 (en) * 2009-02-13 2013-10-15 Apple Inc. LCD panel with index-matching passivation layers
US8294647B2 (en) * 2009-02-13 2012-10-23 Apple Inc. LCD pixel design varying by color
US8345177B2 (en) * 2009-02-13 2013-01-01 Shih Chang Chang Via design for use in displays
US8111232B2 (en) * 2009-03-27 2012-02-07 Apple Inc. LCD electrode arrangement
US8294850B2 (en) * 2009-03-31 2012-10-23 Apple Inc. LCD panel having improved response
JP6320066B2 (ja) * 2014-02-13 2018-05-09 イビデン株式会社 ボール搭載用マスクおよびボール搭載装置
US10737462B2 (en) 2016-08-24 2020-08-11 Hyundai Motor Company Method for coating surface of moving part of vehicle and moving part of vehicle manufactured by the same

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU596372B2 (en) * 1985-08-14 1990-05-03 Michael Bisak Security device
JPH06260750A (ja) * 1993-03-05 1994-09-16 Cmk Corp 各種形状のソルダランドの形成方法
US5511306A (en) * 1994-04-05 1996-04-30 Compaq Computer Corporation Masking of circuit board vias to reduce heat-induced board and chip carrier package warp during wavesolder process
DE4429206C2 (de) * 1994-08-18 1998-04-09 Atlas Copco Tools Ab Einrichtung zur Betriebssperre bzw. Betriebsfreigabe einer elektrischen Handwerkzeugmaschine
KR0139753Y1 (ko) * 1994-11-01 1999-04-15 전성원 자동차용 라이너 탈거장치
US5563581A (en) * 1995-07-05 1996-10-08 Kats; Vyacheslay Safety device for machine tool operators, and the like
US5666010A (en) * 1995-08-30 1997-09-09 Stratiotis; Gus Safety system for machine tools
KR100225655B1 (ko) * 1997-10-23 1999-10-15 윤종용 반도체 패키지의 인쇄회로기판 실장 구조
JPH11150359A (ja) * 1997-11-18 1999-06-02 Sony Corp 電極ランドへの半田のプリコート方法及びこれに用いて好適なスクリーン
JP3683434B2 (ja) * 1999-04-16 2005-08-17 富士通株式会社 半導体装置
JP2001183687A (ja) * 1999-12-22 2001-07-06 Hitachi Ltd 液晶表示装置
JP3536023B2 (ja) * 2000-10-13 2004-06-07 シャープ株式会社 Cof用テープキャリアおよびこれを用いて製造されるcof構造の半導体装置
US6570259B2 (en) * 2001-03-22 2003-05-27 International Business Machines Corporation Apparatus to reduce thermal fatigue stress on flip chip solder connections

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103025079A (zh) * 2012-12-10 2013-04-03 苏沃智能科技江苏有限公司 嵌入式sim卡在gps中的永久固定方法

Also Published As

Publication number Publication date
KR20070048694A (ko) 2007-05-09
CN100413385C (zh) 2008-08-20
TWI229426B (en) 2005-03-11
US20040066635A1 (en) 2004-04-08
KR100772623B1 (ko) 2007-11-02
US7203075B2 (en) 2007-04-10
US20060260539A1 (en) 2006-11-23
US7158387B2 (en) 2007-01-02
KR100772625B1 (ko) 2007-11-02
TW200405530A (en) 2004-04-01
KR20040025629A (ko) 2004-03-24

Similar Documents

Publication Publication Date Title
CN1491077A (zh) 用于装配电子零件的薄膜承载带及用于涂覆阻焊剂的印网掩模
CN1805657A (zh) 配线电路基板
CN1630454A (zh) 印刷线路板及半导体装置
CN1601611A (zh) 带电路的悬浮支架基板及其制造方法
CN1750737A (zh) 其上安装有芯片封装模块的印刷电路板及其制造方法
CN1182345A (zh) 多层印刷电路板
CN1921735A (zh) 带电路的悬挂基板的制造方法
CN1190115C (zh) 用于制造印刷线路板的复合材料
CN1841686A (zh) 柔性印刷线路板的制造方法以及柔性印刷线路板
CN1497717A (zh) 电路装置及其制造方法
CN1630068A (zh) 布线电路板
CN1424756A (zh) 金属布线基板和半导体装置及其制造方法
CN1697592A (zh) 印刷线路板,其生产方法和半导体器件
CN1333562A (zh) 半导体模块及其制造方法
CN1185913C (zh) 带有凸块的布线电路板及其制造方法
CN1512568A (zh) 电子部件封装用薄膜载带及其制造方法
CN1666327A (zh) 挠性配线基板及其制造方法
CN1925148A (zh) 多层配线基板及其制造方法
CN1701429A (zh) 布线板及其制造方法
CN1946265A (zh) 制作布线电路板的工艺
CN1620224A (zh) 安装电子元件的印刷线路板、其制作方法和半导体设备
CN1489202A (zh) 电子器件模块
CN1198873A (zh) 对独立导体电路进行电镀的工艺
CN1577825A (zh) 用于半导体封装的引线框架
CN1630067A (zh) 布线电路板

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20080820

Termination date: 20091016