CN1436331A - 多存储库dimm中实现的每个周期内的多重访问 - Google Patents

多存储库dimm中实现的每个周期内的多重访问 Download PDF

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Publication number
CN1436331A
CN1436331A CN01809630A CN01809630A CN1436331A CN 1436331 A CN1436331 A CN 1436331A CN 01809630 A CN01809630 A CN 01809630A CN 01809630 A CN01809630 A CN 01809630A CN 1436331 A CN1436331 A CN 1436331A
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China
Prior art keywords
data
dimm
memory bank
switching means
clock signal
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CN01809630A
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Chinese (zh)
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克里斯·卡拉巴茨奥斯
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Publication of CN1436331A publication Critical patent/CN1436331A/zh
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
CN01809630A 2000-05-17 2001-05-15 多存储库dimm中实现的每个周期内的多重访问 Pending CN1436331A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/572,641 US6446158B1 (en) 1999-05-17 2000-05-17 Memory system using FET switches to select memory banks
US09/572,641 2000-05-17

Publications (1)

Publication Number Publication Date
CN1436331A true CN1436331A (zh) 2003-08-13

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CN01809630A Pending CN1436331A (zh) 2000-05-17 2001-05-15 多存储库dimm中实现的每个周期内的多重访问

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US (1) US6446158B1 (enExample)
EP (1) EP1290561B1 (enExample)
JP (1) JP4769953B2 (enExample)
CN (1) CN1436331A (enExample)
AU (1) AU2001263124A1 (enExample)
WO (1) WO2001088714A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110390963A (zh) * 2018-04-16 2019-10-29 爱思开海力士有限公司 采样电路和使用采样电路的半导体存储器件

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CN110390963A (zh) * 2018-04-16 2019-10-29 爱思开海力士有限公司 采样电路和使用采样电路的半导体存储器件

Also Published As

Publication number Publication date
US6446158B1 (en) 2002-09-03
EP1290561B1 (en) 2019-10-23
EP1290561A1 (en) 2003-03-12
JP2004511026A (ja) 2004-04-08
JP4769953B2 (ja) 2011-09-07
AU2001263124A1 (en) 2001-11-26
WO2001088714A1 (en) 2001-11-22
EP1290561A4 (en) 2006-10-11

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