JP4769953B2 - マルチプルバンクｄｉｍｍにおけるマルチプルアクセスパーサイクル - Google Patents

マルチプルバンクｄｉｍｍにおけるマルチプルアクセスパーサイクル Download PDF

Info

Publication number
JP4769953B2
JP4769953B2 JP2001585044A JP2001585044A JP4769953B2 JP 4769953 B2 JP4769953 B2 JP 4769953B2 JP 2001585044 A JP2001585044 A JP 2001585044A JP 2001585044 A JP2001585044 A JP 2001585044A JP 4769953 B2 JP4769953 B2 JP 4769953B2
Authority
JP
Japan
Prior art keywords
data
clock signal
memory bank
delta
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2001585044A
Other languages
English (en)
Japanese (ja)
Other versions
JP2004511026A (ja
JP2004511026A5 (enExample
Inventor
カラバトソス、クリス
Original Assignee
ウレンチ アセッツ リミテッド ライアビリティ カンパニー
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ウレンチ アセッツ リミテッド ライアビリティ カンパニー filed Critical ウレンチ アセッツ リミテッド ライアビリティ カンパニー
Publication of JP2004511026A publication Critical patent/JP2004511026A/ja
Publication of JP2004511026A5 publication Critical patent/JP2004511026A5/ja
Application granted granted Critical
Publication of JP4769953B2 publication Critical patent/JP4769953B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
JP2001585044A 2000-05-17 2001-05-15 マルチプルバンクｄｉｍｍにおけるマルチプルアクセスパーサイクル Expired - Fee Related JP4769953B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/572,641 US6446158B1 (en) 1999-05-17 2000-05-17 Memory system using FET switches to select memory banks
US09/572,641 2000-05-17
PCT/US2001/015592 WO2001088714A1 (en) 2000-05-17 2001-05-15 Multiple access per cycle in a multiple bank dimm

Publications (3)

Publication Number Publication Date
JP2004511026A JP2004511026A (ja) 2004-04-08
JP2004511026A5 JP2004511026A5 (enExample) 2005-02-03
JP4769953B2 true JP4769953B2 (ja) 2011-09-07

Family

ID=24288730

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001585044A Expired - Fee Related JP4769953B2 (ja) 2000-05-17 2001-05-15 マルチプルバンクｄｉｍｍにおけるマルチプルアクセスパーサイクル

Country Status (6)

Country Link
US (1) US6446158B1 (enExample)
EP (1) EP1290561B1 (enExample)
JP (1) JP4769953B2 (enExample)
CN (1) CN1436331A (enExample)
AU (1) AU2001263124A1 (enExample)
WO (1) WO2001088714A1 (enExample)

Families Citing this family (94)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6323060B1 (en) 1999-05-05 2001-11-27 Dense-Pac Microsystems, Inc. Stackable flex circuit IC package and method of making same
US6643752B1 (en) 1999-12-09 2003-11-04 Rambus Inc. Transceiver with latency alignment circuitry
US7404032B2 (en) 2000-01-05 2008-07-22 Rambus Inc. Configurable width buffered module having switch elements
US7266634B2 (en) * 2000-01-05 2007-09-04 Rambus Inc. Configurable width buffered module having flyby elements
US6502161B1 (en) 2000-01-05 2002-12-31 Rambus Inc. Memory system including a point-to-point linked memory subsystem
US7010642B2 (en) * 2000-01-05 2006-03-07 Rambus Inc. System featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devices
US7356639B2 (en) * 2000-01-05 2008-04-08 Rambus Inc. Configurable width buffered module having a bypass circuit
US20050010737A1 (en) * 2000-01-05 2005-01-13 Fred Ware Configurable width buffered module having splitter elements
US7363422B2 (en) * 2000-01-05 2008-04-22 Rambus Inc. Configurable width buffered module
US6262895B1 (en) 2000-01-13 2001-07-17 John A. Forthun Stackable chip package with flex carrier
KR100587052B1 (ko) * 2000-06-30 2006-06-07 주식회사 하이닉스반도체 고속 인터페이스용 장치
US6839820B1 (en) * 2000-07-20 2005-01-04 Silicon Graphics, Inc. Method and system for controlling data access between at least two memory arrangements
TW526417B (en) * 2000-08-03 2003-04-01 Asustek Comp Inc Control circuit for providing applications of unbuffered dual in-line memory modules (DIMM) on system supporting only registered DIMM chipset
US6737891B2 (en) 2001-02-01 2004-05-18 Chris Karabatsos Tri-directional, high-speed bus switch
DE10106817C1 (de) * 2001-02-14 2002-08-08 Infineon Technologies Ag Speicheranordnung
US6629225B2 (en) * 2001-05-31 2003-09-30 Intel Corporation Method and apparatus for control calibration of multiple memory modules within a memory channel
US20060255446A1 (en) 2001-10-26 2006-11-16 Staktek Group, L.P. Stacked modules and method
US7026708B2 (en) 2001-10-26 2006-04-11 Staktek Group L.P. Low profile chip scale stacking system and method
US7656678B2 (en) 2001-10-26 2010-02-02 Entorian Technologies, Lp Stacked module systems
US7202555B2 (en) 2001-10-26 2007-04-10 Staktek Group L.P. Pitch change and chip scale stacking system and method
US7485951B2 (en) 2001-10-26 2009-02-03 Entorian Technologies, Lp Modularized die stacking system and method
US7371609B2 (en) 2001-10-26 2008-05-13 Staktek Group L.P. Stacked module systems and methods
US7310458B2 (en) 2001-10-26 2007-12-18 Staktek Group L.P. Stacked module systems and methods
US6914324B2 (en) 2001-10-26 2005-07-05 Staktek Group L.P. Memory expansion and chip scale stacking system and method
US6956284B2 (en) 2001-10-26 2005-10-18 Staktek Group L.P. Integrated circuit stacking system and method
US7053478B2 (en) 2001-10-26 2006-05-30 Staktek Group L.P. Pitch change and chip scale stacking system
US20030234443A1 (en) * 2001-10-26 2003-12-25 Staktek Group, L.P. Low profile stacking system and method
US6940729B2 (en) 2001-10-26 2005-09-06 Staktek Group L.P. Integrated circuit stacking system and method
US7081373B2 (en) 2001-12-14 2006-07-25 Staktek Group, L.P. CSP chip stack with flex circuit
US7003684B2 (en) * 2002-03-27 2006-02-21 Via Technologies, Inc. Memory control chip, control method and control circuit
TW559809B (en) * 2002-03-27 2003-11-01 Via Tech Inc Memory control chip, control method and control circuit
US20050050375A1 (en) * 2003-08-29 2005-03-03 Mark Novak Memory interface system and method
US7542304B2 (en) 2003-09-15 2009-06-02 Entorian Technologies, Lp Memory expansion and integrated circuit stacking system and method
US8250295B2 (en) * 2004-01-05 2012-08-21 Smart Modular Technologies, Inc. Multi-rank memory module that emulates a memory module having a different number of ranks
WO2005083572A1 (ja) * 2004-03-02 2005-09-09 Sony Corporation メモリ制御装置、メモリ制御方法、メモリ制御プログラムおよび画像撮像装置
US7532537B2 (en) * 2004-03-05 2009-05-12 Netlist, Inc. Memory module with a circuit providing load isolation and memory domain translation
US7916574B1 (en) 2004-03-05 2011-03-29 Netlist, Inc. Circuit providing load isolation and memory domain translation for memory module
US7289386B2 (en) * 2004-03-05 2007-10-30 Netlist, Inc. Memory module decoder
US7443023B2 (en) 2004-09-03 2008-10-28 Entorian Technologies, Lp High capacity thin module system
US7522421B2 (en) 2004-09-03 2009-04-21 Entorian Technologies, Lp Split core circuit module
US7511968B2 (en) 2004-09-03 2009-03-31 Entorian Technologies, Lp Buffered thin module system and method
US7468893B2 (en) 2004-09-03 2008-12-23 Entorian Technologies, Lp Thin module system and method
US7606040B2 (en) 2004-09-03 2009-10-20 Entorian Technologies, Lp Memory module system and method
US7542297B2 (en) 2004-09-03 2009-06-02 Entorian Technologies, Lp Optimized mounting area circuit module system and method
US7606050B2 (en) 2004-09-03 2009-10-20 Entorian Technologies, Lp Compact module system and method
US7616452B2 (en) 2004-09-03 2009-11-10 Entorian Technologies, Lp Flex circuit constructions for high capacity circuit module systems and methods
US7579687B2 (en) 2004-09-03 2009-08-25 Entorian Technologies, Lp Circuit module turbulence enhancement systems and methods
US20060050492A1 (en) 2004-09-03 2006-03-09 Staktek Group, L.P. Thin module system and method
US7423885B2 (en) 2004-09-03 2008-09-09 Entorian Technologies, Lp Die module system
US7289327B2 (en) 2006-02-27 2007-10-30 Stakick Group L.P. Active cooling methods and apparatus for modules
US7324352B2 (en) 2004-09-03 2008-01-29 Staktek Group L.P. High capacity thin module system and method
US7760513B2 (en) 2004-09-03 2010-07-20 Entorian Technologies Lp Modified core for circuit module system and method
US7446410B2 (en) 2004-09-03 2008-11-04 Entorian Technologies, Lp Circuit module with thermal casing systems
US7606049B2 (en) 2004-09-03 2009-10-20 Entorian Technologies, Lp Module thermal management system and method
US7280428B2 (en) 2004-09-30 2007-10-09 Rambus Inc. Multi-column addressing mode memory system including an integrated circuit memory device
US7571296B2 (en) * 2004-11-11 2009-08-04 Nvidia Corporation Memory controller-adaptive 1T/2T timing control
US8595459B2 (en) 2004-11-29 2013-11-26 Rambus Inc. Micro-threaded memory
US7309914B2 (en) 2005-01-20 2007-12-18 Staktek Group L.P. Inverted CSP stacking system and method
US7033861B1 (en) 2005-05-18 2006-04-25 Staktek Group L.P. Stacked module systems and method
US20060277355A1 (en) * 2005-06-01 2006-12-07 Mark Ellsberry Capacity-expanding memory device
US7464225B2 (en) 2005-09-26 2008-12-09 Rambus Inc. Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology
US7562271B2 (en) 2005-09-26 2009-07-14 Rambus Inc. Memory system topologies including a buffer device and an integrated circuit memory device
US11328764B2 (en) 2005-09-26 2022-05-10 Rambus Inc. Memory system topologies including a memory die stack
US7576995B2 (en) 2005-11-04 2009-08-18 Entorian Technologies, Lp Flex circuit apparatus and method for adding capacitance while conserving circuit board surface area
US7304382B2 (en) 2006-01-11 2007-12-04 Staktek Group L.P. Managed memory component
US7508058B2 (en) 2006-01-11 2009-03-24 Entorian Technologies, Lp Stacked integrated circuit module
US7508069B2 (en) 2006-01-11 2009-03-24 Entorian Technologies, Lp Managed memory component
US7605454B2 (en) 2006-01-11 2009-10-20 Entorian Technologies, Lp Memory card and method for devising
US7608920B2 (en) 2006-01-11 2009-10-27 Entorian Technologies, Lp Memory card and method for devising
US7511969B2 (en) 2006-02-02 2009-03-31 Entorian Technologies, Lp Composite core circuit module system and method
US20070260841A1 (en) 2006-05-02 2007-11-08 Hampel Craig E Memory module with reduced access granularity
US7468553B2 (en) 2006-10-20 2008-12-23 Entorian Technologies, Lp Stackable micropackages and stacked modules
US7417310B2 (en) 2006-11-02 2008-08-26 Entorian Technologies, Lp Circuit module having force resistant construction
US7945740B2 (en) * 2007-09-24 2011-05-17 International Business Machines Corporation Structure for a memory switching data processing system
US7937537B2 (en) * 2007-09-24 2011-05-03 International Business Machines Corporation Memory switching data processing system
US8516185B2 (en) 2009-07-16 2013-08-20 Netlist, Inc. System and method utilizing distributed byte-wise buffers on a memory module
US8154901B1 (en) 2008-04-14 2012-04-10 Netlist, Inc. Circuit providing load isolation and noise reduction
US8417870B2 (en) 2009-07-16 2013-04-09 Netlist, Inc. System and method of increasing addressable memory space on a memory board
US9128632B2 (en) 2009-07-16 2015-09-08 Netlist, Inc. Memory module with distributed data buffers and method of operation
US8402208B2 (en) * 2009-10-06 2013-03-19 Dell Products L.P. Configurable memory controller/memory module communication system
KR101796116B1 (ko) 2010-10-20 2017-11-10 삼성전자 주식회사 반도체 장치, 이를 포함하는 메모리 모듈, 메모리 시스템 및 그 동작방법
WO2012061633A2 (en) 2010-11-03 2012-05-10 Netlist, Inc. Method and apparatus for optimizing driver load in a memory package
US9477597B2 (en) * 2011-03-25 2016-10-25 Nvidia Corporation Techniques for different memory depths on different partitions
US8701057B2 (en) 2011-04-11 2014-04-15 Nvidia Corporation Design, layout, and manufacturing techniques for multivariant integrated circuits
US9529712B2 (en) 2011-07-26 2016-12-27 Nvidia Corporation Techniques for balancing accesses to memory having different memory types
US9268719B2 (en) 2011-08-05 2016-02-23 Rambus Inc. Memory signal buffers and modules supporting variable access granularity
JP2013061767A (ja) * 2011-09-13 2013-04-04 Elpida Memory Inc メモリシステムおよびメモリモジュール
EP3028153B1 (en) 2013-07-27 2019-03-06 Netlist, Inc. Memory module with local synchronization
KR101707266B1 (ko) * 2013-08-29 2017-02-15 엘에스산전 주식회사 Plc에서의 os의 업데이트 장치 및 방법
KR102509330B1 (ko) * 2018-04-16 2023-03-14 에스케이하이닉스 주식회사 샘플링 회로 및 이를 이용한 반도체 메모리 장치
US10884958B2 (en) 2018-06-25 2021-01-05 Intel Corporation DIMM for a high bandwidth memory channel
US10963404B2 (en) 2018-06-25 2021-03-30 Intel Corporation High bandwidth DIMM
US10635357B2 (en) 2018-07-03 2020-04-28 Nvidia Corporation Method for overlapping memory accesses
US11699471B2 (en) 2019-09-25 2023-07-11 Intel Corporation Synchronous dynamic random access memory (SDRAM) dual in-line memory module (DIMM) having increased per data pin bandwidth

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03113547A (ja) * 1989-09-28 1991-05-14 Casio Comput Co Ltd 記憶制御装置
JPH03269662A (ja) * 1990-03-20 1991-12-02 Fujitsu Ltd 高速メモリアクセス方式
JPH06202933A (ja) * 1992-12-28 1994-07-22 Toshiba Corp 同期式大規模集積回路記憶装置
JPH07282000A (ja) * 1994-04-04 1995-10-27 Hitachi Ltd バスインタフェース回路及びデータ転送システム
JPH0973781A (ja) * 1995-09-05 1997-03-18 Mitsubishi Electric Corp 同期型半導体記憶装置
US5666322A (en) * 1995-09-21 1997-09-09 Nec Electronics, Inc. Phase-locked loop timing controller in an integrated circuit memory
JP2000048599A (ja) * 1998-07-24 2000-02-18 Mitsubishi Electric Corp 同期型半導体記憶装置
JP2000261293A (ja) * 1998-10-29 2000-09-22 Koninkl Philips Electronics Nv ２進信号処理用回路配置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5261068A (en) * 1990-05-25 1993-11-09 Dell Usa L.P. Dual path memory retrieval system for an interleaved dynamic RAM memory unit
US5950223A (en) * 1997-06-19 1999-09-07 Silicon Magic Corporation Dual-edge extended data out memory
US6233650B1 (en) * 1998-04-01 2001-05-15 Intel Corporation Using FET switches for large memory arrays

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03113547A (ja) * 1989-09-28 1991-05-14 Casio Comput Co Ltd 記憶制御装置
JPH03269662A (ja) * 1990-03-20 1991-12-02 Fujitsu Ltd 高速メモリアクセス方式
JPH06202933A (ja) * 1992-12-28 1994-07-22 Toshiba Corp 同期式大規模集積回路記憶装置
JPH07282000A (ja) * 1994-04-04 1995-10-27 Hitachi Ltd バスインタフェース回路及びデータ転送システム
JPH0973781A (ja) * 1995-09-05 1997-03-18 Mitsubishi Electric Corp 同期型半導体記憶装置
US5666322A (en) * 1995-09-21 1997-09-09 Nec Electronics, Inc. Phase-locked loop timing controller in an integrated circuit memory
JP2000048599A (ja) * 1998-07-24 2000-02-18 Mitsubishi Electric Corp 同期型半導体記憶装置
JP2000261293A (ja) * 1998-10-29 2000-09-22 Koninkl Philips Electronics Nv ２進信号処理用回路配置

Also Published As

Publication number Publication date
US6446158B1 (en) 2002-09-03
EP1290561B1 (en) 2019-10-23
EP1290561A1 (en) 2003-03-12
JP2004511026A (ja) 2004-04-08
CN1436331A (zh) 2003-08-13
AU2001263124A1 (en) 2001-11-26
WO2001088714A1 (en) 2001-11-22
EP1290561A4 (en) 2006-10-11

Similar Documents

Publication Publication Date Title
JP4769953B2 (ja) マルチプルバンクｄｉｍｍにおけるマルチプルアクセスパーサイクル
JP4700636B2 (ja) 半導体メモリ装置を装着したメモリモジュールを有するシステム
JP4159415B2 (ja) メモリモジュール及びメモリシステム
JP5044849B2 (ja) 遅延線同期装置および方法
US8458507B2 (en) Bus frequency adjustment circuitry for use in a dynamic random access memory device
KR100626375B1 (ko) 고주파로 동작하는 반도체 메모리 장치 및 모듈
KR100567065B1 (ko) 메모리 장치용 입력 회로
US20130215659A1 (en) Load reduced memory module and memory system including the same
US8053911B2 (en) Semiconductor device and data processor
US11146275B2 (en) Signal generation circuit and a semiconductor apparatus using the signal generation circuit
JP4824274B2 (ja) 同期式半導体メモリ装置の出力制御信号の発生方法及び同期式半導体メモリ装置
CN104167219A (zh) 半导体装置
TWI698751B (zh) 記憶體裝置及操作記憶體裝置之延遲元件之方法
JP4327699B2 (ja) マルチチップ・パッケージおよびｉｃチップ
JP4959264B2 (ja) メモリ制御装置
KR19980030999A (ko) 동기식 메모리장치의 내부 클락 발생기
JP2002318638A (ja) 情報処理システム及び半導体集積回路装置
KR100486199B1 (ko) 반도체메모리장치의하이임피던스제어신호발생회로
JP2006065470A (ja) メモリ制御方法および装置
US7548106B2 (en) Internal read signal generator and semiconductor memory device having the same
JP2008123543A (ja) データ伝送方法、システム及びデバイス
KR100847759B1 (ko) 레지스터 칩
JP5133631B2 (ja) Ｓｄｒａｍコマンド生成回路
KR20010055904A (ko) 더블 데이터 레이트 싱크로너스 디램

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080512

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20110412

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110506

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20110527

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110527

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20110527

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140701

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

LAPS Cancellation because of no payment of annual fees