AU2001263124A1 - Multiple access per cycle in a multiple bank dimm - Google Patents

Multiple access per cycle in a multiple bank dimm

Info

Publication number
AU2001263124A1
AU2001263124A1 AU2001263124A AU6312401A AU2001263124A1 AU 2001263124 A1 AU2001263124 A1 AU 2001263124A1 AU 2001263124 A AU2001263124 A AU 2001263124A AU 6312401 A AU6312401 A AU 6312401A AU 2001263124 A1 AU2001263124 A1 AU 2001263124A1
Authority
AU
Australia
Prior art keywords
per cycle
access per
multiple access
bank dimm
dimm
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001263124A
Other languages
English (en)
Inventor
Chris Karabatsos
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of AU2001263124A1 publication Critical patent/AU2001263124A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
AU2001263124A 2000-05-17 2001-05-15 Multiple access per cycle in a multiple bank dimm Abandoned AU2001263124A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/572,641 US6446158B1 (en) 1999-05-17 2000-05-17 Memory system using FET switches to select memory banks
US09572641 2000-05-17
PCT/US2001/015592 WO2001088714A1 (en) 2000-05-17 2001-05-15 Multiple access per cycle in a multiple bank dimm

Publications (1)

Publication Number Publication Date
AU2001263124A1 true AU2001263124A1 (en) 2001-11-26

Family

ID=24288730

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001263124A Abandoned AU2001263124A1 (en) 2000-05-17 2001-05-15 Multiple access per cycle in a multiple bank dimm

Country Status (6)

Country Link
US (1) US6446158B1 (enExample)
EP (1) EP1290561B1 (enExample)
JP (1) JP4769953B2 (enExample)
CN (1) CN1436331A (enExample)
AU (1) AU2001263124A1 (enExample)
WO (1) WO2001088714A1 (enExample)

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Also Published As

Publication number Publication date
US6446158B1 (en) 2002-09-03
EP1290561B1 (en) 2019-10-23
EP1290561A1 (en) 2003-03-12
JP2004511026A (ja) 2004-04-08
JP4769953B2 (ja) 2011-09-07
CN1436331A (zh) 2003-08-13
WO2001088714A1 (en) 2001-11-22
EP1290561A4 (en) 2006-10-11

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