CN1378704A - 制造具有减反射膜的半导体存储装置的方法 - Google Patents
制造具有减反射膜的半导体存储装置的方法 Download PDFInfo
- Publication number
- CN1378704A CN1378704A CN00814181A CN00814181A CN1378704A CN 1378704 A CN1378704 A CN 1378704A CN 00814181 A CN00814181 A CN 00814181A CN 00814181 A CN00814181 A CN 00814181A CN 1378704 A CN1378704 A CN 1378704A
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- CN
- China
- Prior art keywords
- layer
- grid
- mask
- peripheral circuit
- circuit region
- Prior art date
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- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000000034 method Methods 0.000 title claims description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000011248 coating agent Substances 0.000 title 1
- 238000000576 coating method Methods 0.000 title 1
- 230000002093 peripheral effect Effects 0.000 claims abstract description 49
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 33
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 12
- 239000006117 anti-reflective coating Substances 0.000 claims description 33
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 239000012535 impurity Substances 0.000 claims description 13
- 238000003475 lamination Methods 0.000 claims description 11
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- 238000003860 storage Methods 0.000 claims description 9
- 238000002347 injection Methods 0.000 claims description 8
- 239000007924 injection Substances 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 7
- 235000012239 silicon dioxide Nutrition 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 5
- 238000012545 processing Methods 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims description 4
- 239000002019 doping agent Substances 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 230000004913 activation Effects 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- NCMAYWHYXSWFGB-UHFFFAOYSA-N [Si].[N+][O-] Chemical compound [Si].[N+][O-] NCMAYWHYXSWFGB-UHFFFAOYSA-N 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 abstract description 4
- 238000000059 patterning Methods 0.000 abstract description 2
- 230000000873 masking effect Effects 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 description 15
- 230000008901 benefit Effects 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 3
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000007667 floating Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000005192 partition Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000011017 operating method Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
- H10B41/48—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a tunnel dielectric layer also being used as part of the peripheral transistor
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/942—Masking
- Y10S438/948—Radiation resist
- Y10S438/951—Lift-off
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
- Application Of Or Painting With Fluid Materials (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
Claims (10)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/417,131 US6235587B1 (en) | 1999-10-13 | 1999-10-13 | Method of manufacturing a semiconductor device with reduced arc loss in peripheral circuitry region |
US09/417,131 | 1999-10-13 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1378704A true CN1378704A (zh) | 2002-11-06 |
CN1186812C CN1186812C (zh) | 2005-01-26 |
Family
ID=23652706
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB008141819A Expired - Lifetime CN1186812C (zh) | 1999-10-13 | 2000-09-29 | 制造具有减反射膜的半导体存储装置的方法 |
Country Status (9)
Country | Link |
---|---|
US (1) | US6235587B1 (zh) |
EP (1) | EP1222690B1 (zh) |
JP (1) | JP4944328B2 (zh) |
KR (1) | KR100717409B1 (zh) |
CN (1) | CN1186812C (zh) |
AT (1) | ATE385042T1 (zh) |
DE (1) | DE60037901T2 (zh) |
TW (1) | TW474009B (zh) |
WO (1) | WO2001027994A1 (zh) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100339962C (zh) * | 2003-07-21 | 2007-09-26 | 美格纳半导体有限会社 | 制造非挥发性存储器晶体管的方法 |
CN104425366A (zh) * | 2013-08-20 | 2015-03-18 | 中芯国际集成电路制造(北京)有限公司 | 半导体结构的形成方法 |
WO2020001549A1 (en) * | 2018-06-28 | 2020-01-02 | Changxin Memory Technologies, Inc. | Method for fabricating transistor gate, as well as transistor structure |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10221884A1 (de) * | 2002-05-16 | 2003-11-27 | Infineon Technologies Ag | Verfahren zum Herstellen einer Schicht-Anordnung, Schicht-Anordnung und Speicher-Anordnung |
US6818141B1 (en) * | 2002-06-10 | 2004-11-16 | Advanced Micro Devices, Inc. | Application of the CVD bilayer ARC as a hard mask for definition of the subresolution trench features between polysilicon wordlines |
US7186614B2 (en) * | 2003-11-10 | 2007-03-06 | Intel Corporation | Method for manufacturing high density flash memory and high performance logic on a single die |
US20080085609A1 (en) * | 2006-07-31 | 2008-04-10 | Vasek James E | Method for protecting high-topography regions during patterning of low-topography regions |
KR100760925B1 (ko) * | 2006-09-20 | 2007-09-21 | 동부일렉트로닉스 주식회사 | 반도체 소자 형성방법 |
CN104282630B (zh) * | 2013-07-02 | 2017-05-10 | 中芯国际集成电路制造(上海)有限公司 | 一种制作闪存的方法 |
JP6194684B2 (ja) * | 2013-08-05 | 2017-09-13 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2825585B2 (ja) * | 1990-01-29 | 1998-11-18 | 株式会社日立製作所 | 半導体集積回路装置及びその製造方法 |
DE69320582T2 (de) * | 1992-10-07 | 1999-04-01 | Koninklijke Philips Electronics N.V., Eindhoven | Verfahren zur Herstellung eines integrierten Schaltkreises mit einem nichtflüchtigen Speicherelement |
EP0592039B1 (en) | 1992-10-07 | 1998-08-26 | Koninklijke Philips Electronics N.V. | Method of manufacturing an integrated circuit with a non-volatile memory element |
JPH07147397A (ja) * | 1993-11-25 | 1995-06-06 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
JPH07297393A (ja) * | 1994-04-25 | 1995-11-10 | Seiko Instr Inc | 半導体装置およびその製造方法 |
TW360980B (en) | 1994-05-04 | 1999-06-11 | Nippon Precision Circuits | Single transistor EEPROM memory device |
KR0161402B1 (ko) | 1995-03-22 | 1998-12-01 | 김광호 | 불휘발성 메모리 제조방법 |
KR0182974B1 (ko) * | 1996-08-24 | 1999-03-20 | 김광호 | 플래시 불휘발성 반도체 메모리 장치 및 그 제조방법 |
US5920796A (en) | 1997-09-05 | 1999-07-06 | Advanced Micro Devices, Inc. | In-situ etch of BARC layer during formation of local interconnects |
US5933729A (en) | 1997-12-08 | 1999-08-03 | Advanced Micro Devices, Inc. | Reduction of ONO fence during self-aligned etch to eliminate poly stringers |
JP3147847B2 (ja) * | 1998-02-24 | 2001-03-19 | 日本電気株式会社 | 半導体装置及びその製造方法 |
US6004843A (en) * | 1998-05-07 | 1999-12-21 | Taiwan Semiconductor Manufacturing Company | Process for integrating a MOS logic device and a MOS memory device on a single semiconductor chip |
-
1999
- 1999-10-13 US US09/417,131 patent/US6235587B1/en not_active Expired - Lifetime
-
2000
- 2000-09-29 WO PCT/US2000/026874 patent/WO2001027994A1/en active Search and Examination
- 2000-09-29 DE DE60037901T patent/DE60037901T2/de not_active Expired - Lifetime
- 2000-09-29 EP EP00967129A patent/EP1222690B1/en not_active Expired - Lifetime
- 2000-09-29 AT AT00967129T patent/ATE385042T1/de not_active IP Right Cessation
- 2000-09-29 CN CNB008141819A patent/CN1186812C/zh not_active Expired - Lifetime
- 2000-09-29 KR KR1020027004726A patent/KR100717409B1/ko active IP Right Grant
- 2000-09-29 JP JP2001530912A patent/JP4944328B2/ja not_active Expired - Fee Related
- 2000-10-06 TW TW089120842A patent/TW474009B/zh not_active IP Right Cessation
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100339962C (zh) * | 2003-07-21 | 2007-09-26 | 美格纳半导体有限会社 | 制造非挥发性存储器晶体管的方法 |
CN104425366A (zh) * | 2013-08-20 | 2015-03-18 | 中芯国际集成电路制造(北京)有限公司 | 半导体结构的形成方法 |
CN104425366B (zh) * | 2013-08-20 | 2017-12-29 | 中芯国际集成电路制造(北京)有限公司 | 半导体结构的形成方法 |
WO2020001549A1 (en) * | 2018-06-28 | 2020-01-02 | Changxin Memory Technologies, Inc. | Method for fabricating transistor gate, as well as transistor structure |
Also Published As
Publication number | Publication date |
---|---|
EP1222690B1 (en) | 2008-01-23 |
KR100717409B1 (ko) | 2007-05-11 |
JP4944328B2 (ja) | 2012-05-30 |
DE60037901D1 (de) | 2008-03-13 |
KR20020047230A (ko) | 2002-06-21 |
ATE385042T1 (de) | 2008-02-15 |
EP1222690A1 (en) | 2002-07-17 |
TW474009B (en) | 2002-01-21 |
WO2001027994A1 (en) | 2001-04-19 |
CN1186812C (zh) | 2005-01-26 |
DE60037901T2 (de) | 2009-01-29 |
US6235587B1 (en) | 2001-05-22 |
JP2003511875A (ja) | 2003-03-25 |
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Legal Events
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C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: SPANSION CO.,LTD. Free format text: FORMER OWNER: ADVANCED MICRO DEVICES INC. Effective date: 20070413 Owner name: SPANSION CO., LTD. Free format text: FORMER OWNER: SPANSION CO.,LTD. Effective date: 20070413 |
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C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20070413 Address after: California, USA Patentee after: SPANSION LLC Address before: California, USA Patentee before: Spanson Co. Effective date of registration: 20070413 Address after: California, USA Patentee after: Spanson Co. Address before: California, USA Patentee before: ADVANCED MICRO DEVICES, Inc. |
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C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20160317 Address after: California, USA Patentee after: CYPRESS SEMICONDUCTOR Corp. Address before: California, USA Patentee before: SPANSION LLC |
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CX01 | Expiry of patent term |
Granted publication date: 20050126 |
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CX01 | Expiry of patent term |