CN1311523C - 半导体晶片、半导体元件及其制造方法 - Google Patents

半导体晶片、半导体元件及其制造方法 Download PDF

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CN1311523C
CN1311523C CNB2004100080036A CN200410008003A CN1311523C CN 1311523 C CN1311523 C CN 1311523C CN B2004100080036 A CNB2004100080036 A CN B2004100080036A CN 200410008003 A CN200410008003 A CN 200410008003A CN 1311523 C CN1311523 C CN 1311523C
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根本义彦
春原昌宏
高桥健司
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Renesas Electronics Corp
Kioxia Corp
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Abstract

本发明可以在半导体晶片与支撑板贴合前后不对运送系统进行改变而将其加以利用，同时得到能放宽对半导体晶片的加工精度以及半导体晶片与支撑板的对位精度的要求，提高半导体元件的制造效率的半导体晶片。本发明的半导体晶片在边缘部形成了通过对背面削除来进行分离的台阶部4部，该台阶部4的深度大于通过对背面进行削除加工而形成的最终加工厚度，并且它的从平坦面1a向径向外侧方向延伸的尺寸比半导体晶片1和同该半导体晶片1有大致相同直径的支撑板的直径尺寸的加工公差的最大值减最小值之差与将半导体晶片1同支撑板贴合时产生的对位误差的最大值的总和值大。

Description

半导体晶片、半导体元件及其制造方法
技术领域
本发明涉及在作为形成了半导体电路的平坦面的正表面贴合支撑板、并对其背面进行削除加工使之减薄而成的半导体晶片，利用该半导体晶片制造的半导体元件，以及该半导体元件的制造方法。
背景技术
迄今，作为半导体元件的制造方法，已知有在作为形成了半导体电路的平坦面的晶片正表面贴合用于增强半导体晶片的机械强度的支撑板、其后对半导体晶片的背面进行削除加工使之减薄来制造半导体元件的方法，与此关联的半导体元件的制造方法例如已在专利文献1中示出。
但是，这时必须将半导体晶片研磨得薄至最初厚度的1/10左右，因此存在如下的问题。
即，一般说来，因脆性强且是单晶而具有解理特性的半导体晶片随着变薄容易迅速裂开，故而当研磨到一定厚度以下，其运送是极为困难的，因此，在研磨前将其贴附到具有规定刚性的支撑板上，但是，由于必须使半导体晶片背面研磨前后的半导体晶片的运送系统和加工设备的运送系统通用化，所以用于贴附的支撑板被制成与半导体晶片有相同的直径。可是，例如在半导体晶片和支撑板两者皆有允许公差的最大值时，将两者贴合后的带有支撑板的半导体晶片整体的外径尺寸还增大一个贴合时所产生的对位误差的量，从而比所允许的整体外径尺寸大，出现无法使后工序的加工设备的运送系统运作的情形。因此，发生了例如必须制作适合于各个加工装置的夹具、附件之类的用具，在各种不同的情况下使用夹具、更换附件的情形，存在制造效率低的问题。
另外，当实际上半导体晶片从支撑板伸出时，该部分非常容易裂开，这成为不良或被污染的原因，由于事实上不允许半导体晶片伸出，所以存在对半导体晶片和支撑板的尺寸精度，以及两者的贴合位置精度要求极高的问题。
专利文献1
特开平10-335195号公报
发明内容
本发明的课题是解决上述问题，其目的在于：得到能够在半导体晶片与支撑板贴合前后不对运送系统进行改变而将其加以利用，并且可以放宽对半导体晶片的加工精度以及半导体晶片与支撑板的对位精度的要求，从而能够提高半导体元件的制造效率的半导体晶片。
另外，其目的还在于得到用该半导体晶片制造的半导体元件。
还有，其目的还在于得到该半导体元件的制造方法。
本发明提供一种半导体晶片，在形成半导体电路的为平坦面的正表面上贴合支撑板、并对半导体晶片的背面进行削除加工而成为薄板，其特征在于：在边缘部形成了通过对背面削除来进行分离的分离部，该分离部的深度大于通过对上述背面进行削除加工而形成的最终加工厚度，并且该分离部从上述平坦面向径向外侧方向延伸的尺寸比上述半导体晶片和同该半导体晶片有大致相同直径的支撑板的直径尺寸的加工公差的最大值减最小值之差与将上述半导体晶片和上述支撑板贴合时产生的对位误差的最大值的总和值大；上述分离部是由从上述正表面沿垂直方向切开的垂直面和沿水平方向切开至该垂直面的底面构成的台阶部。
本发明提供一种半导体晶片，在形成半导体电路的为平坦面的正表面上贴合支撑板、并对半导体晶片的背面进行削除加工而成为薄板，其特征在于：在边缘部形成了通过对背面削除来进行分离的分离部，该分离部的深度大于通过对上述背面进行削除加工而形成的最终加工厚度，并且该分离部从上述平坦面向径向外侧方向延伸的尺寸比上述半导体晶片和同该半导体晶片有大致相同直径的支撑板的直径尺寸的加工公差的最大值减最小值之差与将上述半导体晶片和上述支撑板贴合时产生的对位误差的最大值的总和值大；上述分离部是随着向径向的外侧其厚度逐渐变薄的薄板部。
本发明提供一种半导体晶片，在形成半导体电路的为平坦面的正表面上贴合支撑板、并对半导体晶片的背面进行削除加工而成为薄板，其特征在于：在边缘部形成了通过对背面削除来进行分离的分离部，该分离部的深度大于通过对上述背面进行削除加工而形成的最终加工厚度，并且该分离部从上述平坦面向径向外侧方向延伸的尺寸比上述半导体晶片和同该半导体晶片有大致相同直径的支撑板的直径尺寸的加工公差的最大值减最小值之差与将上述半导体晶片和上述支撑板贴合时产生的对位误差的最大值的总和值大；上述分离部是比由上述背面的削除加工而形成的最终加工厚度深的沟槽及沟槽的外周部。
本发明提供一种半导体元件，其特征在于：将具备：对上述任何一项所述的上述半导体晶片的背面进行削除而除掉了上述分离部的基底；和以及在该基底的正表面形成的半导体电路的半导体元件体分割成多个而构成。
本发明提供一种半导体元件的制造方法，其特征在于：包括：
在晶片的正表面侧的边缘部形成上述任何一项所述的分离部，从而形成半导体晶片的工序；在上述半导体晶片的正表面平坦面上形成半导体电路的工序；用粘结材料将具有大致与半导体晶片相同的直径尺寸的支撑板贴合到上述半导体晶片的正表面的工序；对上述半导体晶片的背面进行削除，从而除掉上述分离部，形成基底的工序；以及对该基底的背面进行加工处理的工序。
本发明提供一种半导体元件的制造方法，其特征在于：包括：在晶片的正表面平坦面上形成半导体电路的工序；在晶片的正表面侧的边缘部形成上述方案中的任何一项所述的分离部，从而形成半导体晶片的工序；用粘结材料将具有大致与半导体晶片相同的直径尺寸的支撑板贴合到上述半导体晶片的正表面的工序；对上述半导体晶片的背面进行削除，从而除掉上述分离部，形成基底的工序；以及对该基底的背面进行加工处理的工序。
本发明提供一种半导体元件的制造方法，其特征在于：包括：在晶片的正表面平坦面上形成半导体电路的工序；形成从上述半导体电路延伸至上述晶片的多个孔的工序；在上述晶片的边缘部形成上述方案中的任何一项所述的分离部，从而形成半导体晶片的工序；将作为导电材料的金属埋入上述孔中形成电极部的工序；用粘结材料将具有大致与半导体晶片相同的直径尺寸的支撑板贴合到上述半导体晶片的正表面的工序；对上述半导体晶片的背面进行削除，从而除掉上述分离部，形成基底，同时使上述电极部的端面露出的工序；对上述基底的背面进行削除，使上述电极部突出的工序；在上述基底的背面形成绝缘膜的工序；以及对上述电极部的端面进行加工，形成贯通电极的工序。
附图说明
图1是本发明实施例1的半导体晶片的局部剖面图。
图2是示出本发明实施例1的半导体元件的各制造工序的图。
图3是示出本发明实施例1的半导体元件的各制造工序的图。
图4是示出本发明实施例1的半导体晶片的其他例子的局部剖面图。
图5是示出本发明实施例1的半导体晶片的其他例子的局部剖面图。
图6是示出本发明实施例1的半导体晶片的其他例子的局部剖面图。
图7是示出本发明实施例1的半导体晶片的其他例子的局部剖面图。
图8是示出本发明实施例2的半导体元件的各制造工序的图。
图9是示出本发明实施例3的半导体元件的各制造工序的图。
图10是示出本发明实施例4的半导体元件的各制造工序的图。
图11(a)是不同形状的半导体晶片的平面图，图11(b)是图11(a)的半导体晶片被研磨削除后的基底的平面图。
图12(a)是另外的不同形状的半导体晶片的平面图，图12(b)是图12(a)的半导体晶片被研磨削除后的基底的平面图。
图13(a)是另外的不同形状的半导体晶片的平面图，图13(b)是图13(a)的半导体晶片被研磨削除后的基底的平面图。
图14(a)是另外的不同形状的半导体晶片的平面图，图14(b)是图14(a)的半导体晶片被研磨削除后的基底的平面图。
图15(a)是示出用图11(a)所示的半导体晶片制造的半导体元件的一道制造工序的剖面图，图15(b)是图15(a)的下一道工序的剖面图。
具体实施方式
以下说明本发明的各实施例，在各实施例中，对相同的或相当的构件、部位标以相同的符号并进行说明。
实施例1
图1是本发明实施例1的半导体晶片的局部侧向剖面图，图2(I)～(V)是示出半导体元件的制造方法的各工序的图，图3(I)～(VI)是示出图2(V)的下一道工序以后的半导体元件的制造方法的各工序的图。
在该半导体晶片1的、作为形成了半导体电路2的平坦面1a的正表面贴合支撑板3，同时对其背面进行研磨加工，制成薄板。在圆盘状的半导体晶片1的正表面边缘部形成作为分离部的台阶部4。台阶部4由从正表面沿垂直方向切开的垂直面4b和沿水平方向切开至该垂直面4b的底面4a构成。台阶部4的底面4a位于比对背面进行研磨削除后的基底5的厚度的尺寸深的位置上，并且该底面4a的宽度尺寸比半导体晶片1和同该半导体晶片1有大致相同直径的支撑板3的直径尺寸的加工公差的最大值减最小值之差与将半导体晶片1和支撑板3贴合时产生的对位误差的最大值的总和值大。
从上述半导体晶片1开始，经各制造工序制造半导体元件12，下面说明该各制造工序。
首先，通过对圆盘状的晶片的正表面侧的边缘部进行台阶加工形成台阶部4，从而形成半导体晶片1(图2(I))。接着，在半导体晶片1的正表面正表面的平坦面1a上形成半导体电路2(图2(II))。其后，用粘结材料7将具有大致与半导体晶片1相同的直径尺寸的支撑板3贴合到具有台阶部4的半导体晶片1的正表面(图2(III))。这时，在该图中，在半导体晶片1与支撑板3之间产生了贴合误差A。然后，对半导体晶片1的背面进行削除，直至厚度为原来的1/10左右的最终加工厚度，由此除掉作为分离部的台阶部4，形成基底5(图2(IV))。接着，对基底5背面进行形成绝缘膜8的加工处理，形成半导体元件体6(图2(V))。其结果是形成了用粘结材料7将半导体元件体6固定在支撑板3上的块体11。
接着，将块体11的背面贴附到在环形框架9的下面拉紧设置的支撑膜10上(图3(I))。其后，从块体11的正表面侧照射紫外线，使粘结材料7失去粘结力，使支撑板3与半导体元件体6分离(图2(II)、(III))。接着，切割半导体元件体6，将其分割为多个，形成半导体元件12(图3(IV))。最后，从支撑膜10的背面照射紫外线，使支撑膜10正表面的粘结层失去粘结力，将半导体元件12从支撑膜10上剥离，从而完成半导体元件12的制造(图3(V)、(VI)。
关于上述结构的半导体元件12，由于在半导体电路2的形成工序开始前在半导体晶片1的边缘部形成台阶部4，该台阶部4位于比半导体晶片1的最终加工厚度深的位置上，并且其宽度比半导体晶片1和同该半导体晶片1有相同直径的支撑板3的加工公差的最大值减最小值之差与将它们贴合时产生的对位误差的最大值的总和值大，在贴合到支撑板3上后，对半导体晶片1进行研磨加工，所以台阶部4因研磨加工而消失，形成其外径尺寸比半导体晶片1的外径尺寸小一个台阶部4的部分的基底5。这时，由于将半导体晶片1与支撑板3的加工公差和对位误差这两种误差考虑在内，使台阶部4的宽度尺寸为恰当的值，所以将半导体晶片1的背面研磨后的基底5不从支撑板3的外周面向外侧突出。
因此，直径与支撑板3的大致相同、在正表面形成了半导体电路2的半导体晶片1的运送系统可以在形成基底5的工序(图2(IV))后的各工序中直接利用。
另外，将半导体晶片1的背面研磨后的块体1的直径尺寸大致为支撑板3的直径的尺寸，块体11的直径尺寸的精度由支撑板3的直径尺寸的精度决定，因而对半导体晶片1的加工精度以及半导体晶片1与支撑板3的对位精度要求被放宽。
另外，由于在图2(IV)以后的工序中基底5的尺寸比支撑板3的尺寸小，所以在从基底5上分离支撑板3时可以利用该尺寸之差，从不与基底5重合的支撑板3的部分、在离开贴附了基底5的支撑膜10的方向剥离支撑板3成为可能，同基底与支撑板大致有相同尺寸的块体被贴附在支撑膜10上的状态时相比，提高了将支撑板3从基底5上分离的可操作性。
另外，作为上述半导体晶片1的分离部的台阶部4具有垂直于底面4a的垂直面4b，但也可以如图4所示，是对底面4a具有倾斜面4c的形状的台阶部4A，也可以如图5所示，是在垂直面4b与平坦面1a交叉的部位具有倒角部4d的形状的台阶部4B。
另外，也可以如图6所示，是具有从平坦面1a向边缘部其厚度逐渐变薄的薄板部4C的半导体晶片1。这时，将粘结在支撑板3上的半导体晶片1的背面研磨至厚度B，由此削除作为分离部的薄板部4C，与上述的块体11相同，块体11的直径尺寸由支撑板3的直径尺寸决定，可以得到与上面所述的半导体晶片1完全相同的作用效果。
另外，也可以如图7所示，是在底面4a的最内的内径部具有沟部4e，并且在垂直面4b与平坦面1a交叉的部位具有倒角部4d的形状的作为分离部的台阶部4D。
实施例2
图8(I)～(IV)是示出本发明实施例2的半导体元件12的制造方法的诸工序中的与实施例1不同的各工序的图。
在上述实施例1中，在平坦面1a上形成半导体电路2之前预先将半导体晶片1的边缘部减薄，这时，半导体晶片1的最终加工厚度以及将半导体晶片1与支撑板3进行贴合的装置的对位精度必须在贴合前决定。
实际上，半导体晶片1的最终加工厚度常因品种及用途而不同，采用在实施例1中所述的制造方法时，必须预先准备根据品种及用途来改变边缘部的加工形状的半导体晶片1。
与此相对照，在本实施例中，在圆盘形状的晶片50的平坦面1a上形成半导体电路2后，根据该半导体电路2的用途在晶片50的边缘部形成以规定宽度进行规定深度的台阶加工而得到的台阶部4(图8(I)～(III))，在最终加工厚度因品种及用途而不同的场合，即使未预先准备固有尺寸的台阶部4，也能够得到与实施例1相同的作用效果。另外，图8(IV)的制造工序以后的各工序与图2(IV)、图3(I)～图3(VI)所示的各制造工序相同，其说明从略。
实施例3
图9(I)～图9(VI)是示出本发明实施例3的半导体元件体6的制造方法的诸工序中的与实施例1不同的各工序的图。
在实施例2中，在图8(III)的工序中形成了作为分离部的台阶部4，本实施例的不同点在于，如图9(III)所示，取代台阶部4，在半导体晶片1的边缘部的规定位置形成比通过研磨半导体晶片1的背面而形成的基底5的厚度深的沟槽26，以沟槽26及其外周部作为分离部。
在本例中，在对支撑板3贴附后的半导体晶片1的背面进行研磨的同时，使该沟槽26外侧的半导体晶片1的外周部分离，从而形成基底5。其后的制造工序与图2(IV)、图3(I)～图3(VI)所示的各制造工序相同，还有，本实施例的作用效果与实施例2的相同。
实施例4
图10(I)～图10(VIII)是示出本发明实施例4的半导体元件30的制造方法的各工序的图。
该半导体元件30虽然具有与在正表面形成的半导体电路2电连接的贯通电极23，但该半导体元件30从晶片50开始经各制造工序制成。下面说明该各制造工序。
首先，在圆盘状的晶片50的平坦面1a上形成半导体电路2(图10(I))。然后，在利用刻蚀形成从半导体电路2延伸至晶片50的多个孔20的同时，在该边缘部形成台阶部4，由此形成半导体晶片1(图10(II))。其后，将作为导电材料的金属埋入孔20中，形成电极部21(图10(III))。其后，用粘结材料7将具有与半导体晶片1大致相同的直径尺寸的支撑板3贴合到具有作分离部的台阶部4的半导体晶片1的正表面(图10(IV))。接着，对半导体晶片1的背面进行削除，直至厚度为原来的1/10左右的最终加工厚度，由此除掉台阶部4，形成基底5。另外，由于台阶部4的深度与孔20的深度相同，所以这时在削除台阶部4的同时，电极部21的端面露出(图10(V))。接着，刻蚀基底5的背面，使电极部21突出(图10(VI))。其后，对基底5的背面进行形成绝缘膜24的加工处理后，在电极部21的端面附着金属，形成贯通电极23，从而形成具有半导体元件30的块体31(图10(VII)、(VIII))。
其后，与实施例1～3相同，利用紫外线照射，使半导体元件30与块体31分离。
在具有该贯通电极23的半导体元件30中，在通过对晶片50进行刻蚀加工形成孔20的同时，在边缘部形成了台阶部4，不需要特地设立形成台阶部4的工序。于是，在正表面形成了半导体电路2的半导体晶片1的运送系统可以在形成基底5的工序(图10(V))以后的工序中直接利用。
另外，研磨了半导体晶片1的背面，贯通电极23从背面突出后的块体31的直径尺寸是支撑板3的直径尺寸，块体31的直径尺寸精度由支撑板3的直径尺寸精度决定，因而对半导体晶片1的精度以及半导体晶片1与支撑板3的对位精度要求被放宽。
另外，由于台阶部4的深度与孔20的深度相同，所以在削除台阶部4的同时，露出了电极部21的端面，故而可以用同一工序进行台阶部4的削除和电极部21的端面露出处理，因此提高了制造效率。
实施例5
在上述各实施例中，对圆盘形状的半导体晶片1进行了说明，但本发明也可如图11(a)、(b)和图12(a)、(b)所示，应用于半导体晶片1的背面被研磨削除后的基底5的形状为环形的情形，以及如图13(a)、(b)和图14(a)、(b)所示，应用于半导体晶片1的背面被研磨削除后的基底5的形状为大致四边形的情形。
例如，在用图11(a)所示的半导体晶片1制造半导体元件12时，在制造过程中，在通过对圆盘状的晶片的正表面侧的边缘部进行台阶加工而具有台阶部4的半导体晶片1的正表面正表面的平坦面1a上形成半导体电路2，其后，用粘结材料7将具有与半导体晶片1大致相同的直径尺寸的支撑板3贴合到半导体晶片1的正表面(图15(a))。接着，对半导体晶片1的背面削除至最终加工厚度，从而除掉作为分离部的台阶部4，形成图11(b)所示的基底5(图15(b))。其后的工序与在实施例1中说明过的相同。
发明的效果
如以上所述，由于本发明的半导体晶片在边缘部形成了用于通过对背面削除来进行分离的分离部，该分离部的深度大于通过对背面进行削除加工而形成的最终加工厚度，并且它的从平坦面向径向外侧方向延伸的尺寸比上述半导体晶片和同该半导体晶片有大致相同直径的支撑板的直径尺寸的加工公差的最大值减最小值之差与将半导体晶片同支撑板贴合时产生的对位误差的最大值的总和值大，所以甚至在将半导体晶片与支撑板进行贴合后也能够与其前一样利用运送系统而不改变它，同时可以放宽对半导体晶片的加工精度以及半导体晶片与支撑板的对位精度的要求，其结果是可以提高半导体元件的制造效率。
另外，由于本发明的半导体元件通过将半导体元件体分割成多个而构成，而该半导体元件体具备：对半导体晶片的背面进行削除而除掉了分离部的基底；以及在该基底的正表面形成的半导体电路，所以提高了制造效率。
另外，由于本发明的半导体元件的制造方法包括：在晶片的正表面侧的边缘部形成分离部，从而形成半导体晶片的工序；在上述半导体晶片正表面正表面的平坦面上形成半导体电路的工序；用粘结材料将具有大致与半导体晶片相同的直径尺寸的支撑板贴合到上述半导体晶片的正表面的工序；对上述半导体晶片的背面进行削除，从而除掉上述分离部，形成基底的工序；以及对该基底的背面进行加工处理的工序，所以甚至在将半导体晶片与支撑板进行贴合后也能够与其前一样利用运送系统而不改变它，同时可以放宽对半导体晶片的加工精度以及半导体晶片与支撑板的对位精度的要求，其结果是可以提高半导体元件的制造效率。
另外，由于基底的尺寸小于支撑板的尺寸，所以提高了将支撑板从基底上分离的分离可操作性。
另外，由于本发明的半导体元件的制造方法包括：在晶片的正表面正表面的平坦面上形成半导体电路的工序；在晶片的正表面侧的边缘部形成分离部，从而形成半导体晶片的工序；用粘结材料将具有大致与半导体晶片相同的直径尺寸的支撑板贴合到上述半导体晶片的正表面的工序；对上述半导体晶片的背面进行削除，从而除掉上述分离部，形成基底的工序；以及对该基底的背面进行加工处理的工序，所以甚至在将半导体晶片与支撑板进行贴合后也能够与其前一样利用运送系统而不改变它，同时可以放宽对半导体晶片的加工精度以及半导体晶片与支撑板的对位精度的要求，其结果是可以提高半导体元件的制造效率。
另外，由于基底的尺寸小于支撑板的尺寸，所以提高了将支撑板从基底上分离的分离可操作性。
另外，在最终加工厚度因品种及用途而不同的场合，也可以不预先准备固有尺寸的分离部。
另外，由于本发明的半导体元件的制造方法包括：在晶片的正表面正表面的平坦面上形成半导体电路的工序；形成从上述半导体电路延伸至上述晶片的多个孔的工序；在上述晶片的边缘部形成分离部，从而形成半导体晶片的工序；将作为导电材料的金属埋入上述孔中形成电极部的工序；用粘结材料将具有大致与半导体晶片相同的直径尺寸的支撑板贴合到上述半导体晶片的正表面的工序；对上述半导体晶片的背面进行削除，从而除掉上述分离部，形成基底，同时使上述电极部的端面露出的工序；对上述基底的背面进行削除，使上述电极部突出的工序；在上述基底的背面形成绝缘膜的工序；以及对上述电极部的端面进行加工，形成贯通电极的工序，所以甚至在将半导体晶片与支撑板进行贴合后也能够与其前一样利用运送系统而不改变它，同时可以放宽对半导体晶片的加工精度以及半导体晶片与支撑板的对位精度的要求，其结果是可以提高半导体元件的制造效率。

Claims (9)

1.一种半导体晶片，在形成半导体电路的为平坦面的正表面上贴合支撑板、并对半导体晶片的背面进行削除加工而成为薄板，其特征在于：
在边缘部形成了通过对背面削除来进行分离的分离部，该分离部的深度大于通过对上述背面进行削除加工而形成的最终加工厚度，并且该分离部从上述平坦面向径向外侧方向延伸的尺寸比上述半导体晶片和同该半导体晶片有大致相同直径的支撑板的直径尺寸的加工公差的最大值减最小值之差与将上述半导体晶片和上述支撑板贴合时产生的对位误差的最大值的总和值大；
上述分离部是由从上述正表面沿垂直方向切开的垂直面和沿水平方向切开至该垂直面的底面构成的台阶部。
2.一种半导体晶片，在形成半导体电路的为平坦面的正表面上贴合支撑板、并对半导体晶片的背面进行削除加工而成为薄板，其特征在于：
在边缘部形成了通过对背面削除来进行分离的分离部，该分离部的深度大于通过对上述背面进行削除加工而形成的最终加工厚度，并且该分离部从上述平坦面向径向外侧方向延伸的尺寸比上述半导体晶片和同该半导体晶片有大致相同直径的支撑板的直径尺寸的加工公差的最大值减最小值之差与将上述半导体晶片和上述支撑板贴合时产生的对位误差的最大值的总和值大；
上述分离部是随着向径向的外侧其厚度逐渐变薄的薄板部。
3.一种半导体晶片，在形成半导体电路的为平坦面的正表面上贴合支撑板、并对半导体晶片的背面进行削除加工而成为薄板，其特征在于：
在边缘部形成了通过对背面削除来进行分离的分离部，该分离部的深度大于通过对上述背面进行削除加工而形成的最终加工厚度，并且该分离部从上述平坦面向径向外侧方向延伸的尺寸比上述半导体晶片和同该半导体晶片有大致相同直径的支撑板的直径尺寸的加工公差的最大值减最小值之差与将上述半导体晶片和上述支撑板贴合时产生的对位误差的最大值的总和值大；
上述分离部是比由上述背面的削除加工而形成的最终加工厚度深的沟槽及沟槽的外周部。
4.一种半导体元件，其特征在于：
将具备：
对权利要求1至3的任何一项所述的上述半导体晶片的背面进行削除而除掉了上述分离部的基底；和
以及在该基底的正表面形成的半导体电路的半导体元件体分割成多个而构成。
5.一种半导体元件的制造方法，其特征在于：
包括：
在晶片的正表面侧的边缘部形成权利要求1至3的任何一项所述的分离部，从而形成半导体晶片的工序；
在上述半导体晶片的正表面平坦面上形成半导体电路的工序；
用粘结材料将具有大致与半导体晶片相同的直径尺寸的支撑板贴合到上述半导体晶片的正表面的工序；
对上述半导体晶片的背面进行削除，从而除掉上述分离部，形成基底的工序；以及
对该基底的背面进行加工处理的工序。
6.一种半导体元件的制造方法，其特征在于：
包括：
在晶片的正表面平坦面上形成半导体电路的工序；
在晶片的正表面侧的边缘部形成权利要求1至3的任何一项所述的分离部，从而形成半导体晶片的工序；
用粘结材料将具有大致与半导体晶片相同的直径尺寸的支撑板贴合到上述半导体晶片的正表面的工序；
对上述半导体晶片的背面进行削除，从而除掉上述分离部，形成基底的工序；以及
对该基底的背面进行加工处理的工序。
7.一种半导体元件的制造方法，其特征在于：
包括：
在晶片的正表面平坦面上形成半导体电路的工序；
形成从上述半导体电路延伸至上述晶片的多个孔的工序；
在上述晶片的边缘部形成权利要求1至3的任何一项所述的分离部，从而形成半导体晶片的工序；
将作为导电材料的金属埋入上述孔中形成电极部的工序；
用粘结材料将具有大致与半导体晶片相同的直径尺寸的支撑板贴合到上述半导体晶片的正表面的工序；
对上述半导体晶片的背面进行削除，从而除掉上述分离部，形成基底，同时使上述电极部的端面露出的工序；
对上述基底的背面进行削除，使上述电极部突出的工序；
在上述基底的背面形成绝缘膜的工序；以及
对上述电极部的端面进行加工，形成贯通电极的工序。
8.如权利要求7所述的半导体元件制造方法，其特征在于：
形成上述孔的工序与形成上述分离部从而形成上述半导体晶片的工序同时进行。
9.如权利要求7所述的半导体元件制造方法，其特征在于：
上述分离部是权利要求1所述的台阶部，上述孔的深度与上述台阶部的垂直面的高度相同。
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CP01 Change in the name or title of a patent holder
CP01 Change in the name or title of a patent holder

Address after: Tokyo, Japan

Co-patentee after: Kaixia Co.,Ltd.

Patentee after: Renesas Electronics Corp.

Co-patentee after: SHINKO ELECTRIC INDUSTRIES Co.,Ltd.

Address before: Tokyo, Japan

Co-patentee before: TOSHIBA MEMORY Corp.

Patentee before: Renesas Electronics Corp.

Co-patentee before: Shinko Electric Industries Co.,Ltd.

CX01 Expiry of patent term
CX01 Expiry of patent term

Granted publication date: 20070418