CN1311523C - 半导体晶片、半导体元件及其制造方法 - Google Patents

半导体晶片、半导体元件及其制造方法 Download PDF

Info

Publication number
CN1311523C
CN1311523C CNB2004100080036A CN200410008003A CN1311523C CN 1311523 C CN1311523 C CN 1311523C CN B2004100080036 A CNB2004100080036 A CN B2004100080036A CN 200410008003 A CN200410008003 A CN 200410008003A CN 1311523 C CN1311523 C CN 1311523C
Authority
CN
China
Prior art keywords
mentioned
semiconductor wafer
wafer
back side
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CNB2004100080036A
Other languages
English (en)
Other versions
CN1577733A (zh
Inventor
根本义彦
春原昌宏
高桥健司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Renesas Electronics Corp
Kioxia Corp
Original Assignee
Renesas Technology Corp
Toshiba Corp
Shinko Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp, Toshiba Corp, Shinko Electric Co Ltd filed Critical Renesas Technology Corp
Publication of CN1577733A publication Critical patent/CN1577733A/zh
Application granted granted Critical
Publication of CN1311523C publication Critical patent/CN1311523C/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02S—GENERATION OF ELECTRIC POWER BY CONVERSION OF INFRARED RADIATION, VISIBLE LIGHT OR ULTRAVIOLET LIGHT, e.g. USING PHOTOVOLTAIC [PV] MODULES
    • H02S40/00—Components or accessories in combination with PV modules, not provided for in groups H02S10/00 - H02S30/00
    • H02S40/20—Optical components
    • H02S40/22—Light-reflecting or light-concentrating means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3043—Making grooves, e.g. cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68363—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/52—PV systems with concentrators
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/977—Thinning or removal of substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

本发明可以在半导体晶片与支撑板贴合前后不对运送系统进行改变而将其加以利用，同时得到能放宽对半导体晶片的加工精度以及半导体晶片与支撑板的对位精度的要求，提高半导体元件的制造效率的半导体晶片。本发明的半导体晶片在边缘部形成了通过对背面削除来进行分离的台阶部4部，该台阶部4的深度大于通过对背面进行削除加工而形成的最终加工厚度，并且它的从平坦面1a向径向外侧方向延伸的尺寸比半导体晶片1和同该半导体晶片1有大致相同直径的支撑板的直径尺寸的加工公差的最大值减最小值之差与将半导体晶片1同支撑板贴合时产生的对位误差的最大值的总和值大。

Description

半导体晶片、半导体元件及其制造方法
技术领域
本发明涉及在作为形成了半导体电路的平坦面的正表面贴合支撑板、并对其背面进行削除加工使之减薄而成的半导体晶片，利用该半导体晶片制造的半导体元件，以及该半导体元件的制造方法。
背景技术
迄今，作为半导体元件的制造方法，已知有在作为形成了半导体电路的平坦面的晶片正表面贴合用于增强半导体晶片的机械强度的支撑板、其后对半导体晶片的背面进行削除加工使之减薄来制造半导体元件的方法，与此关联的半导体元件的制造方法例如已在专利文献1中示出。
但是，这时必须将半导体晶片研磨得薄至最初厚度的1/10左右，因此存在如下的问题。
即，一般说来，因脆性强且是单晶而具有解理特性的半导体晶片随着变薄容易迅速裂开，故而当研磨到一定厚度以下，其运送是极为困难的，因此，在研磨前将其贴附到具有规定刚性的支撑板上，但是，由于必须使半导体晶片背面研磨前后的半导体晶片的运送系统和加工设备的运送系统通用化，所以用于贴附的支撑板被制成与半导体晶片有相同的直径。可是，例如在半导体晶片和支撑板两者皆有允许公差的最大值时，将两者贴合后的带有支撑板的半导体晶片整体的外径尺寸还增大一个贴合时所产生的对位误差的量，从而比所允许的整体外径尺寸大，出现无法使后工序的加工设备的运送系统运作的情形。因此，发生了例如必须制作适合于各个加工装置的夹具、附件之类的用具，在各种不同的情况下使用夹具、更换附件的情形，存在制造效率低的问题。
另外，当实际上半导体晶片从支撑板伸出时，该部分非常容易裂开，这成为不良或被污染的原因，由于事实上不允许半导体晶片伸出，所以存在对半导体晶片和支撑板的尺寸精度，以及两者的贴合位置精度要求极高的问题。
专利文献1
特开平10-335195号公报
发明内容
本发明的课题是解决上述问题，其目的在于：得到能够在半导体晶片与支撑板贴合前后不对运送系统进行改变而将其加以利用，并且可以放宽对半导体晶片的加工精度以及半导体晶片与支撑板的对位精度的要求，从而能够提高半导体元件的制造效率的半导体晶片。
另外，其目的还在于得到用该半导体晶片制造的半导体元件。
还有，其目的还在于得到该半导体元件的制造方法。
本发明提供一种半导体晶片，在形成半导体电路的为平坦面的正表面上贴合支撑板、并对半导体晶片的背面进行削除加工而成为薄板，其特征在于：在边缘部形成了通过对背面削除来进行分离的分离部，该分离部的深度大于通过对上述背面进行削除加工而形成的最终加工厚度，并且该分离部从上述平坦面向径向外侧方向延伸的尺寸比上述半导体晶片和同该半导体晶片有大致相同直径的支撑板的直径尺寸的加工公差的最大值减最小值之差与将上述半导体晶片和上述支撑板贴合时产生的对位误差的最大值的总和值大；上述分离部是由从上述正表面沿垂直方向切开的垂直面和沿水平方向切开至该垂直面的底面构成的台阶部。
本发明提供一种半导体晶片，在形成半导体电路的为平坦面的正表面上贴合支撑板、并对半导体晶片的背面进行削除加工而成为薄板，其特征在于：在边缘部形成了通过对背面削除来进行分离的分离部，该分离部的深度大于通过对上述背面进行削除加工而形成的最终加工厚度，并且该分离部从上述平坦面向径向外侧方向延伸的尺寸比上述半导体晶片和同该半导体晶片有大致相同直径的支撑板的直径尺寸的加工公差的最大值减最小值之差与将上述半导体晶片和上述支撑板贴合时产生的对位误差的最大值的总和值大；上述分离部是随着向径向的外侧其厚度逐渐变薄的薄板部。
本发明提供一种半导体晶片，在形成半导体电路的为平坦面的正表面上贴合支撑板、并对半导体晶片的背面进行削除加工而成为薄板，其特征在于：在边缘部形成了通过对背面削除来进行分离的分离部，该分离部的深度大于通过对上述背面进行削除加工而形成的最终加工厚度，并且该分离部从上述平坦面向径向外侧方向延伸的尺寸比上述半导体晶片和同该半导体晶片有大致相同直径的支撑板的直径尺寸的加工公差的最大值减最小值之差与将上述半导体晶片和上述支撑板贴合时产生的对位误差的最大值的总和值大；上述分离部是比由上述背面的削除加工而形成的最终加工厚度深的沟槽及沟槽的外周部。
本发明提供一种半导体元件，其特征在于：将具备：对上述任何一项所述的上述半导体晶片的背面进行削除而除掉了上述分离部的基底；和以及在该基底的正表面形成的半导体电路的半导体元件体分割成多个而构成。
本发明提供一种半导体元件的制造方法，其特征在于：包括：
在晶片的正表面侧的边缘部形成上述任何一项所述的分离部，从而形成半导体晶片的工序；在上述半导体晶片的正表面平坦面上形成半导体电路的工序；用粘结材料将具有大致与半导体晶片相同的直径尺寸的支撑板贴合到上述半导体晶片的正表面的工序；对上述半导体晶片的背面进行削除，从而除掉上述分离部，形成基底的工序；以及对该基底的背面进行加工处理的工序。
本发明提供一种半导体元件的制造方法，其特征在于：包括：在晶片的正表面平坦面上形成半导体电路的工序；在晶片的正表面侧的边缘部形成上述方案中的任何一项所述的分离部，从而形成半导体晶片的工序；用粘结材料将具有大致与半导体晶片相同的直径尺寸的支撑板贴合到上述半导体晶片的正表面的工序；对上述半导体晶片的背面进行削除，从而除掉上述分离部，形成基底的工序；以及对该基底的背面进行加工处理的工序。
本发明提供一种半导体元件的制造方法，其特征在于：包括：在晶片的正表面平坦面上形成半导体电路的工序；形成从上述半导体电路延伸至上述晶片的多个孔的工序；在上述晶片的边缘部形成上述方案中的任何一项所述的分离部，从而形成半导体晶片的工序；将作为导电材料的金属埋入上述孔中形成电极部的工序；用粘结材料将具有大致与半导体晶片相同的直径尺寸的支撑板贴合到上述半导体晶片的正表面的工序；对上述半导体晶片的背面进行削除，从而除掉上述分离部，形成基底，同时使上述电极部的端面露出的工序；对上述基底的背面进行削除，使上述电极部突出的工序；在上述基底的背面形成绝缘膜的工序；以及对上述电极部的端面进行加工，形成贯通电极的工序。
附图说明
图1是本发明实施例1的半导体晶片的局部剖面图。
图2是示出本发明实施例1的半导体元件的各制造工序的图。
图3是示出本发明实施例1的半导体元件的各制造工序的图。
图4是示出本发明实施例1的半导体晶片的其他例子的局部剖面图。
图5是示出本发明实施例1的半导体晶片的其他例子的局部剖面图。
图6是示出本发明实施例1的半导体晶片的其他例子的局部剖面图。
图7是示出本发明实施例1的半导体晶片的其他例子的局部剖面图。
图8是示出本发明实施例2的半导体元件的各制造工序的图。
图9是示出本发明实施例3的半导体元件的各制造工序的图。
图10是示出本发明实施例4的半导体元件的各制造工序的图。
图11(a)是不同形状的半导体晶片的平面图，图11(b)是图11(a)的半导体晶片被研磨削除后的基底的平面图。
图12(a)是另外的不同形状的半导体晶片的平面图，图12(b)是图12(a)的半导体晶片被研磨削除后的基底的平面图。
图13(a)是另外的不同形状的半导体晶片的平面图，图13(b)是图13(a)的半导体晶片被研磨削除后的基底的平面图。
图14(a)是另外的不同形状的半导体晶片的平面图，图14(b)是图14(a)的半导体晶片被研磨削除后的基底的平面图。
图15(a)是示出用图11(a)所示的半导体晶片制造的半导体元件的一道制造工序的剖面图，图15(b)是图15(a)的下一道工序的剖面图。
具体实施方式
以下说明本发明的各实施例，在各实施例中，对相同的或相当的构件、部位标以相同的符号并进行说明。
实施例1
图1是本发明实施例1的半导体晶片的局部侧向剖面图，图2(I)～(V)是示出半导体元件的制造方法的各工序的图，图3(I)～(VI)是示出图2(V)的下一道工序以后的半导体元件的制造方法的各工序的图。
在该半导体晶片1的、作为形成了半导体电路2的平坦面1a的正表面贴合支撑板3，同时对其背面进行研磨加工，制成薄板。在圆盘状的半导体晶片1的正表面边缘部形成作为分离部的台阶部4。台阶部4由从正表面沿垂直方向切开的垂直面4b和沿水平方向切开至该垂直面4b的底面4a构成。台阶部4的底面4a位于比对背面进行研磨削除后的基底5的厚度的尺寸深的位置上，并且该底面4a的宽度尺寸比半导体晶片1和同该半导体晶片1有大致相同直径的支撑板3的直径尺寸的加工公差的最大值减最小值之差与将半导体晶片1和支撑板3贴合时产生的对位误差的最大值的总和值大。
从上述半导体晶片1开始，经各制造工序制造半导体元件12，下面说明该各制造工序。
首先，通过对圆盘状的晶片的正表面侧的边缘部进行台阶加工形成台阶部4，从而形成半导体晶片1(图2(I))。接着，在半导体晶片1的正表面正表面的平坦面1a上形成半导体电路2(图2(II))。其后，用粘结材料7将具有大致与半导体晶片1相同的直径尺寸的支撑板3贴合到具有台阶部4的半导体晶片1的正表面(图2(III))。这时，在该图中，在半导体晶片1与支撑板3之间产生了贴合误差A。然后，对半导体晶片1的背面进行削除，直至厚度为原来的1/10左右的最终加工厚度，由此除掉作为分离部的台阶部4，形成基底5(图2(IV))。接着，对基底5背面进行形成绝缘膜8的加工处理，形成半导体元件体6(图2(V))。其结果是形成了用粘结材料7将半导体元件体6固定在支撑板3上的块体11。
接着，将块体11的背面贴附到在环形框架9的下面拉紧设置的支撑膜10上(图3(I))。其后，从块体11的正表面侧照射紫外线，使粘结材料7失去粘结力，使支撑板3与半导体元件体6分离(图2(II)、(III))。接着，切割半导体元件体6，将其分割为多个，形成半导体元件12(图3(IV))。最后，从支撑膜10的背面照射紫外线，使支撑膜10正表面的粘结层失去粘结力，将半导体元件12从支撑膜10上剥离，从而完成半导体元件12的制造(图3(V)、(VI)。
关于上述结构的半导体元件12，由于在半导体电路2的形成工序开始前在半导体晶片1的边缘部形成台阶部4，该台阶部4位于比半导体晶片1的最终加工厚度深的位置上，并且其宽度比半导体晶片1和同该半导体晶片1有相同直径的支撑板3的加工公差的最大值减最小值之差与将它们贴合时产生的对位误差的最大值的总和值大，在贴合到支撑板3上后，对半导体晶片1进行研磨加工，所以台阶部4因研磨加工而消失，形成其外径尺寸比半导体晶片1的外径尺寸小一个台阶部4的部分的基底5。这时，由于将半导体晶片1与支撑板3的加工公差和对位误差这两种误差考虑在内，使台阶部4的宽度尺寸为恰当的值，所以将半导体晶片1的背面研磨后的基底5不从支撑板3的外周面向外侧突出。
因此，直径与支撑板3的大致相同、在正表面形成了半导体电路2的半导体晶片1的运送系统可以在形成基底5的工序(图2(IV))后的各工序中直接利用。
另外，将半导体晶片1的背面研磨后的块体1的直径尺寸大致为支撑板3的直径的尺寸，块体11的直径尺寸的精度由支撑板3的直径尺寸的精度决定，因而对半导体晶片1的加工精度以及半导体晶片1与支撑板3的对位精度要求被放宽。
另外，由于在图2(IV)以后的工序中基底5的尺寸比支撑板3的尺寸小，所以在从基底5上分离支撑板3时可以利用该尺寸之差，从不与基底5重合的支撑板3的部分、在离开贴附了基底5的支撑膜10的方向剥离支撑板3成为可能，同基底与支撑板大致有相同尺寸的块体被贴附在支撑膜10上的状态时相比，提高了将支撑板3从基底5上分离的可操作性。
另外，作为上述半导体晶片1的分离部的台阶部4具有垂直于底面4a的垂直面4b，但也可以如图4所示，是对底面4a具有倾斜面4c的形状的台阶部4A，也可以如图5所示，是在垂直面4b与平坦面1a交叉的部位具有倒角部4d的形状的台阶部4B。
另外，也可以如图6所示，是具有从平坦面1a向边缘部其厚度逐渐变薄的薄板部4C的半导体晶片1。这时，将粘结在支撑板3上的半导体晶片1的背面研磨至厚度B，由此削除作为分离部的薄板部4C，与上述的块体11相同，块体11的直径尺寸由支撑板3的直径尺寸决定，可以得到与上面所述的半导体晶片1完全相同的作用效果。
另外，也可以如图7所示，是在底面4a的最内的内径部具有沟部4e，并且在垂直面4b与平坦面1a交叉的部位具有倒角部4d的形状的作为分离部的台阶部4D。
实施例2
图8(I)～(IV)是示出本发明实施例2的半导体元件12的制造方法的诸工序中的与实施例1不同的各工序的图。
在上述实施例1中，在平坦面1a上形成半导体电路2之前预先将半导体晶片1的边缘部减薄，这时，半导体晶片1的最终加工厚度以及将半导体晶片1与支撑板3进行贴合的装置的对位精度必须在贴合前决定。
实际上，半导体晶片1的最终加工厚度常因品种及用途而不同，采用在实施例1中所述的制造方法时，必须预先准备根据品种及用途来改变边缘部的加工形状的半导体晶片1。
与此相对照，在本实施例中，在圆盘形状的晶片50的平坦面1a上形成半导体电路2后，根据该半导体电路2的用途在晶片50的边缘部形成以规定宽度进行规定深度的台阶加工而得到的台阶部4(图8(I)～(III))，在最终加工厚度因品种及用途而不同的场合，即使未预先准备固有尺寸的台阶部4，也能够得到与实施例1相同的作用效果。另外，图8(IV)的制造工序以后的各工序与图2(IV)、图3(I)～图3(VI)所示的各制造工序相同，其说明从略。
实施例3
图9(I)～图9(VI)是示出本发明实施例3的半导体元件体6的制造方法的诸工序中的与实施例1不同的各工序的图。
在实施例2中，在图8(III)的工序中形成了作为分离部的台阶部4，本实施例的不同点在于，如图9(III)所示，取代台阶部4，在半导体晶片1的边缘部的规定位置形成比通过研磨半导体晶片1的背面而形成的基底5的厚度深的沟槽26，以沟槽26及其外周部作为分离部。
在本例中，在对支撑板3贴附后的半导体晶片1的背面进行研磨的同时，使该沟槽26外侧的半导体晶片1的外周部分离，从而形成基底5。其后的制造工序与图2(IV)、图3(I)～图3(VI)所示的各制造工序相同，还有，本实施例的作用效果与实施例2的相同。
实施例4
图10(I)～图10(VIII)是示出本发明实施例4的半导体元件30的制造方法的各工序的图。
该半导体元件30虽然具有与在正表面形成的半导体电路2电连接的贯通电极23，但该半导体元件30从晶片50开始经各制造工序制成。下面说明该各制造工序。
首先，在圆盘状的晶片50的平坦面1a上形成半导体电路2(图10(I))。然后，在利用刻蚀形成从半导体电路2延伸至晶片50的多个孔20的同时，在该边缘部形成台阶部4，由此形成半导体晶片1(图10(II))。其后，将作为导电材料的金属埋入孔20中，形成电极部21(图10(III))。其后，用粘结材料7将具有与半导体晶片1大致相同的直径尺寸的支撑板3贴合到具有作分离部的台阶部4的半导体晶片1的正表面(图10(IV))。接着，对半导体晶片1的背面进行削除，直至厚度为原来的1/10左右的最终加工厚度，由此除掉台阶部4，形成基底5。另外，由于台阶部4的深度与孔20的深度相同，所以这时在削除台阶部4的同时，电极部21的端面露出(图10(V))。接着，刻蚀基底5的背面，使电极部21突出(图10(VI))。其后，对基底5的背面进行形成绝缘膜24的加工处理后，在电极部21的端面附着金属，形成贯通电极23，从而形成具有半导体元件30的块体31(图10(VII)、(VIII))。
其后，与实施例1～3相同，利用紫外线照射，使半导体元件30与块体31分离。
在具有该贯通电极23的半导体元件30中，在通过对晶片50进行刻蚀加工形成孔20的同时，在边缘部形成了台阶部4，不需要特地设立形成台阶部4的工序。于是，在正表面形成了半导体电路2的半导体晶片1的运送系统可以在形成基底5的工序(图10(V))以后的工序中直接利用。
另外，研磨了半导体晶片1的背面，贯通电极23从背面突出后的块体31的直径尺寸是支撑板3的直径尺寸，块体31的直径尺寸精度由支撑板3的直径尺寸精度决定，因而对半导体晶片1的精度以及半导体晶片1与支撑板3的对位精度要求被放宽。
另外，由于台阶部4的深度与孔20的深度相同，所以在削除台阶部4的同时，露出了电极部21的端面，故而可以用同一工序进行台阶部4的削除和电极部21的端面露出处理，因此提高了制造效率。
实施例5
在上述各实施例中，对圆盘形状的半导体晶片1进行了说明，但本发明也可如图11(a)、(b)和图12(a)、(b)所示，应用于半导体晶片1的背面被研磨削除后的基底5的形状为环形的情形，以及如图13(a)、(b)和图14(a)、(b)所示，应用于半导体晶片1的背面被研磨削除后的基底5的形状为大致四边形的情形。
例如，在用图11(a)所示的半导体晶片1制造半导体元件12时，在制造过程中，在通过对圆盘状的晶片的正表面侧的边缘部进行台阶加工而具有台阶部4的半导体晶片1的正表面正表面的平坦面1a上形成半导体电路2，其后，用粘结材料7将具有与半导体晶片1大致相同的直径尺寸的支撑板3贴合到半导体晶片1的正表面(图15(a))。接着，对半导体晶片1的背面削除至最终加工厚度，从而除掉作为分离部的台阶部4，形成图11(b)所示的基底5(图15(b))。其后的工序与在实施例1中说明过的相同。
发明的效果
如以上所述，由于本发明的半导体晶片在边缘部形成了用于通过对背面削除来进行分离的分离部，该分离部的深度大于通过对背面进行削除加工而形成的最终加工厚度，并且它的从平坦面向径向外侧方向延伸的尺寸比上述半导体晶片和同该半导体晶片有大致相同直径的支撑板的直径尺寸的加工公差的最大值减最小值之差与将半导体晶片同支撑板贴合时产生的对位误差的最大值的总和值大，所以甚至在将半导体晶片与支撑板进行贴合后也能够与其前一样利用运送系统而不改变它，同时可以放宽对半导体晶片的加工精度以及半导体晶片与支撑板的对位精度的要求，其结果是可以提高半导体元件的制造效率。
另外，由于本发明的半导体元件通过将半导体元件体分割成多个而构成，而该半导体元件体具备：对半导体晶片的背面进行削除而除掉了分离部的基底；以及在该基底的正表面形成的半导体电路，所以提高了制造效率。
另外，由于本发明的半导体元件的制造方法包括：在晶片的正表面侧的边缘部形成分离部，从而形成半导体晶片的工序；在上述半导体晶片正表面正表面的平坦面上形成半导体电路的工序；用粘结材料将具有大致与半导体晶片相同的直径尺寸的支撑板贴合到上述半导体晶片的正表面的工序；对上述半导体晶片的背面进行削除，从而除掉上述分离部，形成基底的工序；以及对该基底的背面进行加工处理的工序，所以甚至在将半导体晶片与支撑板进行贴合后也能够与其前一样利用运送系统而不改变它，同时可以放宽对半导体晶片的加工精度以及半导体晶片与支撑板的对位精度的要求，其结果是可以提高半导体元件的制造效率。
另外，由于基底的尺寸小于支撑板的尺寸，所以提高了将支撑板从基底上分离的分离可操作性。
另外，由于本发明的半导体元件的制造方法包括：在晶片的正表面正表面的平坦面上形成半导体电路的工序；在晶片的正表面侧的边缘部形成分离部，从而形成半导体晶片的工序；用粘结材料将具有大致与半导体晶片相同的直径尺寸的支撑板贴合到上述半导体晶片的正表面的工序；对上述半导体晶片的背面进行削除，从而除掉上述分离部，形成基底的工序；以及对该基底的背面进行加工处理的工序，所以甚至在将半导体晶片与支撑板进行贴合后也能够与其前一样利用运送系统而不改变它，同时可以放宽对半导体晶片的加工精度以及半导体晶片与支撑板的对位精度的要求，其结果是可以提高半导体元件的制造效率。
另外，由于基底的尺寸小于支撑板的尺寸，所以提高了将支撑板从基底上分离的分离可操作性。
另外，在最终加工厚度因品种及用途而不同的场合，也可以不预先准备固有尺寸的分离部。
另外，由于本发明的半导体元件的制造方法包括：在晶片的正表面正表面的平坦面上形成半导体电路的工序；形成从上述半导体电路延伸至上述晶片的多个孔的工序；在上述晶片的边缘部形成分离部，从而形成半导体晶片的工序；将作为导电材料的金属埋入上述孔中形成电极部的工序；用粘结材料将具有大致与半导体晶片相同的直径尺寸的支撑板贴合到上述半导体晶片的正表面的工序；对上述半导体晶片的背面进行削除，从而除掉上述分离部，形成基底，同时使上述电极部的端面露出的工序；对上述基底的背面进行削除，使上述电极部突出的工序；在上述基底的背面形成绝缘膜的工序；以及对上述电极部的端面进行加工，形成贯通电极的工序，所以甚至在将半导体晶片与支撑板进行贴合后也能够与其前一样利用运送系统而不改变它，同时可以放宽对半导体晶片的加工精度以及半导体晶片与支撑板的对位精度的要求，其结果是可以提高半导体元件的制造效率。

Claims (9)

1.一种半导体晶片，在形成半导体电路的为平坦面的正表面上贴合支撑板、并对半导体晶片的背面进行削除加工而成为薄板，其特征在于：
在边缘部形成了通过对背面削除来进行分离的分离部，该分离部的深度大于通过对上述背面进行削除加工而形成的最终加工厚度，并且该分离部从上述平坦面向径向外侧方向延伸的尺寸比上述半导体晶片和同该半导体晶片有大致相同直径的支撑板的直径尺寸的加工公差的最大值减最小值之差与将上述半导体晶片和上述支撑板贴合时产生的对位误差的最大值的总和值大；
上述分离部是由从上述正表面沿垂直方向切开的垂直面和沿水平方向切开至该垂直面的底面构成的台阶部。
2.一种半导体晶片，在形成半导体电路的为平坦面的正表面上贴合支撑板、并对半导体晶片的背面进行削除加工而成为薄板，其特征在于：
在边缘部形成了通过对背面削除来进行分离的分离部，该分离部的深度大于通过对上述背面进行削除加工而形成的最终加工厚度，并且该分离部从上述平坦面向径向外侧方向延伸的尺寸比上述半导体晶片和同该半导体晶片有大致相同直径的支撑板的直径尺寸的加工公差的最大值减最小值之差与将上述半导体晶片和上述支撑板贴合时产生的对位误差的最大值的总和值大；
上述分离部是随着向径向的外侧其厚度逐渐变薄的薄板部。
3.一种半导体晶片，在形成半导体电路的为平坦面的正表面上贴合支撑板、并对半导体晶片的背面进行削除加工而成为薄板，其特征在于：
在边缘部形成了通过对背面削除来进行分离的分离部，该分离部的深度大于通过对上述背面进行削除加工而形成的最终加工厚度，并且该分离部从上述平坦面向径向外侧方向延伸的尺寸比上述半导体晶片和同该半导体晶片有大致相同直径的支撑板的直径尺寸的加工公差的最大值减最小值之差与将上述半导体晶片和上述支撑板贴合时产生的对位误差的最大值的总和值大；
上述分离部是比由上述背面的削除加工而形成的最终加工厚度深的沟槽及沟槽的外周部。
4.一种半导体元件，其特征在于：
将具备：
对权利要求1至3的任何一项所述的上述半导体晶片的背面进行削除而除掉了上述分离部的基底；和
以及在该基底的正表面形成的半导体电路的半导体元件体分割成多个而构成。
5.一种半导体元件的制造方法，其特征在于：
包括：
在晶片的正表面侧的边缘部形成权利要求1至3的任何一项所述的分离部，从而形成半导体晶片的工序；
在上述半导体晶片的正表面平坦面上形成半导体电路的工序；
用粘结材料将具有大致与半导体晶片相同的直径尺寸的支撑板贴合到上述半导体晶片的正表面的工序；
对上述半导体晶片的背面进行削除，从而除掉上述分离部，形成基底的工序；以及
对该基底的背面进行加工处理的工序。
6.一种半导体元件的制造方法，其特征在于：
包括：
在晶片的正表面平坦面上形成半导体电路的工序；
在晶片的正表面侧的边缘部形成权利要求1至3的任何一项所述的分离部，从而形成半导体晶片的工序；
用粘结材料将具有大致与半导体晶片相同的直径尺寸的支撑板贴合到上述半导体晶片的正表面的工序；
对上述半导体晶片的背面进行削除，从而除掉上述分离部，形成基底的工序；以及
对该基底的背面进行加工处理的工序。
7.一种半导体元件的制造方法，其特征在于：
包括：
在晶片的正表面平坦面上形成半导体电路的工序；
形成从上述半导体电路延伸至上述晶片的多个孔的工序；
在上述晶片的边缘部形成权利要求1至3的任何一项所述的分离部，从而形成半导体晶片的工序；
将作为导电材料的金属埋入上述孔中形成电极部的工序；
用粘结材料将具有大致与半导体晶片相同的直径尺寸的支撑板贴合到上述半导体晶片的正表面的工序；
对上述半导体晶片的背面进行削除，从而除掉上述分离部，形成基底，同时使上述电极部的端面露出的工序；
对上述基底的背面进行削除，使上述电极部突出的工序；
在上述基底的背面形成绝缘膜的工序；以及
对上述电极部的端面进行加工，形成贯通电极的工序。
8.如权利要求7所述的半导体元件制造方法，其特征在于：
形成上述孔的工序与形成上述分离部从而形成上述半导体晶片的工序同时进行。
9.如权利要求7所述的半导体元件制造方法，其特征在于：
上述分离部是权利要求1所述的台阶部，上述孔的深度与上述台阶部的垂直面的高度相同。
CNB2004100080036A 2003-07-01 2004-03-05 半导体晶片、半导体元件及其制造方法 Expired - Lifetime CN1311523C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP189574/03 2003-07-01
JP189574/2003 2003-07-01
JP2003189574A JP2005026413A (ja) 2003-07-01 2003-07-01 半導体ウエハ、半導体素子およびその製造方法

Publications (2)

Publication Number Publication Date
CN1577733A CN1577733A (zh) 2005-02-09
CN1311523C true CN1311523C (zh) 2007-04-18

Family

ID=33549791

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2004100080036A Expired - Lifetime CN1311523C (zh) 2003-07-01 2004-03-05 半导体晶片、半导体元件及其制造方法

Country Status (6)

Country Link
US (2) US7195988B2 (zh)
JP (1) JP2005026413A (zh)
KR (1) KR100661471B1 (zh)
CN (1) CN1311523C (zh)
DE (1) DE102004006494A1 (zh)
TW (1) TWI265551B (zh)

Families Citing this family (256)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8058142B2 (en) * 1996-11-04 2011-11-15 Besang Inc. Bonded semiconductor structure and method of making the same
US8018058B2 (en) * 2004-06-21 2011-09-13 Besang Inc. Semiconductor memory device
US8071438B2 (en) 2003-06-24 2011-12-06 Besang Inc. Semiconductor circuit
FR2860842B1 (fr) * 2003-10-14 2007-11-02 Tracit Technologies Procede de preparation et d'assemblage de substrats
DE102004018249B3 (de) * 2004-04-15 2006-03-16 Infineon Technologies Ag Verfahren zum Bearbeiten eines Werkstücks an einem Werkstückträger
FR2880184B1 (fr) 2004-12-28 2007-03-30 Commissariat Energie Atomique Procede de detourage d'une structure obtenue par assemblage de deux plaques
US8367524B2 (en) 2005-03-29 2013-02-05 Sang-Yun Lee Three-dimensional integrated circuit structure
US7786551B2 (en) * 2005-09-16 2010-08-31 Stats Chippac Ltd. Integrated circuit system with wafer trimming
DE102006042026B4 (de) 2006-09-07 2016-08-04 Infineon Technologies Ag Vorrichtung zum Halten eines Substrats und Verfahren zur Behandlung eines Substrats
US7988794B2 (en) * 2007-02-07 2011-08-02 Infineon Technologies Ag Semiconductor device and method
JP2009043992A (ja) * 2007-08-09 2009-02-26 Disco Abrasive Syst Ltd ウエーハの加工方法
DE102008035055B3 (de) 2008-07-26 2009-12-17 X-Fab Semiconductor Foundries Ag Verfahren zur Ausrichtung einer elektronischen CMOS-Struktur bezogen auf eine vergrabene Struktur bei gebondeten und rückgedünnten Stapeln von Halbleiterscheiben
US8362800B2 (en) 2010-10-13 2013-01-29 Monolithic 3D Inc. 3D semiconductor device including field repairable logics
US8384426B2 (en) 2009-04-14 2013-02-26 Monolithic 3D Inc. Semiconductor device and structure
US8362482B2 (en) 2009-04-14 2013-01-29 Monolithic 3D Inc. Semiconductor device and structure
US9711407B2 (en) 2009-04-14 2017-07-18 Monolithic 3D Inc. Method of manufacturing a three dimensional integrated circuit by transfer of a mono-crystalline layer
US7986042B2 (en) 2009-04-14 2011-07-26 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US9509313B2 (en) 2009-04-14 2016-11-29 Monolithic 3D Inc. 3D semiconductor device
US8754533B2 (en) 2009-04-14 2014-06-17 Monolithic 3D Inc. Monolithic three-dimensional semiconductor device and structure
US8669778B1 (en) 2009-04-14 2014-03-11 Monolithic 3D Inc. Method for design and manufacturing of a 3D semiconductor device
US8427200B2 (en) 2009-04-14 2013-04-23 Monolithic 3D Inc. 3D semiconductor device
US9577642B2 (en) 2009-04-14 2017-02-21 Monolithic 3D Inc. Method to form a 3D semiconductor device
US8058137B1 (en) 2009-04-14 2011-11-15 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US8373439B2 (en) 2009-04-14 2013-02-12 Monolithic 3D Inc. 3D semiconductor device
US8405420B2 (en) 2009-04-14 2013-03-26 Monolithic 3D Inc. System comprising a semiconductor device and structure
US8395191B2 (en) 2009-10-12 2013-03-12 Monolithic 3D Inc. Semiconductor device and structure
US8378715B2 (en) 2009-04-14 2013-02-19 Monolithic 3D Inc. Method to construct systems
US8413905B2 (en) * 2009-10-05 2013-04-09 Visa U.S.A. Inc. Portable prescription transaction payment device
FR2950734B1 (fr) * 2009-09-28 2011-12-09 Soitec Silicon On Insulator Procede de collage et de transfert d'une couche
US8148728B2 (en) 2009-10-12 2012-04-03 Monolithic 3D, Inc. Method for fabrication of a semiconductor device and structure
US8536023B2 (en) 2010-11-22 2013-09-17 Monolithic 3D Inc. Method of manufacturing a semiconductor device and structure
US11374118B2 (en) 2009-10-12 2022-06-28 Monolithic 3D Inc. Method to form a 3D integrated circuit
US11984445B2 (en) 2009-10-12 2024-05-14 Monolithic 3D Inc. 3D semiconductor devices and structures with metal layers
US10366970B2 (en) 2009-10-12 2019-07-30 Monolithic 3D Inc. 3D semiconductor device and structure
US11018133B2 (en) 2009-10-12 2021-05-25 Monolithic 3D Inc. 3D integrated circuit
US8742476B1 (en) 2012-11-27 2014-06-03 Monolithic 3D Inc. Semiconductor device and structure
US8450804B2 (en) 2011-03-06 2013-05-28 Monolithic 3D Inc. Semiconductor device and structure for heat removal
US10388863B2 (en) 2009-10-12 2019-08-20 Monolithic 3D Inc. 3D memory device and structure
US9099424B1 (en) 2012-08-10 2015-08-04 Monolithic 3D Inc. Semiconductor system, device and structure with heat removal
US10157909B2 (en) 2009-10-12 2018-12-18 Monolithic 3D Inc. 3D semiconductor device and structure
US10910364B2 (en) 2009-10-12 2021-02-02 Monolitaic 3D Inc. 3D semiconductor device
US8581349B1 (en) 2011-05-02 2013-11-12 Monolithic 3D Inc. 3D memory semiconductor device and structure
US10354995B2 (en) 2009-10-12 2019-07-16 Monolithic 3D Inc. Semiconductor memory device and structure
US8476145B2 (en) 2010-10-13 2013-07-02 Monolithic 3D Inc. Method of fabricating a semiconductor device and structure
US12027518B1 (en) 2009-10-12 2024-07-02 Monolithic 3D Inc. 3D semiconductor devices and structures with metal layers
US10043781B2 (en) 2009-10-12 2018-08-07 Monolithic 3D Inc. 3D semiconductor device and structure
CN102110121B (zh) * 2009-12-24 2015-09-23 阿里巴巴集团控股有限公司 一种数据处理方法及其系统
US8373230B1 (en) 2010-10-13 2013-02-12 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US8541819B1 (en) 2010-12-09 2013-09-24 Monolithic 3D Inc. Semiconductor device and structure
US9099526B2 (en) 2010-02-16 2015-08-04 Monolithic 3D Inc. Integrated circuit device and structure
US8492886B2 (en) 2010-02-16 2013-07-23 Monolithic 3D Inc 3D integrated circuit with logic
US8026521B1 (en) 2010-10-11 2011-09-27 Monolithic 3D Inc. Semiconductor device and structure
US8461035B1 (en) 2010-09-30 2013-06-11 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
KR101134819B1 (ko) 2010-07-02 2012-04-13 이상윤 반도체 메모리 장치의 제조 방법
US9219005B2 (en) 2011-06-28 2015-12-22 Monolithic 3D Inc. Semiconductor system and device
US9953925B2 (en) 2011-06-28 2018-04-24 Monolithic 3D Inc. Semiconductor system and device
US8901613B2 (en) 2011-03-06 2014-12-02 Monolithic 3D Inc. Semiconductor device and structure for heat removal
US10217667B2 (en) 2011-06-28 2019-02-26 Monolithic 3D Inc. 3D semiconductor device, fabrication method and system
US8642416B2 (en) 2010-07-30 2014-02-04 Monolithic 3D Inc. Method of forming three dimensional integrated circuit devices using layer transfer technique
JP2012043825A (ja) * 2010-08-12 2012-03-01 Disco Abrasive Syst Ltd ウエーハの加工方法
US10497713B2 (en) 2010-11-18 2019-12-03 Monolithic 3D Inc. 3D semiconductor memory device and structure
US8273610B2 (en) 2010-11-18 2012-09-25 Monolithic 3D Inc. Method of constructing a semiconductor device and structure
US8163581B1 (en) 2010-10-13 2012-04-24 Monolith IC 3D Semiconductor and optoelectronic devices
US11482440B2 (en) 2010-12-16 2022-10-25 Monolithic 3D Inc. 3D semiconductor device and structure with a built-in test circuit for repairing faulty circuits
US11227897B2 (en) 2010-10-11 2022-01-18 Monolithic 3D Inc. Method for producing a 3D semiconductor memory device and structure
US8114757B1 (en) 2010-10-11 2012-02-14 Monolithic 3D Inc. Semiconductor device and structure
US11469271B2 (en) 2010-10-11 2022-10-11 Monolithic 3D Inc. Method to produce 3D semiconductor devices and structures with memory
US11257867B1 (en) 2010-10-11 2022-02-22 Monolithic 3D Inc. 3D semiconductor device and structure with oxide bonds
US11024673B1 (en) 2010-10-11 2021-06-01 Monolithic 3D Inc. 3D semiconductor device and structure
US11315980B1 (en) 2010-10-11 2022-04-26 Monolithic 3D Inc. 3D semiconductor device and structure with transistors
US10290682B2 (en) 2010-10-11 2019-05-14 Monolithic 3D Inc. 3D IC semiconductor device and structure with stacked memory
US11158674B2 (en) 2010-10-11 2021-10-26 Monolithic 3D Inc. Method to produce a 3D semiconductor device and structure
US10896931B1 (en) 2010-10-11 2021-01-19 Monolithic 3D Inc. 3D semiconductor device and structure
US11600667B1 (en) 2010-10-11 2023-03-07 Monolithic 3D Inc. Method to produce 3D semiconductor devices and structures with memory
US11018191B1 (en) 2010-10-11 2021-05-25 Monolithic 3D Inc. 3D semiconductor device and structure
US11164898B2 (en) 2010-10-13 2021-11-02 Monolithic 3D Inc. Multilevel semiconductor device and structure
US11404466B2 (en) 2010-10-13 2022-08-02 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors
US11605663B2 (en) 2010-10-13 2023-03-14 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US11694922B2 (en) 2010-10-13 2023-07-04 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US10833108B2 (en) 2010-10-13 2020-11-10 Monolithic 3D Inc. 3D microdisplay device and structure
US10943934B2 (en) 2010-10-13 2021-03-09 Monolithic 3D Inc. Multilevel semiconductor device and structure
US11163112B2 (en) 2010-10-13 2021-11-02 Monolithic 3D Inc. Multilevel semiconductor device and structure with electromagnetic modulators
US8379458B1 (en) 2010-10-13 2013-02-19 Monolithic 3D Inc. Semiconductor device and structure
US12080743B2 (en) 2010-10-13 2024-09-03 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US11984438B2 (en) 2010-10-13 2024-05-14 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US10978501B1 (en) 2010-10-13 2021-04-13 Monolithic 3D Inc. Multilevel semiconductor device and structure with waveguides
US10998374B1 (en) 2010-10-13 2021-05-04 Monolithic 3D Inc. Multilevel semiconductor device and structure
US11855114B2 (en) 2010-10-13 2023-12-26 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US9197804B1 (en) 2011-10-14 2015-11-24 Monolithic 3D Inc. Semiconductor and optoelectronic devices
US11133344B2 (en) 2010-10-13 2021-09-28 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors
US11043523B1 (en) 2010-10-13 2021-06-22 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors
US10679977B2 (en) 2010-10-13 2020-06-09 Monolithic 3D Inc. 3D microdisplay device and structure
US11855100B2 (en) 2010-10-13 2023-12-26 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US11929372B2 (en) 2010-10-13 2024-03-12 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US11327227B2 (en) 2010-10-13 2022-05-10 Monolithic 3D Inc. Multilevel semiconductor device and structure with electromagnetic modulators
US12094892B2 (en) 2010-10-13 2024-09-17 Monolithic 3D Inc. 3D micro display device and structure
US11437368B2 (en) 2010-10-13 2022-09-06 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US11869915B2 (en) 2010-10-13 2024-01-09 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US11063071B1 (en) 2010-10-13 2021-07-13 Monolithic 3D Inc. Multilevel semiconductor device and structure with waveguides
US11018042B1 (en) 2010-11-18 2021-05-25 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11569117B2 (en) 2010-11-18 2023-01-31 Monolithic 3D Inc. 3D semiconductor device and structure with single-crystal layers
US11482439B2 (en) 2010-11-18 2022-10-25 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device comprising charge trap junction-less transistors
US11443971B2 (en) 2010-11-18 2022-09-13 Monolithic 3D Inc. 3D semiconductor device and structure with memory
US11862503B2 (en) 2010-11-18 2024-01-02 Monolithic 3D Inc. Method for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11508605B2 (en) 2010-11-18 2022-11-22 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11355381B2 (en) 2010-11-18 2022-06-07 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11107721B2 (en) 2010-11-18 2021-08-31 Monolithic 3D Inc. 3D semiconductor device and structure with NAND logic
US11901210B2 (en) 2010-11-18 2024-02-13 Monolithic 3D Inc. 3D semiconductor device and structure with memory
US11121021B2 (en) 2010-11-18 2021-09-14 Monolithic 3D Inc. 3D semiconductor device and structure
US12068187B2 (en) 2010-11-18 2024-08-20 Monolithic 3D Inc. 3D semiconductor device and structure with bonding and DRAM memory cells
US11164770B1 (en) 2010-11-18 2021-11-02 Monolithic 3D Inc. Method for producing a 3D semiconductor memory device and structure
US11211279B2 (en) 2010-11-18 2021-12-28 Monolithic 3D Inc. Method for processing a 3D integrated circuit and structure
US12100611B2 (en) 2010-11-18 2024-09-24 Monolithic 3D Inc. Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11610802B2 (en) 2010-11-18 2023-03-21 Monolithic 3D Inc. Method for producing a 3D semiconductor device and structure with single crystal transistors and metal gate electrodes
US11735462B2 (en) 2010-11-18 2023-08-22 Monolithic 3D Inc. 3D semiconductor device and structure with single-crystal layers
US11495484B2 (en) 2010-11-18 2022-11-08 Monolithic 3D Inc. 3D semiconductor devices and structures with at least two single-crystal layers
US11482438B2 (en) 2010-11-18 2022-10-25 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device and structure
US11923230B1 (en) 2010-11-18 2024-03-05 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US11094576B1 (en) 2010-11-18 2021-08-17 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device and structure
US11804396B2 (en) 2010-11-18 2023-10-31 Monolithic 3D Inc. Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US12033884B2 (en) 2010-11-18 2024-07-09 Monolithic 3D Inc. Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11355380B2 (en) 2010-11-18 2022-06-07 Monolithic 3D Inc. Methods for producing 3D semiconductor memory device and structure utilizing alignment marks
US11004719B1 (en) 2010-11-18 2021-05-11 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device and structure
US11031275B2 (en) 2010-11-18 2021-06-08 Monolithic 3D Inc. 3D semiconductor device and structure with memory
US11615977B2 (en) 2010-11-18 2023-03-28 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11854857B1 (en) 2010-11-18 2023-12-26 Monolithic 3D Inc. Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11521888B2 (en) 2010-11-18 2022-12-06 Monolithic 3D Inc. 3D semiconductor device and structure with high-k metal gate transistors
US11784082B2 (en) 2010-11-18 2023-10-10 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US20120129318A1 (en) * 2010-11-24 2012-05-24 Semiconductor Energy Laboratory Co., Ltd. Atmospheric pressure plasma etching apparatus and method for manufacturing soi substrate
US8975670B2 (en) 2011-03-06 2015-03-10 Monolithic 3D Inc. Semiconductor device and structure for heat removal
JP2013008915A (ja) * 2011-06-27 2013-01-10 Toshiba Corp 基板加工方法及び基板加工装置
US10388568B2 (en) 2011-06-28 2019-08-20 Monolithic 3D Inc. 3D semiconductor device and system
US8687399B2 (en) 2011-10-02 2014-04-01 Monolithic 3D Inc. Semiconductor device and structure
US9029173B2 (en) 2011-10-18 2015-05-12 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
JP2013131652A (ja) * 2011-12-21 2013-07-04 Fujitsu Semiconductor Ltd 半導体装置の製造方法、半導体ウェハの加工方法、半導体ウェハ
US9000557B2 (en) 2012-03-17 2015-04-07 Zvi Or-Bach Semiconductor device and structure
US11410912B2 (en) 2012-04-09 2022-08-09 Monolithic 3D Inc. 3D semiconductor device with vias and isolation layers
US11694944B1 (en) 2012-04-09 2023-07-04 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11476181B1 (en) 2012-04-09 2022-10-18 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11616004B1 (en) 2012-04-09 2023-03-28 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11881443B2 (en) 2012-04-09 2024-01-23 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11088050B2 (en) 2012-04-09 2021-08-10 Monolithic 3D Inc. 3D semiconductor device with isolation layers
US11164811B2 (en) 2012-04-09 2021-11-02 Monolithic 3D Inc. 3D semiconductor device with isolation layers and oxide-to-oxide bonding
US11594473B2 (en) 2012-04-09 2023-02-28 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US8557632B1 (en) 2012-04-09 2013-10-15 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US10600888B2 (en) 2012-04-09 2020-03-24 Monolithic 3D Inc. 3D semiconductor device
US11735501B1 (en) 2012-04-09 2023-08-22 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US9343348B2 (en) 2012-06-12 2016-05-17 Erich Thallner Substrate-product substrate combination and device and method for producing a substrate-product substrate combination
JP5962759B2 (ja) * 2012-06-29 2016-08-03 日立化成株式会社 半導体装置の製造方法
JP6057592B2 (ja) * 2012-08-06 2017-01-11 株式会社ディスコ ウエーハの加工方法
JP6116155B2 (ja) * 2012-08-20 2017-04-19 株式会社ディスコ ウエーハの加工方法
JP6013831B2 (ja) * 2012-08-21 2016-10-25 株式会社ディスコ ウエーハの加工方法
JP2014053351A (ja) * 2012-09-05 2014-03-20 Disco Abrasive Syst Ltd ウエーハの加工方法
JP2014056910A (ja) * 2012-09-12 2014-03-27 Tokyo Electron Ltd 塗布処理装置、接合システム、塗布処理方法、プログラム及びコンピュータ記憶媒体
JP2014063919A (ja) 2012-09-21 2014-04-10 Disco Abrasive Syst Ltd ウエーハの加工方法
US8574929B1 (en) 2012-11-16 2013-11-05 Monolithic 3D Inc. Method to form a 3D semiconductor device and structure
US8686428B1 (en) 2012-11-16 2014-04-01 Monolithic 3D Inc. Semiconductor device and structure
US11967583B2 (en) 2012-12-22 2024-04-23 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11784169B2 (en) 2012-12-22 2023-10-10 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11916045B2 (en) 2012-12-22 2024-02-27 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11063024B1 (en) 2012-12-22 2021-07-13 Monlithic 3D Inc. Method to form a 3D semiconductor device and structure
US11217565B2 (en) 2012-12-22 2022-01-04 Monolithic 3D Inc. Method to form a 3D semiconductor device and structure
US8674470B1 (en) 2012-12-22 2014-03-18 Monolithic 3D Inc. Semiconductor device and structure
US11018116B2 (en) 2012-12-22 2021-05-25 Monolithic 3D Inc. Method to form a 3D semiconductor device and structure
US11961827B1 (en) 2012-12-22 2024-04-16 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US12051674B2 (en) 2012-12-22 2024-07-30 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11309292B2 (en) 2012-12-22 2022-04-19 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US10600657B2 (en) 2012-12-29 2020-03-24 Monolithic 3D Inc 3D semiconductor device and structure
US11430667B2 (en) 2012-12-29 2022-08-30 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US9871034B1 (en) 2012-12-29 2018-01-16 Monolithic 3D Inc. Semiconductor device and structure
US11430668B2 (en) 2012-12-29 2022-08-30 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US10892169B2 (en) 2012-12-29 2021-01-12 Monolithic 3D Inc. 3D semiconductor device and structure
US10903089B1 (en) 2012-12-29 2021-01-26 Monolithic 3D Inc. 3D semiconductor device and structure
US9385058B1 (en) 2012-12-29 2016-07-05 Monolithic 3D Inc. Semiconductor device and structure
US11004694B1 (en) 2012-12-29 2021-05-11 Monolithic 3D Inc. 3D semiconductor device and structure
US10651054B2 (en) 2012-12-29 2020-05-12 Monolithic 3D Inc. 3D semiconductor device and structure
US11177140B2 (en) 2012-12-29 2021-11-16 Monolithic 3D Inc. 3D semiconductor device and structure
US11087995B1 (en) 2012-12-29 2021-08-10 Monolithic 3D Inc. 3D semiconductor device and structure
US10115663B2 (en) 2012-12-29 2018-10-30 Monolithic 3D Inc. 3D semiconductor device and structure
CN103928290B (zh) * 2013-01-11 2016-08-10 中芯国际集成电路制造(上海)有限公司 晶圆边缘的刻蚀方法
US11935949B1 (en) 2013-03-11 2024-03-19 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and memory cells
US11869965B2 (en) 2013-03-11 2024-01-09 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and memory cells
US8902663B1 (en) 2013-03-11 2014-12-02 Monolithic 3D Inc. Method of maintaining a memory state
US10325651B2 (en) 2013-03-11 2019-06-18 Monolithic 3D Inc. 3D semiconductor device with stacked memory
US12094965B2 (en) 2013-03-11 2024-09-17 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and memory cells
US12100646B2 (en) 2013-03-12 2024-09-24 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US8994404B1 (en) 2013-03-12 2015-03-31 Monolithic 3D Inc. Semiconductor device and structure
US11398569B2 (en) 2013-03-12 2022-07-26 Monolithic 3D Inc. 3D semiconductor device and structure
US11923374B2 (en) 2013-03-12 2024-03-05 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11088130B2 (en) 2014-01-28 2021-08-10 Monolithic 3D Inc. 3D semiconductor device and structure
US10840239B2 (en) 2014-08-26 2020-11-17 Monolithic 3D Inc. 3D semiconductor device and structure
US9117749B1 (en) 2013-03-15 2015-08-25 Monolithic 3D Inc. Semiconductor device and structure
US10224279B2 (en) 2013-03-15 2019-03-05 Monolithic 3D Inc. Semiconductor device and structure
JP5921473B2 (ja) * 2013-03-21 2016-05-24 株式会社東芝 半導体装置の製造方法
US11270055B1 (en) 2013-04-15 2022-03-08 Monolithic 3D Inc. Automation for monolithic 3D devices
US11341309B1 (en) 2013-04-15 2022-05-24 Monolithic 3D Inc. Automation for monolithic 3D devices
US11574109B1 (en) 2013-04-15 2023-02-07 Monolithic 3D Inc Automation methods for 3D integrated circuits and devices
US11030371B2 (en) 2013-04-15 2021-06-08 Monolithic 3D Inc. Automation for monolithic 3D devices
US11720736B2 (en) 2013-04-15 2023-08-08 Monolithic 3D Inc. Automation methods for 3D integrated circuits and devices
US11487928B2 (en) 2013-04-15 2022-11-01 Monolithic 3D Inc. Automation for monolithic 3D devices
US9021414B1 (en) 2013-04-15 2015-04-28 Monolithic 3D Inc. Automation for monolithic 3D devices
JP6197422B2 (ja) * 2013-07-11 2017-09-20 富士通セミコンダクター株式会社 半導体装置の製造方法および支持基板付きウェハ
TWI671141B (zh) * 2013-08-30 2019-09-11 半導體能源研究所股份有限公司 支撐體供應裝置及供應支撐體的方法
US8906745B1 (en) * 2013-09-12 2014-12-09 Micro Processing Technology, Inc. Method using fluid pressure to remove back metal from semiconductor wafer scribe streets
CN104576350B (zh) * 2013-10-23 2018-06-01 中芯国际集成电路制造(上海)有限公司 晶圆减薄方法
CN104716017B (zh) * 2013-12-13 2017-10-24 上海华虹宏力半导体制造有限公司 改善晶圆边缘处理的方法
US11107808B1 (en) 2014-01-28 2021-08-31 Monolithic 3D Inc. 3D semiconductor device and structure
US12094829B2 (en) 2014-01-28 2024-09-17 Monolithic 3D Inc. 3D semiconductor device and structure
US10297586B2 (en) 2015-03-09 2019-05-21 Monolithic 3D Inc. Methods for processing a 3D semiconductor device
US11031394B1 (en) 2014-01-28 2021-06-08 Monolithic 3D Inc. 3D semiconductor device and structure
KR102261814B1 (ko) * 2014-06-16 2021-06-07 삼성전자주식회사 반도체 패키지의 제조 방법
US20150371956A1 (en) * 2014-06-19 2015-12-24 Globalfoundries Inc. Crackstops for bulk semiconductor wafers
US10381328B2 (en) 2015-04-19 2019-08-13 Monolithic 3D Inc. Semiconductor device and structure
US11011507B1 (en) 2015-04-19 2021-05-18 Monolithic 3D Inc. 3D semiconductor device and structure
US11056468B1 (en) 2015-04-19 2021-07-06 Monolithic 3D Inc. 3D semiconductor device and structure
US10825779B2 (en) 2015-04-19 2020-11-03 Monolithic 3D Inc. 3D semiconductor device and structure
US11956952B2 (en) 2015-08-23 2024-04-09 Monolithic 3D Inc. Semiconductor memory device and structure
JP6410152B2 (ja) * 2015-09-11 2018-10-24 東芝メモリ株式会社 半導体装置の製造方法
US12100658B2 (en) 2015-09-21 2024-09-24 Monolithic 3D Inc. Method to produce a 3D multilayer semiconductor device and structure
US11114427B2 (en) 2015-11-07 2021-09-07 Monolithic 3D Inc. 3D semiconductor processor and memory device and structure
US11978731B2 (en) 2015-09-21 2024-05-07 Monolithic 3D Inc. Method to produce a multi-level semiconductor memory device and structure
US10515981B2 (en) 2015-09-21 2019-12-24 Monolithic 3D Inc. Multilevel semiconductor device and structure with memory
US11937422B2 (en) 2015-11-07 2024-03-19 Monolithic 3D Inc. Semiconductor memory device and structure
US10522225B1 (en) 2015-10-02 2019-12-31 Monolithic 3D Inc. Semiconductor device with non-volatile memory
US11296115B1 (en) 2015-10-24 2022-04-05 Monolithic 3D Inc. 3D semiconductor device and structure
US11114464B2 (en) 2015-10-24 2021-09-07 Monolithic 3D Inc. 3D semiconductor device and structure
US11991884B1 (en) 2015-10-24 2024-05-21 Monolithic 3D Inc. 3D semiconductor device and structure with logic and memory
US12016181B2 (en) 2015-10-24 2024-06-18 Monolithic 3D Inc. 3D semiconductor device and structure with logic and memory
US12035531B2 (en) 2015-10-24 2024-07-09 Monolithic 3D Inc. 3D semiconductor device and structure with logic and memory
US10847540B2 (en) 2015-10-24 2020-11-24 Monolithic 3D Inc. 3D semiconductor memory device and structure
US10418369B2 (en) 2015-10-24 2019-09-17 Monolithic 3D Inc. Multi-level semiconductor memory device and structure
JP6676365B2 (ja) * 2015-12-21 2020-04-08 キヤノン株式会社 撮像装置の製造方法
US10804407B2 (en) 2016-05-12 2020-10-13 Semiconductor Energy Laboratory Co., Ltd. Laser processing apparatus and stack processing apparatus
DE102016109693B4 (de) * 2016-05-25 2022-10-27 Infineon Technologies Ag Verfahren zum Trennen von Halbleiterdies von einem Halbleitersubstrat und Halbleitersubstratanordnung
US11812620B2 (en) 2016-10-10 2023-11-07 Monolithic 3D Inc. 3D DRAM memory devices and structures with control circuits
US11329059B1 (en) 2016-10-10 2022-05-10 Monolithic 3D Inc. 3D memory devices and structures with thinned single crystal substrates
US11869591B2 (en) 2016-10-10 2024-01-09 Monolithic 3D Inc. 3D memory devices and structures with control circuits
US11930648B1 (en) 2016-10-10 2024-03-12 Monolithic 3D Inc. 3D memory devices and structures with metal layers
US11711928B2 (en) 2016-10-10 2023-07-25 Monolithic 3D Inc. 3D memory devices and structures with control circuits
US11251149B2 (en) 2016-10-10 2022-02-15 Monolithic 3D Inc. 3D memory device and structure
KR102524962B1 (ko) 2016-11-14 2023-04-21 삼성전자주식회사 기판 구조체 제조 방법 및 이를 이용하여 제조된 기판 구조체
JP7025235B2 (ja) * 2017-04-19 2022-02-24 キヤノン株式会社 パターン形成方法および物品製造方法
US10388535B1 (en) * 2018-05-25 2019-08-20 Powertech Technology Inc. Wafer processing method with full edge trimming
JP7242220B2 (ja) * 2018-09-03 2023-03-20 キヤノン株式会社 接合ウェハ及びその製造方法、並びにスルーホール形成方法
JP7187115B2 (ja) * 2018-12-04 2022-12-12 株式会社ディスコ ウェーハの加工方法
CN113272938B (zh) * 2018-12-11 2024-09-10 超极存储器股份有限公司 半导体模块的制造方法
US11018156B2 (en) 2019-04-08 2021-05-25 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US11296106B2 (en) 2019-04-08 2022-04-05 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US11763864B2 (en) 2019-04-08 2023-09-19 Monolithic 3D Inc. 3D memory semiconductor devices and structures with bit-line pillars
US10892016B1 (en) 2019-04-08 2021-01-12 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US11158652B1 (en) 2019-04-08 2021-10-26 Monolithic 3D Inc. 3D memory semiconductor devices and structures
JP7103305B2 (ja) * 2019-05-29 2022-07-20 信越半導体株式会社 インゴットの切断方法
CN111063649B (zh) * 2019-12-03 2022-11-01 深圳市华星光电半导体显示技术有限公司 Micro LED的转移方法及转移装置
JP2022046207A (ja) 2020-09-10 2022-03-23 キオクシア株式会社 半導体装置の製造方法、及び半導体装置
US11841296B2 (en) * 2021-12-02 2023-12-12 Globalfoundries U.S. Inc. Semiconductor substrates for electrical resistivity measurements
TWI810862B (zh) * 2022-03-24 2023-08-01 南茂科技股份有限公司 工件載具

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5384008A (en) * 1993-06-18 1995-01-24 Applied Materials, Inc. Process and apparatus for full wafer deposition
CN1123466A (zh) * 1994-08-25 1996-05-29 株式会社日立制作所 曝光方法以及用该方法制造半导体集成电路器件的方法
US6374508B1 (en) * 1998-06-12 2002-04-23 Applied Materials, Inc. Apparatus and method for aligning a substrate on a support member
JP2003059852A (ja) * 2001-08-10 2003-02-28 Dainippon Screen Mfg Co Ltd 基板の熱処理装置

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6088535U (ja) * 1983-11-24 1985-06-18 住友電気工業株式会社 半導体ウエハ
US5225235A (en) * 1987-05-18 1993-07-06 Osaka Titanium Co., Ltd. Semiconductor wafer and manufacturing method therefor
JP2645478B2 (ja) * 1988-10-07 1997-08-25 富士通株式会社 半導体装置の製造方法
JPH0485827A (ja) 1990-07-26 1992-03-18 Fujitsu Ltd 半導体装置の製造方法
JP2691244B2 (ja) 1990-11-28 1997-12-17 株式会社日立製作所 誘電体分離基板
JPH06215993A (ja) 1993-01-14 1994-08-05 Ube Ind Ltd 複合半導体基板及びその製造方法
US5937312A (en) 1995-03-23 1999-08-10 Sibond L.L.C. Single-etch stop process for the manufacture of silicon-on-insulator wafers
US6291315B1 (en) * 1996-07-11 2001-09-18 Denso Corporation Method for etching trench in manufacturing semiconductor devices
US5821166A (en) * 1996-12-12 1998-10-13 Komatsu Electronic Metals Co., Ltd. Method of manufacturing semiconductor wafers
JPH10270298A (ja) 1997-03-27 1998-10-09 Mitsubishi Materials Shilicon Corp 張り合わせ基板の製造方法
JP3368799B2 (ja) * 1997-05-22 2003-01-20 住友電気工業株式会社 Ｉｉｉ−ｖ族化合物半導体ウェハおよびその製造方法
JPH10335195A (ja) 1997-05-27 1998-12-18 Mitsubishi Materials Shilicon Corp 張り合わせ基板の製造方法
JP3390660B2 (ja) 1998-04-28 2003-03-24 株式会社日立製作所 誘電体分離基板の製造方法
JP3515917B2 (ja) 1998-12-01 2004-04-05 シャープ株式会社 半導体装置の製造方法
WO2001033614A1 (en) * 1999-11-02 2001-05-10 University Of Hawaii Method for fabricating arrays of micro-needles
US20010038153A1 (en) * 2000-01-07 2001-11-08 Kiyofumi Sakaguchi Semiconductor substrate and process for its production
JP4846915B2 (ja) 2000-03-29 2011-12-28 信越半導体株式会社 貼り合わせウェーハの製造方法
JP3991300B2 (ja) * 2000-04-28 2007-10-17 株式会社Ｓｕｍｃｏ 張り合わせ誘電体分離ウェーハの製造方法
JP2001345294A (ja) * 2000-05-31 2001-12-14 Toshiba Corp 半導体装置の製造方法
TW475168B (en) * 2000-05-31 2002-02-01 Via Tech Inc Processing method for disk drive reading
US6482749B1 (en) * 2000-08-10 2002-11-19 Seh America, Inc. Method for etching a wafer edge using a potassium-based chemical oxidizer in the presence of hydrofluoric acid
JP2002343972A (ja) 2001-05-15 2002-11-29 Sony Corp 半導体素子の製造方法
JP3802507B2 (ja) * 2002-05-20 2006-07-26 株式会社ルネサステクノロジ 半導体装置の製造方法
US7258931B2 (en) * 2002-08-29 2007-08-21 Samsung Electronics Co., Ltd. Semiconductor wafers having asymmetric edge profiles that facilitate high yield processing by inhibiting particulate contamination
US6790748B2 (en) * 2002-12-19 2004-09-14 Intel Corporation Thinning techniques for wafer-to-wafer vertical stacks

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5384008A (en) * 1993-06-18 1995-01-24 Applied Materials, Inc. Process and apparatus for full wafer deposition
CN1123466A (zh) * 1994-08-25 1996-05-29 株式会社日立制作所 曝光方法以及用该方法制造半导体集成电路器件的方法
US6374508B1 (en) * 1998-06-12 2002-04-23 Applied Materials, Inc. Apparatus and method for aligning a substrate on a support member
JP2003059852A (ja) * 2001-08-10 2003-02-28 Dainippon Screen Mfg Co Ltd 基板の熱処理装置

Also Published As

Publication number Publication date
JP2005026413A (ja) 2005-01-27
KR20050003974A (ko) 2005-01-12
TWI265551B (en) 2006-11-01
US7709932B2 (en) 2010-05-04
US20060038260A1 (en) 2006-02-23
US20050023647A1 (en) 2005-02-03
DE102004006494A1 (de) 2005-01-27
TW200503050A (en) 2005-01-16
KR100661471B1 (ko) 2006-12-27
CN1577733A (zh) 2005-02-09
US7195988B2 (en) 2007-03-27

Similar Documents

Publication Publication Date Title
CN1311523C (zh) 半导体晶片、半导体元件及其制造方法
CN1868040A (zh) 表面保护用板以及半导体晶片的磨削方法
CN1174479C (zh) 半导体装置的制造方法
CN1146032C (zh) 电子元件的小片接合方法及其小片接合装置
CN1292455C (zh) 半导体器件及其制造方法
CN1601704A (zh) 晶片的加工方法
CN1536646A (zh) 半导体器件的制造方法
CN1681961A (zh) Pvd靶和处理pvd靶的方法
CN1581443A (zh) 晶片加工方法
JP2007096229A (ja) ウエーハの加工方法
EP2751831B1 (en) Discontinuous patterned bonds for semiconductor devices and associated systems and methods
CN1837311A (zh) 用于制造供半导体生产使用的胶带的装置和方法
CN101066004A (zh) 具有被导电材料填充的通孔的基板的制造方法
CN1620713A (zh) 加工衬底,特别是半导体晶片
CN1242493C (zh) 半导体芯片的制造方法
CN1969381A (zh) 在工件支承件上对工件进行机械加工的方法
CN103295892B (zh) 半导体装置的制造方法
CN1933196A (zh) 发光器件及其制造方法
JP2008306119A (ja) 分離装置及び分離方法
CN1834608A (zh) 以半导体硅加工技术制备的样品支架
JP2005150434A (ja) 半導体ウェーハの製造方法
CN1291267C (zh) 液晶显示板的生产方法
CN1591787A (zh) 切削方法、切削装置及半导体器件的制造方法
CN103296155B (zh) 一种薄膜led外延芯片的制造方法
CN1577778A (zh) 半导体器件的制造方法及半导体制造装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
ASS Succession or assignment of patent right

Owner name: RENESAS TECH CORP.

Free format text: FORMER OWNER: MITSUBISHI ELECTRIC CO., LTD.

C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20050805

Address after: Tokyo, Japan

Applicant after: Renesas Technology Corp.

Co-applicant after: Toshiba Corp.

Co-applicant after: SHINKO ELECTRIC INDUSTRIES Co.,Ltd.

Address before: Tokyo, Japan

Applicant before: MITSUBISHI ELECTRIC Corp.

Co-applicant before: Toshiba Corp.

Co-applicant before: SHINKO ELECTRIC INDUSTRIES Co.,Ltd.

C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: NEC CORP.

Free format text: FORMER OWNER: RENESAS TECHNOLOGY CORP.

Effective date: 20101025

C41 Transfer of patent application or patent right or utility model
C56 Change in the name or address of the patentee

Owner name: RENESAS TECHNOLOGY CORP.

Free format text: FORMER NAME: NEC CORP.

COR Change of bibliographic data

Free format text: CORRECT: ADDRESS; FROM: TOKYO, JAPAN TO: KAWASAKI CITY, KANAGAWA PREFECTURE, JAPAN

CP01 Change in the name or title of a patent holder

Address after: Kawasaki, Kanagawa, Japan

Co-patentee after: Toshiba Corp.

Patentee after: Renesas Electronics Corp.

Co-patentee after: SHINKO ELECTRIC INDUSTRIES Co.,Ltd.

Address before: Kawasaki, Kanagawa, Japan

Co-patentee before: Toshiba Corp.

Patentee before: NEC ELECTRONICS Corp.

Co-patentee before: SHINKO ELECTRIC INDUSTRIES Co.,Ltd.

TR01 Transfer of patent right

Effective date of registration: 20101025

Address after: Kawasaki, Kanagawa, Japan

Co-patentee after: Toshiba Corp.

Patentee after: NEC ELECTRONICS Corp.

Co-patentee after: SHINKO ELECTRIC INDUSTRIES Co.,Ltd.

Address before: Tokyo, Japan

Co-patentee before: Toshiba Corp.

Patentee before: Renesas Technology Corp.

Co-patentee before: SHINKO ELECTRIC INDUSTRIES Co.,Ltd.

CP02 Change in the address of a patent holder

Address after: Tokyo, Japan

Co-patentee after: Toshiba Corp.

Patentee after: Renesas Electronics Corp.

Co-patentee after: SHINKO ELECTRIC INDUSTRIES Co.,Ltd.

Address before: Kawasaki, Kanagawa, Japan

Co-patentee before: Toshiba Corp.

Patentee before: Renesas Electronics Corp.

Co-patentee before: SHINKO ELECTRIC INDUSTRIES Co.,Ltd.

CP01 Change in the name or title of a patent holder
CP01 Change in the name or title of a patent holder

Address after: Tokyo, Japan

Co-patentee after: TOSHIBA MEMORY Corp.

Patentee after: Renesas Electronics Corp.

Co-patentee after: SHINKO ELECTRIC INDUSTRIES Co.,Ltd.

Address before: Tokyo, Japan

Co-patentee before: Japanese businessman Panjaya Co.,Ltd.

Patentee before: Renesas Electronics Corp.

Co-patentee before: SHINKO ELECTRIC INDUSTRIES Co.,Ltd.

TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20191022

Address after: Tokyo, Japan

Co-patentee after: Japanese businessman Panjaya Co.,Ltd.

Patentee after: Renesas Electronics Corp.

Co-patentee after: SHINKO ELECTRIC INDUSTRIES Co.,Ltd.

Address before: Tokyo, Japan

Co-patentee before: TOSHIBA MEMORY Corp.

Patentee before: Renesas Electronics Corp.

Co-patentee before: SHINKO ELECTRIC INDUSTRIES Co.,Ltd.

Effective date of registration: 20191022

Address after: Tokyo, Japan

Co-patentee after: TOSHIBA MEMORY Corp.

Patentee after: Renesas Electronics Corp.

Co-patentee after: SHINKO ELECTRIC INDUSTRIES Co.,Ltd.

Address before: Tokyo, Japan

Co-patentee before: Toshiba Corp.

Patentee before: Renesas Electronics Corp.

Co-patentee before: SHINKO ELECTRIC INDUSTRIES Co.,Ltd.

CP01 Change in the name or title of a patent holder
CP01 Change in the name or title of a patent holder

Address after: Tokyo, Japan

Co-patentee after: Kaixia Co.,Ltd.

Patentee after: Renesas Electronics Corp.

Co-patentee after: SHINKO ELECTRIC INDUSTRIES Co.,Ltd.

Address before: Tokyo, Japan

Co-patentee before: TOSHIBA MEMORY Corp.

Patentee before: Renesas Electronics Corp.

Co-patentee before: Shinko Electric Industries Co.,Ltd.

CX01 Expiry of patent term
CX01 Expiry of patent term

Granted publication date: 20070418