CN1292946A - 相位检测器 - Google Patents

相位检测器 Download PDF

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CN1292946A
CN1292946A CN998038822A CN99803882A CN1292946A CN 1292946 A CN1292946 A CN 1292946A CN 998038822 A CN998038822 A CN 998038822A CN 99803882 A CN99803882 A CN 99803882A CN 1292946 A CN1292946 A CN 1292946A
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signal
phase
reference clock
frequency
clock signal
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CN1116734C (zh
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B·林德奎斯特
M·尼尔松
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Clastres LLC
WIRELESS PLANET LLC
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Telefonaktiebolaget LM Ericsson AB
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D13/00—Circuits for comparing the phase or frequency of two mutually-independent oscillations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D13/00—Circuits for comparing the phase or frequency of two mutually-independent oscillations
    • H03D13/003—Circuits for comparing the phase or frequency of two mutually-independent oscillations in which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means
    • H03D13/004—Circuits for comparing the phase or frequency of two mutually-independent oscillations in which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means the logic means delivering pulses at more than one terminal, e.g. up and down pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H03L7/0895—Details of the current generators
    • H03L7/0896—Details of the current generators the current generators being controlled by differential up-down pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H03L7/0895—Details of the current generators
    • H03L7/0898—Details of the current generators the source or sink current values being variable

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Manipulation Of Pulses (AREA)
  • Noise Elimination (AREA)

Abstract

在此公开一种既在输入脉冲信号的上升沿又在其下降沿触发的相位检测器。这种方法有效地将输入信号频率加倍。当相位检测器被用于锁相环中时,倍频意味着可使用较低的分频比,从而减少由此引入的任何噪音影响。

Description

相位检测器
发明的技术领域
本发明涉及相位检测器电路，尤其是涉及一种可在锁相环中使用的相位检测器。更具体而言，本发明涉及一种在系统时钟的两个沿上触发的相位检测器，从而有效地将参考频率加倍而没有增加电路和噪音。
发明背景
在数字通信系统中，例如在GSM或DCS系统下工作的移动电话通信中，使用连续相位调制(CPM)技术。
锁相环是众所周知的。一种具基准频率的信号提供对相位检测器的输入，相位检测器的输出被滤波并传送到压控振荡器。该压控振荡器的输出就是锁相环的输出，并且还被反馈到分频器。分频器的输出被反馈到相位检测器，该电路起作用使环的输出成为等于基准频率乘以分频器分频比的频率。从而通过利用包含信息的输入信号控制可编程分频器，最好是分数-N分频器，也就是可提供非整数分频比的分频器，实现频率或相位调制。
美国专利No．4，814，726示出这种类型的一个电路。
通常，在这样的电路中，出现在基准信号中的，或者由相位检测器产生的噪音信号被与分频器分频比对应的因数放大。因此，能够增加基准频率由此降低此分频比是有利的。然而，引入，诸如倍频器来增加基准频率和降低噪音影响，需要增加额外电路，并增加电路的规模和电流消耗。
发明概述
依据本发明，通过在信号时钟的两个沿上触发有效地将基准频率加倍。这种方法产生将基准频率加倍的效果，而没有连带增加电路规模和电流消耗，以便减少噪音对电路输出的影响。
依据本发明的一个方面，提供一种在输入基准频率信号的两个沿上触发的相位检测器。
依据本发明的第二方面，提供一种锁相环，包括在输入基准频率信号的两个沿上触发的相位检测器。
依据本发明的第三方面，提供一种分数-N锁相环电路，具有△-∑调制器控制其分频因数，在其中相位检测器在输入基准频率信号的两个沿上触发。
附图简述
图1示出依据本发明的一个方面的一种锁相环电路。
图2示出依据本发明的另一方面的一种相位检测器的方框图。
图3较详细地示出图2中相位检测器电路一个部分的一种可能的
实施方案的电路图。
优选实施方案详述
图1是一种分数-N锁相环电路的方框图，在本例中，如在移动通信设备，例如移动电话的发送电路中所用的那样，一种△-∑调制器被用于控制分频器的分频因数。类似的电路可用于控制这样一种设备的接收电路中的本地振荡器频率。
通常作为惯例，具有参考频率fref的输入基准信号Vref被供给相位检测器4的第一输入2。相位检测器4的输出被在环滤路器6中滤波并传送到压控振荡器(VCO)8，在环路输出10上提供输出信号。VCO 8的输出信号也供给分频器12，在其中被除以分频比N。分频器12的分频输出被供给相位检测器2的第二输入14。
正如众所周知的那样，此反馈环使电路输出10上的输出信号具有等于N·fref的频率。因此，利用一种通常广为人知的可编程分频器12，通过控制分频比N的值可以控制输出频率。
在图1的电路中，对应于要被发送的数据的信息信号被加到数据输入16，然后加到波形发生器18，以便产生具有所希望的调制的信号瞬时频率的信号，该信号被除以基准频率fref，并在此频率fref上被采样。
根据在信道选择输入20上的信号，一种偏置可在相加器22中被加到来自波形发生器18的信号上，这对△-∑调制器24提供输入，然后被用于产生所希望的分频比N，供输入到分频器12。因此，在环路输出10上产生的输出信号被连续地相位调制，对数据输入16上的输入数据信号作出响应，产生供由常规的发送电路放大和发送的信号。
由于锁相环(PLL)，相对于瞬时频率而言，是一种低通滤波器，可被认为是一种用于重建所希望的调制信号的设备。通过选择在锁相环中环滤波器的带宽对于调制信号通过来说是足够的，VCO 8的输出由对应于瞬时频率的信号和对应于△-∑调制器的量化噪音的相位噪音组成。可通过增加过采样因数或者增加由PLL实现的滤波的滚降性能来减少相位噪音。后者不危害PLL的稳定性容限是困难的。通过增加参考频率可以增加过采样因数，但或许不可能改变这个频率，例如，如果该信号也被用作移动站的系统时钟，或者得不到合适的晶体。
利用一种倍频器将系统时钟信号的频率加倍来产生较高的基准频率是可能的，但这将噪音源引入环中，而且增加设备的尺寸和功率消耗。
因此，依据本发明，相位检测器4利用输入时钟信号Vref的两个沿，有效地将基准频率加倍，没有添加使设备的尺寸或功率消耗增加的任何电路。这有效地将过采样率加倍，没有使输出信号中噪音影响有任何增加。
将会认识到，这种类型的相位检测器可用于其他的应用中，例如在任何锁相环中。在这样一种电路中，使用加倍的输入频率将使所需的分频比值减半，因此减少由此引入的任何噪音影响。
图2更详细地示出构成图1所示设备的部件的相位检测器4的结构。相位检测器4具有第一输入端2，接收基准频率信号Vref，第二输入端14，接收分频器电路12的输出，和输出端26，在图1的电路中，提供对环滤波器6的输入信号。正如通常在相位检测器中已知的那样，相位检测器4在输出端26上产生输出，代表出现在它的两个输入2，14上信号之间相位差。
相位检测器4包括三个D型触发器28，30，32，其中每一个具有数据(D)，时钟(C)和复位(R)输入端，和输出(Q)。三个触发器28，30，32中每一个的数据输入(D)，在这种情况下接收“高”或“1”输入。
来自输入端2的基准时钟信号被供给第一触发器28的钟输入，在基准时钟信号的每个上升沿上触发器28被触发，在此设备的输出上产生一个信号。输入基准时钟也被加到一个反相器(NOT)(34)，被反相的基准频率输出由此被加到第二触发器30的时钟输入。因而，该触发器在被反相的基准频率的每个上升沿上，即在对应于基准频率本身的每个下降沿上触发。在此第二触发器30的输出上产生一个信号。来自这两个触发器28，30的输出被加给一个或门36，其输出被加给一个电荷泵装置40的源输入38。
在相位检测器4的第二输入端14上的输入信号被加给第三触发器32的时钟输入，在该信号的每个上升沿上被触发，在该设备输出上产生的信号被加给电荷泵设备40的接收(sink)控制输入42。
与门44接收加给电荷泵电路40上源控制输入38和接收控制输入42的输入信号，当这两个信号都为高时，也就是来自第三触发器32的输出，和来自第一和第二触发器28，30的输出之一都为高时，产生一个输出脉冲。被延时电路46延时以避免死区效应的与门44输出信号被供给所有的三个触发器28，30，32的复位输入端。
这样，在每个时钟周期内电路被触发两次，在基准时钟信号的上升沿上由触发器28触发一次，在基准时钟信号的下降沿的时刻上由触发器30触发一次。因而，事实上，基准时钟的频率已被加倍。
图3是示出电荷泵电路40结构的电路图。来自输入端点38的源控制信号被加给一个NPN晶体管52的基极端，被反相的源控制信号加给输入54，也就是NPN晶体管56的基极端。晶体管52，56的发射极通过一个电流源58连到地。
被通过输入端42提供的接受控制信号连到一个NPN晶体管60的基极端，被反相的接受控制信号加给端点62，也就是NPN晶体管64的基极。晶体管60，64的发射极通过一个电流源66连到地线。
在电流源58，66中的电流设置输出电流脉冲的上升和下降时间。
晶体管52，60的集电极端被通过各自的电阻68，70连到正电源线Vcc，晶体管56，64的集电极端被直接连到正电源Vcc。
控制在电路中流动的电流幅度的输入电压Vin被连到NPN晶体管72，74的基极，这些晶体管的集电极被连到正电源线Vcc，其发射极被分别连到晶体管52，60的集电极节点。输入电压Vin的幅度是常数，但可被改变，以便改变PLL闭环带宽。
这些节点也被连到各个PNP晶体管76，78的基极端，其发射极端被通过各自的电阻80，82连到正电源线Vcc。输入电压Vin的幅度和电阻器80，82的电阻一起设置输出电流脉冲的幅度。晶体管76，78的集电极端点被连到各个NPN晶体管84，86的集电极端点，其基极端被连在一起，其发射极端被通过各自的匹配电阻88，90连到地线，减少噪音对晶体管84，86的影响。NPN晶体管86的集电极和基极端点被连在一起。
这样本电路由两个相等的通过电流镜反射的电流源组成。通过差分输入对38，54和42，62提供的差分输入信号的幅度控制电流源，特别是由此提供的电流脉冲的长度，因而控制通过晶体管84提供的输出电流，和在输出端92上的输出信号。
在此公开了一种在每个输入基准时钟信号周期中被触发两次，从而有效地将基准频率加倍的相位检测器。

Claims (8)

1．一种相位检测器，包括：
一个基准时钟信号输入；
一个比较信号输入；和
用于将比较信号相位与具有两倍于基准时钟信号频率的信号的相位作比较的装置。
2．一种相位检测器，包括：
一个基准时钟信号输入；
一个比较信号输入；
用于将基准时钟信号转换为具有两倍于基准时钟信号频率的倍频基准信号的装置；和
用于将比较信号的相位和倍频基准信号的相位作比较的装置。
3．一种相位检测器，包括：
一个参考钟信号输入；
一个比较信号输入；
根据基准时钟信号的每个正行进或负行进沿产生第一脉冲信号的装置；
根据比较信号的每个脉冲产生第二脉冲信号的装置；和
用于比较第一和第二脉冲相位的装置。
4．如权利要求3中的相位检测器，其中用于产生第一脉冲信号的装置包括：
两个锁存装置，基准时钟信号被加给第一锁存装置，以根据基准时钟信号的每个正行进沿产生一个脉冲，基准时钟信号被加给第二锁存装置，以根据基准时钟信号的每个负行进沿产生一个脉冲；和
组合逻辑装置，用于产生具有与由第一和第二锁存装置产生的每个脉冲对应的脉冲的第一脉冲信号。
5．一种锁相环，包括在任何前述权利要求中要求的相位检测器。
6．一种分数-N分频比锁相环，包括在权利要求1到4中的一项中要求的相位检测器。
7．一种包括分数-N锁相环的便携式无线电通信设备，包括：
一个相位检测器；
一个滤波器；
一个压控振荡器；和一个分数-N分频器；
相位检测器包括：
一个基准时钟信号输入；
一个比较信号输入，从分频器接收一个信号；
根据参考钟信号的每个正行进或负行进的沿产生第一脉冲信号的装置；
根据比较信号的每个脉冲产生第二脉冲信号的装置；和
用于比较第一和第二脉冲的相位的装置。
8．一种在权利要求7中要求的便携式无线电通信设备，包括一个△-∑调制器，用于产生分频器的分频比。
CN99803882A 1998-03-13 1999-03-11 相位检测器 Expired - Fee Related CN1116734C (zh)

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GB9805456.2 1998-03-13
GB9805456A GB2335322B (en) 1998-03-13 1998-03-13 Phase detector

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CN1292946A true CN1292946A (zh) 2001-04-25
CN1116734C CN1116734C (zh) 2003-07-30

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CN103970180A (zh) * 2013-02-06 2014-08-06 辉达公司 固定频率时钟源的时钟频率调制的方法

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US6198355B1 (en) 2001-03-06
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EP1062725A1 (en) 2000-12-27
AR014721A1 (es) 2001-03-28

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