CN1244160C - 半导体器件 - Google Patents

半导体器件 Download PDF

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CN1244160C
CN1244160C CNB031086152A CN03108615A CN1244160C CN 1244160 C CN1244160 C CN 1244160C CN B031086152 A CNB031086152 A CN B031086152A CN 03108615 A CN03108615 A CN 03108615A CN 1244160 C CN1244160 C CN 1244160C
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semiconductor device
base layer
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CN1449058A (zh
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小野升太郎
山口好广
川口雄介
中村和敏
安原纪夫
松下宪一
帆玉信一
中川明夫
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Toshiba Corp
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Abstract

本发明提供一种保持低导通阻抗仍能降低栅漏间容量的半导体器件。本发明的功率MOSFET(1)，具有：在n+型低阻抗半导体衬底(10)上形成的n-型高阻抗外延层(50)；在n-型高阻抗外延层(50)的表面部分选择地形成的p型基极层(14)；在p型基极层(14)的表面部分选择地形成的n+型源极层(16)；在n-型高阻抗外延层(50)的表面部分，在p型基极层(14)之间，选择地形成的具有比n-型高阻抗外延层(50)高的杂质浓度的Njfet层(40)；隔着栅极绝缘膜(22)形成的栅电极(24)；及源电极(20)和漏电极(12)；在该功率MOSFET(1)中，将夹着Njfet层(40)的p型基极层(14)被配置成相互接近，以便从这些基极层(14)控制耗尽。

Description

半导体器件
技术领域
本发明涉及半导体器件，特别涉及具有功率MOSFET(金属氧化物半导体场效应晶体管)结构的半导体器件。
背景技术
近年来，功率MOSFET加入到大电流、高电压的开关电源的领域，在以笔记本电脑为首的移动通信设备等的节能开关领域的需求迅速增长。在这些领域中，功率MOSFET在功率控制电路或锂离子电池的安全电路等中使用较多，因此非常需要可以用电池电压直接驱动的低电压驱动化、低导通阻抗化、及为降低开关损失而使栅漏间容量QGD降低等。
参照图17的概要剖面图，说明有关已有技术的纵型功率MOSFET。并且，下面各图的相同部分都用同一参照图号，并适当省略其说明。
在图17所示的功率MOSFET100中，在n+型低阻抗半导体衬底10下面设有漏电极12，并且在n+型低阻抗半导体衬底10上形成了n-型高阻抗外延层50。在高阻抗外延层50的表面选择形成p型基极层14，在p型基极层14的表面部分选择形成n+型源极层16。另外，在p型基极层14的表面部分，与n+型源极层16邻接来选择形成高浓度p型区域18。在高阻抗外延层50的表面部分，在p型基极层14之间夹着的区域，选择形成n型杂质浓度比高阻抗外延层50高的掺杂Njfet区域90。在Njfet区域90表面、夹着该Njfet区域90的p型基极层14表面和与p型基极层14相邻接的n+型源极层16表面上，使栅极绝缘膜92介于之间来设置栅电极94。另外，在n+型源极层16的表面和高浓度p型区域18的表面，在上述栅电极94的两侧设置源电极20。
具有这种结构的功率MOSFET100，为降低栅漏间容量QGD，需要Njfet区域90易被耗尽。
然而，如果为使Njfet区域90易被耗尽而降低Njfet区域90的杂质浓度，则芯片的导通阻抗增高，结果存在耐压下降的问题。
发明内容
本发明是鉴于上述问题而提出来的，目的在于提供一种半导体器件，维持低导通阻抗不变而使Njfet区域易被耗尽，且能降低栅漏间容量。
根据本发明，提供一种半导体器件，具有：
半导体衬底，其至少表面部分成为第一导电型低阻抗漏极层；漏电极，其与上述低阻抗漏极层连接；第一导电型高阻抗外延层，其在上述低阻抗漏极层之上形成；第二导电型基极层，其在上述高阻抗外延层的表面部分选择地形成；第一导电型源极层，其在上述第二导电型基极层的表面部分选择地形成；第一导电型jfet层，其在上述高阻抗外延层的表面部分夹着上述第二导电型基极层的区域选择地形成，具有比上述高阻抗外延层高的杂质浓度；栅极绝缘膜，其在上述第一导电型jfet层表面的至少一部分、夹着上述第一导电型jfet层的第二导电型基极层的表面、以及与上述第二导电型基极层相邻的上述第一导电型源极层的表面形成；栅电极，其在上述栅极绝缘膜上形成；及源电极，其在上述栅电极的两边，在上述第一导电型源极层与第一导电型源极层邻接的上述第二导电型基极层上配置；在第一导电型jfet层两边的上述第二导电型基极层被配置成相互接近，以便从上述第二导电型基极层控制耗尽；与上述栅电极的长度方向垂直的方向上的上述第一导电型jfet层的宽度L，与相邻的上述栅电极间的宽度基本相等，或者比相邻的上述栅电极间的宽度窄。
附图说明
图1是本发明的半导体器件的第1实施例的概要剖面图。
图2是图1所示半导体器件的Njfet区域宽度L的仿真结果的曲线。
图3是图1所示半导体器件的Njfet区域表面掺杂量的仿真结果曲线。
图4是本发明的半导体器件的第2实施例的概要剖面图。
图5是本发明的半导体器件的第3实施例的概要剖面图。
图6是用于说明图5所示半导体器件的栅漏间容量QGD降低的图。
图7是图5所示半导体器件的栅漏间容量QGD降低的说明用示意图。
图8是示出通过仿真求出图5所示半导体器件LDD区域的杂质浓度的适合范围的曲线图。
图9是图5所示半导体器件栅电极平面形状的例1的俯视图。
图10是图5所示半导体器件栅电极平面形状的例2的俯视图。
图11是沿图10的切断线A-A的概要剖面图。
图12是沿图10的切断线B-B的概要剖面图。
图13是图5所示半导体器件栅电极平面形状的的例3的俯视图。
图14是图5所示半导体器件栅电极平面形状的的例4的俯视图。
图15是本发明的半导体器件的第4实施例的概要剖面图。
图16是本发明的半导体器件的第5实施例的概要剖面图。
图17是已有技术的纵型功率MOSFET例子的概要剖面图。
具体实施方式
以下，就本发明的几种实施例参照图面进行说明。
(1)第1实施例
图1是本发明的半导体器件的第1实施例的概要剖面图。本实施例的半导体器件的特征是Njfet区域40的宽度窄且浓度高。下面，详细说明本实施例的半导体器件的结构。
图1所示的功率MOSFET1是适用了本发明的纵型功率MOSFET，具有n+型低阻抗半导体衬底10、漏电极12、n-型高阻抗外延层50、p型基极层14、n+型源极层16、Njfet区域40、栅电极24、源电极20。
漏电极12设在n+型低阻抗半导体衬底10的一个表面(图1的下表面)，n-型高阻抗外延层50设在n+型低阻抗半导体衬底10的另一个表面(图1的上表面)。p型基极层14是在n-型高阻抗外延层50的表面部分选择形成的，n+型源极层16是在p型基极层14的表面部分选择形成的。在p型基极层14表面部分形成高浓度p型区域18。在n-型高阻抗外延层50的表面部分，在p型基极层14之间夹着的区域选择地形成Njfet区域40。在Njfet区域40的表面、与它相邻的p型基极层14的表面和与p型基极层14相邻接的n+型源极层16表面上，隔着栅极绝缘膜22设置栅电极24。另外，在n+型源极层16的表面和高浓度p型区域18的表面，在上述栅电极24的两侧设置源电极20。
Njfet区域40是本实施例的特征部分，与图17对比可清楚看出，比已有技术的功率MOSFET的Njfet区域90的宽度更窄，其宽度大致与相邻的两个栅电极24的间隔相同或更窄。通过形成具有如上所述窄的宽度L的Njfet区域40，可得到如下构造，即在Njfet区域40耗尽时，由栅电极24对栅漏间容量QGD的贡献减少，由邻接的p型基极层14控制耗尽。Njfet区域40的宽度L通过仿真已判明，当p型基极层14的深度为Xj＝1.0μm时，L≤1.0μm。
图2是示出Njfet区域40的宽度L的仿真结果的曲线图。如图所示，可以清楚当栅极绝缘膜22的膜厚大致形成为30nm时，在L≤1.0μm的区域，RONQGD大致为小于等于24〔mΩnC〕的值，特别是在Xj×0.7或以下的区域，RONQGD及耐压BV都有明显的效果。
返回图1，Njfet区域40的深度Xjfet基本上与p型基极层14的深度Xj相同，另外，与p型基极层14的接合界面如下形成，即，随着接近Njfet区域40的表面，相对该表面垂直。
另外，通过如上所述使Njfet区域40的宽度L变窄，其表面能在约1E16～约3E17〔cm-3〕的范围高浓度化，因此可以降低导通阻抗RON。
图3是示出Njfet区域40的表面掺杂量的仿真结果的曲线图。如图所示，根据仿真结果可以清楚，当Njfet区域40的宽度L＝1μm时，当Njfet区域40的表面掺杂量N≤4E×12时，可得到不小于30V的耐压BV，RONQGD的值也低。
(2)第2实施例
图4是本发明的半导体器件的第2实施例的概要剖面图。与图1进行比较可以看出，本实施例的功率MOSFET3的特征不仅在于Njfet区域40窄且杂质浓度高，而且还在于使与Njfet区域40相对的区域变厚来形成栅极绝缘膜23。更具体地说，是在栅极绝缘膜23中，与Njfet区域40相对的区域23a大致具有90nm的厚度，其他区域大致具有30nm的厚度。因此，可以在与Njfet区域40相对的区域，使栅电极25与Njfet区域40隔离。
由于Njfet区域40窄且杂质浓度高，在Njfet区域40耗尽时，由p型基极层14控制耗尽，所以，可以采用这样构造的栅极绝缘膜23和栅电极25。
根据本实施例的功率MOSFET3，在与Njfet区域40相对的区域，隔着形成得比其他区域厚的栅极绝缘膜23设有栅电极25，所以可进一步降低由栅电极对栅漏间容量QGD的影响。
(3)第3实施例
图5是本发明的半导体器件的第3实施例的概要剖面图。与图1对比非常明显，本实施例的功率MOSFET5的特征是在栅电极28中将与Njfet区域40相对的部分选择性去除。
如上所述，通过采用分割栅电极28的构造，Njfet区域40的宽度L可以更加变窄，因此栅漏间容量QGD更加降低，从而器件的动作速度也就变得更快。另外，通过将被分割构造的栅电极28作为掩膜来掺入n型杂质，可自对准产生Njfet区域40。
图6及图7是用于说明本实施例中栅漏间容量QGD降低的图。图6显示的是图17所示的已有功率MOSFET100的电子密度，图7显示的是Njfet区域宽度没有变窄而只是分割了图17的功率MOSFET100的栅电极时的电子密度。图6及图7都是施加20V的Vds时的电子密度。
两图相比可以看出，仅分割已有功率MOSFET100的栅电极94，相邻p型基极14之间的区域大，所以栅极引起的耗尽比例大。其结果，栅极引起的耗尽消失，从而耐压降低。
返回图5，本实施例的功率MOSFET5还具有在Njfet区域40的表面部分形成的LDD(低掺杂漏极：Lightly Doped Drain)区域44。该LDD区域44如下形成，即以被分割的栅电极28作为掩膜，在Njfet区域40中浅浅地注入n型杂质离子后进行热扩散而自对准形成的。
图8是通过仿真求出的功率MOSFET5的LDD区域44的杂质浓度的适当范围的曲线图。如图所示，当Xj＝0.8μm、L＝0.4μm时，如果LDD区域44的杂质浓度Cs以5E17〔cm-3〕上限，则RONQGD的值可不大于10〔mΩnC〕。
有关本实施例的功率MOSFET5具有的栅电极的平面形状，参照图9至图14进行说明。
图9所示是栅电极28’平面形状的例1。本例的栅电极28’被分割成了两个，但与已有的功率MOSFET一样形成的是条纹形状。通过这样的电极形状，栅电极本身的阻抗变大，存在影响器件高速化的缺点。
首先，关于功率MOSFET5的Njfet区域40，不是在n-型高阻抗外延层50的表面部分沿栅电极28的长度方向形成条纹形状，而例如是像分别成矩形的平面形状那样沿长度方向周期配置，形成为各矩形区域被p型基极层14包围，然后，如图10的例2所示，将被分割的栅电极形成为在下层不存在Njfet区域40的区域周期地相互连接、且具有像梯子那样的平面形状。这样一来，由于以像围绕被周期性配置的Njfet区域40那样的平面形状来设置栅电极28，所以栅电极的阻抗也可大幅降低。还有，Njfet区域40的耗尽在图9所示的例中虽然只是沿纸面的横方向扩展，但通过周期地配置Njfet区域40，可以在全方位扩展。因此器件的动作速度更快。沿图10的切断线A-A的概要剖面图如图11所示，沿图10的切断线B-B的概要剖面图如图12所示。
图10所示的例子，被p型基极层14围住的Njfet区域40的形状为矩形，但Njfet区域40的形状不限于此，例如也可以像图13所示的例3那样为圆形，也可以像图14所示的例4那样为的多角形。
(4)第4实施例
图15是本发明的半导体器件的第4实施例的概要剖面图。如图所示功率MOSFET7的特征是还具有绝缘膜52和固定电位电极54这点，所述绝缘膜52在Njfet区域46内大致中央位置、以与p型基极层14的扩散深度大致相同的深度设置的沟道TR内设置，所述固定电位电极54设置在该绝缘层52内。
如上所述，通过在被p型基极层14夹着(或包围)的Njfet区域46内设置绝缘层52，可对晶片表面从斜方向进行离子注入。这样，就可以形成高浓度、宽度L窄的Njfet区域46。另外，通过在沟道TR内使绝缘层52介于中间来设置电极54，可使耐压只再上升5V，并且栅漏间容量QGD还能再降低20％左右。
(5)第5实施例
图16是本发明的半导体器件的第5实施例的概要剖面图。如图所示的功率MOSFET9是将上述第3实施例应用于横型功率MOSFET。也就是说，在p型基极层14的外侧区域，从n-型高阻抗外延层50的表面贯穿它而与它正下方的n+型低阻抗半导体层10接合从而形成n+型低阻抗漏极层68，在该n+型低阻抗漏极层68的表面设置漏极62，这样就构成了纵型功率MOSFET。以下几点实质上都与图5所示的功率MOSFET5相同，即，被p型基极层14夹着(或包围)的Njfet区域40形成为窄的宽度L、Njfet区域40形成为高浓度、栅电极28被分割设置、以及在Njfet区域40的表面部分形成LDD区域44。
以上，说明了本发明的几种实施例，本发明并不是局限于上述方使，也可在本技术范围内进行各种改变来进行应用。
发明的效果
根据以上的详细说明，如果采用本发明，则保持低的导通阻抗就能降低栅漏间容量，所以提供一种大致从10V系列的低耐压到大致100V系列的耐压为止，利用同样的设计就能高性能化的半导体器件。

Claims (15)

1.一种半导体器件，其特征在于，具有：
半导体衬底，其至少表面部分成为第一导电型低阻抗漏极层；
漏电极，其与上述低阻抗漏极层连接；
第一导电型高阻抗外延层，其在上述低阻抗漏极层之上形成；
第二导电型基极层，其在上述高阻抗外延层的表面部分选择地形成；
第一导电型源极层，其在上述第二导电型基极层的表面部分选择地形成；
第一导电型jfet层，其在上述高阻抗外延层的表面部分由上述第二导电型基极层夹着的区域选择地形成，具有比上述高阻抗外延层高的杂质浓度；
栅极绝缘膜，其在上述第一导电型jfet层表面的至少一部分、夹着上述第一导电型jfet层相邻的上述第二导电型基极层的表面、以及与上述第二导电型基极层的表面相邻的上述第一导电型源极层的表面形成；
栅电极，其在上述栅极绝缘膜上形成；及
源电极，其在上述栅电极的两边，在上述第一导电型源极层和与第一导电型源极层邻接的上述第二导电型基极层上配置；
在上述第一导电型jfet层两边的上述第二导电型基极层被配置成相互接近，以便从上述第二导电型基极层控制耗尽；
与上述栅电极的长度方向垂直的方向上的上述第一导电型jfet层的宽度L，与相邻的上述栅电极间的宽度基本相等，或者比相邻的上述栅电极间的宽度窄。
2.如权利要求1所述的半导体器件，其特征在于：上述第二导电型基极层的深度Xj与上述第一导电型jfet层的宽度L，满足下式L≤Xj×0.7。
3.如权利要求1所述的半导体器件，其特征在于：上述第一导电型jfet层的深度与上述第二导电型基极层的深度基本相同。
4.如权利要求1所述的半导体器件，其特征在于：上述第二导电型基极层与上述第一导电型jfet层的结合界面，随着与表面接近而相对表面垂直。
5.如权利要求1所述的半导体器件，其特征在于：上述栅极绝缘膜中与上述第一导电型jfet层相对的区域被形成为比其他区域厚。
6.如权利要求1所述的半导体器件，其特征在于：上述栅极绝缘膜和上述栅电极是选择性除去与上述第一导电型jfet层相对的区域的一部分而形成的。
7.如权利要求6所述的半导体器件，其特征在于：上述第一导电型jfet层是以上述栅电极为掩膜通过自对准而形成的。
8.如权利要求6所述的半导体器件，其特征在于：还具有第一导电型LDD层，其形成在上述第一导电型jfet层的表面部分，杂质浓度比上述高阻抗外延层的杂质浓度高、比上述第一导电型jfet层低。
9.如权利要求8所述的半导体器件，其特征在于：上述第一导电型LDD层是以上述栅电极为掩膜通过自对准而形成的。
10.如权利要求6所述的半导体器件，其特征在于：上述第一导电型jfet层的表面最高浓度，不大于5E17cm-3。
11.如权利要求6至10任一项所述的半导体器件，其特征在于：
上述第一导电型jfet层分别具有矩形的平面形状，沿上述栅电极的长度方向被周期地配置；
上述第二导电型基极层形成为包围上述各第一导电型jfet层。
12.如权利要求6至10任一项所述的半导体器件，其特征在于：
上述第一导电型jfet层分别具有圆形的平面形状，沿上述栅电极的长度方向被周期地配置；
上述第二导电型基极层形成为包围上述各第一导电型jfet层。
13.如权利要求6至10任一项所述的半导体器件，其特征在于：
上述第一导电型jfet层分别具有多角形平面形状，沿上述栅电极的长度方向被周期地配置；
上述第二导电型基极层形成为包围上述各第一导电型jfet层。
14.如权利要求6至10任一项所述的半导体器件，其特征在于：还具有在上述第一导电型jfet层内形成的绝缘层。
15.如权利要求14所述的半导体器件，其特征在于：还具有设置在上述绝缘层内、形成为被上述绝缘层覆盖、电位固定的电极。
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