WO2015096605A1 - 分裂栅功率半导体场效应晶体管 - Google Patents

分裂栅功率半导体场效应晶体管 Download PDF

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WO2015096605A1
WO2015096605A1 PCT/CN2014/093007 CN2014093007W WO2015096605A1 WO 2015096605 A1 WO2015096605 A1 WO 2015096605A1 CN 2014093007 W CN2014093007 W CN 2014093007W WO 2015096605 A1 WO2015096605 A1 WO 2015096605A1
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gate
split gate
conductivity type
heavily doped
forming
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PCT/CN2014/093007
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English (en)
French (fr)
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梁嘉进
伍震威
单建安
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梁嘉进
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Priority to EP14875355.1A priority Critical patent/EP3089216B1/en
Priority to US14/766,594 priority patent/US9397178B2/en
Priority to CN201480002400.4A priority patent/CN104737298B/zh
Publication of WO2015096605A1 publication Critical patent/WO2015096605A1/zh
Priority to US15/188,694 priority patent/US9825149B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/405—Resistive arrangements, e.g. resistive or semi-insulating field plates
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors

Definitions

  • the present invention relates generally to the construction and fabrication of power semiconductor devices, and in particular to split gate planar power semiconductor field effect transistors (FETs).
  • FETs field effect transistors
  • the heavily doped n-type region is labeled as n + and the heavily doped P-type region is labeled as p + .
  • These heavily doped regions typically have a doping concentration between 1 x 10 18 cm -3 and 1 x 10 21 cm -3 .
  • the lightly doped n-type region is labeled n - and the lightly doped P-type region is labeled p - .
  • These lightly doped regions typically have a doping concentration between 1 x 10 13 cm -3 and 1 x 10 17 cm -3 .
  • Power MOSFETs have been widely used in switching applications. High switching speeds are required in order to reduce switching power losses and reduce the size of passive components in the system. Accordingly, it is an object of the present invention to provide a split gate power MOSFET having a high switching speed.
  • Another object of the present invention is to provide a split gate IGBT having a high switching speed.
  • FIG. 1 A cross section of a prior art power MOSFET structure is shown in FIG.
  • the high voltage can be blocked between the drain and source of the device by a reverse biased p-type body region (13) / n - - epitaxial (14) junction.
  • current can be conducted between the n + source (11) and the n - - epitaxial (14) through the n-type channel.
  • the n - - epitaxial (14) under the gate (21) is charged or discharged through the gate capacitance. Therefore, the switching speed of the device is largely dependent on the overlap region of the gate (21)-n - - epitaxial (14).
  • the overlap region can be reduced by reducing the distance between two adjacent p-type body regions (13).
  • the adjacent p-type body regions (13) are too close to each other, high resistance is induced in the upper portion of the n - - epitaxial (14) between the two adjacent p-type body regions (13), and High on-resistance of undesired devices.
  • FIG. 1 Another prior art power MOSFET structure [1] is shown in FIG.
  • the split gate structure of the device produces a much smaller gate (21)-n -- epitaxial (14) overlap region and thus a higher switching speed than the device previously shown in FIG.
  • the space between adjacent p-type body regions (13) is not reduced to maintain substantially the same on-resistance.
  • the split gate will create a high electric field at the edge of the overlap region of the gate (21)-n - epitaxial (14), and the high electric field can cause early breakdown of the device [2].
  • FIG. 2 Yet another prior art power MOSFET structure [2] is shown in FIG.
  • the device has the same phase as the device previously shown in Figure 2.
  • the same split gate structure The device has an additional dummy gate (22) connected to the source electrode (22).
  • the dummy gate (22) has the function of a field plate, which can reduce the electric field at the edge of the gate electrode (21) in the off state. Therefore, the problem of early breakdown is solved.
  • an advanced photolithography step is required to create a small gap between the dummy gate (22) and the split gate (21).
  • the dummy gate (22) also creates additional capacitance at the sidewalls of the split gate (21), which can cause degradation of the switching speed as compared to the switching speed of the device shown in FIG.
  • the present invention provides a planar power MOSFET structure including a split gate (21) and a semi-insulating field plate (34) as shown in FIG.
  • a semi-insulating field plate (34) is connected to the source electrode (22) at the sidewall. Due to the high resistivity of the semi-insulating field plate (34), the RC delay time of the board (34) is greater than an order of magnitude greater than the typical switching time of the device. For example, current state-of-the-art power MOSFETs have a switching time of approximately 10 -8 s, while plates (34) typically have an RC delay time of approximately 10 -5 s.
  • the semi-insulating field plate (34) is difficult to conduct any transient current during switching, so even if there is a large overlap between the semi-insulating field plate (34) and the gate (21), it will not cause a switch. delay.
  • the potential of the semi-insulating field plate (34) remains the same as that of the source electrode (22). Therefore, similar to the dummy gate (22), the semi-insulating field plate can also suppress a high electric field in the vicinity of the gate electrode (21) and thus prevent early breakdown.
  • the present invention also provides an insulated gate bipolar transistor (IGBT) including a split gate (21) and a semi-insulating field plate (34) as shown in FIG. Similar to in a power MOSFET, the split gate (21) provides a high switching speed and the semi-insulating field plate (34) prevents premature breakdown.
  • IGBT insulated gate bipolar transistor
  • a split gate planar power MOSFET structure including
  • a lightly doped epitaxial layer (14) of a first conductivity type the lightly doped epitaxial layer being on top of the heavily doped substrate (15),
  • a body region (13) of a second conductivity type being connected to the source electrode (22) by the heavily doped diffusion (12),
  • a heavily doped source (11) of a first conductivity type the heavily doped source (11) being contacted by the source electrode (22),
  • a gate dielectric (31) covering a surface of the body region (13) and forming between the heavily doped source (11) and the lightly doped epitaxial layer (14) Channel,
  • a semi-insulating field plate (34) on the top of the thin dielectric layer (33) and in contact with the source electrode (22) at the sidewall,
  • ILD interlayer dielectric
  • the gate dielectric (31) is silicon oxide.
  • split gate electrode (21) is at least one of polysilicon, metal or metal silicide.
  • the thin dielectric layer (33) is silicon oxide.
  • the semi-insulating field plate (34) comprises titanium nitride, polysilicon, and amorphous silicon.
  • the ILD (32) is silicon oxide.
  • drain electrode (23) and the source electrode (22) are metal or metal silicide.
  • a split gate planar IGBT structure including
  • lightly doped drift region (14) of a first conductivity type said lightly doped drift region (14) being on top of said buffer region (16)
  • a heavily doped emitter region (11) of a first conductivity type the heavily doped emitter region (11) being contacted by the emitter (24),
  • a gate dielectric (31) covering a surface of the body region (13) and forming a trench between the heavily doped emitter region (11) and the lightly doped drift region (14) Road,
  • a semi-insulating field plate (34) that is in contact with the emitter (24) on top of the thin dielectric layer (33) and at the sidewalls,
  • ILD interlayer dielectric
  • collector (25) and the emitter (24) are both metal or metal silicide.
  • the gate dielectric (31) is silicon oxide.
  • split gate electrode (21) is at least one of polysilicon, metal or metal silicide.
  • the thin dielectric layer (33) is silicon oxide.
  • the semi-insulating field plate (34) comprises titanium nitride, polysilicon, and amorphous silicon.
  • the ILD (32) is silicon oxide.
  • a method of fabricating a split gate planar power MOSFET structure including
  • a first conductivity type heavily doped source (11) by ion implantation and annealing, depositing a thin dielectric layer (33), a semi-insulating field plate (34), and an ILD (32),
  • a source electrode (22) is formed at the bottom and at the surface of the drain electrode (23).
  • split gate (21) is patterned by photolithography and etching.
  • ion implantation is optionally performed after etching the split gate (21) to increase the doping concentration of the upper portion of the n - - epitaxial (14).
  • the ILD (32), the semi-insulating field plate (34), and the thin dielectric layer (33) are simultaneously patterned by photolithography and etching.
  • a manufacturing method for a split gate planar IGBT structure including
  • a first conductive type heavily doped emitter region (11) by implantation and annealing, depositing a thin dielectric layer (33), a semi-insulating field plate (34), and an ILD (32),
  • split gate (21) is patterned by photolithography and etching.
  • ion implantation is optionally performed after etching the split gate (21) to increase the doping concentration of the upper portion of the n - - epitaxial (14).
  • the ILD (32), the semi-insulating field plate (34), and the thin dielectric layer (33) are simultaneously patterned by photolithography and etching.
  • FIG. 1 is a cross-sectional view of a prior art power MOSFET structure.
  • FIG. 2 is a cross-sectional view of another prior art power MOSFET structure.
  • FIG. 3 is a cross-sectional view of still another prior art power MOSFET structure.
  • FIG. 4 is a cross-sectional view of the present invention implemented in a power MOSFET.
  • Fig. 5 is a cross-sectional view of the present invention implemented in an IGBT.
  • 6A-6H illustrate key manufacturing process steps of the power MOSFET previously shown in FIG.
  • FIG. 7A through 7H illustrate key manufacturing process steps of the IGBT previously shown in FIG.
  • FIG. 1 is a cross-sectional view of a prior art power MOSFET structure.
  • FIG. 2 is a cross-sectional view of another prior art power MOSFET structure.
  • the device has a split gate (21) and a gate dielectric (31) under the gate (21). Only a small portion of the surface of the n - epitaxial (14) is covered by the gate dielectric (31), while the remaining surface is covered by an interlayer dielectric (ILD) (32).
  • ILD interlayer dielectric
  • FIG. 3 is a cross-sectional view of still another prior art power MOSFET structure.
  • the device has a split gate (21) and a dummy gate (22) between the split gates (21).
  • the dummy gate (22) is connected to the source electrode (22), and the dummy gate (22) is isolated from the split gate (21) by the ILD (32).
  • the planar power MOSFET structure includes a drain electrode (23) at the bottom; an n + substrate (15); n - - epitaxy (14) on top of the n + substrate (15); p + diffusion (12)
  • the p + diffusion is contacted by the source electrode (22); the p-type body region (13) is connected to the source electrode (22) by p + diffusion (12); n + source ( 11), the n + source is contacted by the source electrode (22); a gate dielectric (31), the gate dielectric covering the surface of the p-type body region (13) and at the n + source (11) and n - Forming a channel between the epitaxy (14); a split gate electrode (21) on top of the gate dielectric (31); a thin dielectric layer (33) covering the split gate (21) and n - - Both surfaces of the epitaxy (14); a semi-insulating field plate (34) on the top of the thin dielectric layer
  • the source electrode (22) and the drain electrode (23) are typically metal or metal silicide.
  • the gate dielectric (31) is typically silicon oxide, but other high dielectric constant materials (e.g., aluminum oxide, oxynitride, and hafnium oxide) can also be used as the gate dielectric (31).
  • the gate electrode (21) of the device is typically polysilicon because it is suitable for self-aligned high temperature processes. However, metal or metal silicide can also be used as the gate electrode (21) for the purpose of minimizing gate resistance.
  • the thin dielectric layer (33) is typically silicon oxide, but other dielectric materials can also be used for isolation purposes. ILD (32) is also used for isolation, and typically ILD (32) is silicon oxide.
  • the semi-insulating field plate (34) can be any high resistivity material including, but not limited to, titanium nitride, polysilicon, and amorphous silicon.
  • Fig. 5 is a cross-sectional view of the present invention implemented in an IGBT.
  • the structure of the IGBT is similar to that of the power MOSFET previously shown in FIG.
  • the emitter (24) instead of the source electrode (22) is located at the surface, and the collector (25) instead of the drain electrode (23) is located at the bottom.
  • the collector (25) instead of the drain electrode (23) is located at the bottom.
  • the manufacturing process includes (1) forming n - - epitaxy (14) on top of the n + substrate (15) by epitaxial growth; (2) forming p + diffusion (12) by implantation and main diffusion; (3) forming a gate a dielectric (31) for forming a gate electrode (21) by deposition, patterning both the gate dielectric (31) and the gate electrode (21); (4) forming a p-type body region by self-aligned implantation and main diffusion (13) (5) forming a split gate (21) by patterning the gate electrode (21) and the gate dielectric (31); (6) forming an n + source (11) by implantation and annealing, depositing a thin dielectric layer (33), a semi-insulating field plate (34) and an ILD (32); (7) a patterned ILD (32), a semi-insulating field plate (34), and a thin dielectric layer (33) to form contact holes (41); and (8) A source electrode (2
  • the split gate (21) is formed by photolithography and subsequent etching. Usually such lithography requires an additional mask. Further, after forming the split gate (21), the ion implantation step may optionally be added before the formation of the n + source (11) to increase the doping concentration of the upper portion of the n ⁇ - epitaxial (14), and thus Reduced on-resistance.
  • the ILD (32), the semi-insulating field plate (34), and the thin dielectric layer (33) can be patterned together by photolithography using a mask for the contact holes (41) and subsequent etching.
  • FIG. 7A through 7H illustrate key manufacturing process steps of the IGBT previously shown in FIG.
  • the manufacturing steps are similar to the manufacturing steps illustrated in Figures 6A-6H.
  • the process to a lightly doped n - substrate wafer (14) instead of n-- - epitaxial (14) starts.
  • the process is the same as that of the power MOSFET until the emitter (24) electrode is formed at the surface, as shown in Figure 7G.
  • the n - substrate wafer (14) is tapered, and the n-buffer (16) is formed by ion implantation and annealing at the back side.
  • the p + collector region (17) is then formed by ion implantation at the back side and annealing.
  • the collector (25) is formed at the back side of the wafer as shown in Figure 7H.

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Abstract

本发明大体上涉及功率场效应晶体管(FET)的结构和制造。本发明提供平面功率金属氧化物半导体场效应晶体管(MOSFET)以及包括分裂栅和半绝缘场板的绝缘栅双极晶体管(IGBT)结构。本发明还提供这些结构的制造方法。

Description

分裂栅功率半导体场效应晶体管 技术领域
本发明大体上涉及功率半导体装置的结构和制造，且具体而言涉及分裂栅平面功率半导体场效应晶体管(FET)。
背景技术
本发明将在n沟道功率FET中说明，但是在以下说明中将理解，本发明同样适用于p沟道功率FET。在本发明说明书中，重掺杂的n型区域标记为n+，并且重掺杂的P型区域标记为p+。这些重掺杂区域通常具有介于1×1018cm-3与1×1021cm-3之间的掺杂浓度。在本发明说明书中，轻掺杂的n型区域标记为n-，并且轻掺杂的P型区域标记为p-。这些轻掺杂区域通常具有介于1×1013cm-3与1×1017cm-3之间的掺杂浓度。
功率MOSFET已广泛用于开关应用中。需要高开关速度以便减少开关功率损耗并且减小系统中的无源部件的尺寸。因此，本发明的目标是提供具有高开关速度的分裂栅功率MOSFET。
此外，在IGBT结构中也需要高开关速度。因此，本发明的另一目标是提供具有高开关速度的分裂栅IGBT。
现有技术
图1中示出现有技术功率MOSFET结构的横截面。如图所示，在断开状态下，高压可以由反向偏压的p型体区(13)/n--外延(14)结阻挡在装置的漏极与源极之间。在通路状态下，电流可以通过n型沟道在n+源极(11)与n--外延(14)之间传导。在装置的开关期间，栅(21)下方的n--外延(14)通过栅电容充电或放电。因此，装置的开关速度大部分取决于栅(21)-n--外延(14)重叠区域。为了增强开关速度，重叠区域可以通过减小两个邻近p型体区(13)之间的距离而减小。然而，如果邻近p型体区(13)彼此太靠近，那么会在位于两个邻近p型体区(13)之间的n--外延(14)的上部部分中引起高电阻，并且会引发不合需要的装置的高导通电阻。
图2中示出另一现有技术功率MOSFET结构[1]。如图中所示，装置的分裂栅结构会产生小得多的栅(21)-n--外延(14)重叠区域以及因此与先前图1中示出的装置相比更高的开关速度。同时，邻近p型体区(13)之间的空间未减小以维持大致相同的导通电阻。然而，在断开状态下，分裂栅会在栅(21)-n--外延(14)重叠区域的边缘处产生高电场，并且高电场可以引起装置的提前击穿[2]。
图3中示出又另一现有技术功率MOSFET结构[2]。装置具有与先前图2中示出的装置相 同的分裂栅结构。装置具有连接到源极电极(22)上的额外虚拟栅(22)。虚拟栅(22)具有场板的功能，这可以在断开状态下减小在栅电极(21)的边缘处的电场。因此，解决了提前击穿的问题。然而，需要先进的光刻步骤以在虚拟栅(22)与分裂栅(21)之间形成小的间隙。此外，虚拟栅(22)还在分裂栅(21)的侧壁处产生额外电容，与图2中示出的装置的开关速度相比，这会引起开关速度的退化。
发明内容
因此，本发明的目标是提供具有高开关速度，但不存在提前击穿问题的分裂栅平面功率FET。
为了实现此目标以及其他目标，本发明提供包括如图4中所示的分裂栅(21)以及半绝缘场板(34)的平面功率MOSFET结构。半绝缘场板(34)在侧壁处连接到源极电极(22)。由于半绝缘场板(34)的高电阻率，因此板(34)的RC延迟时间大于装置的典型开关时间一个数量级以上。例如，目前先进技术功率MOSFET的开关时间约为10-8s，而板(34)的RC延迟时间通常约为10-5s。由于这种差异，因此半绝缘场板(34)在开关期间难以传导任何瞬变电流，因此即使在半绝缘场板(34)与栅(21)之间存在大的重叠区域也不会引起开关延迟。另一方面，在装置的断开状态下，因为在半绝缘场板(34)中不存在静态电流，半绝缘场板(34)的电势保持为与源极电极(22)的电势相同。因此，类似于虚拟栅(22)，半绝缘场板还可以抑制栅电极(21)附近的高电场并且因此防止提前击穿。
为了实现此目标以及其他目标，本发明还提供包括如图5中所示的分裂栅(21)以及半绝缘场板(34)的绝缘栅双极晶体管(IGBT)。类似于在功率MOSFET中，分裂栅(21)提供高开关速度，并且半绝缘场板(34)防止提前击穿。
一种分裂栅平面功率MOSFET结构，其包括
在底部处的漏极电极(23)，
第一导电型的重掺杂衬底(15)，
第一导电型的轻掺杂外延层(14)，所述轻掺杂外延层在所述重掺杂衬底(15)的顶部上，
第二导电型的重掺杂扩散(12)，所述重掺杂扩散(12)由源极电极(22)接触，
第二导电型的体区(13)，所述的体区(13)通过所述重掺杂扩散(12)连接到所述源极电极(22)，
第一导电型的重掺杂源极(11)，所述重掺杂源极(11)由所述源极电极(22)接触，
栅电介质(31)，所述的栅电介质(31)覆盖所述体区(13)的表面并且在所述重掺杂源极(11)与所述轻掺杂外延层(14)之间形成沟道，
分裂栅电极(21)，所述分裂栅电极(21)在所述栅电介质(31)的顶部上，
薄电介质层(33)，所述薄电介质层(33)覆盖所述分裂栅(21)以及所述轻掺杂外延层(14)的所述两者表面，
半绝缘场板(34)，所述半绝缘场板(34)在所述薄电介质层(33)的顶部上并且在侧壁处由所述源极电极(22)接触，
层间电介质(ILD)(32)，所述层间电介质(32)在所述半绝缘场板(34)的顶部上，
以及源极电极(22)，所述源极电极在接触孔(41)中并且在所述ILD(32)的顶部上。
进一步的，其中所述栅电介质(31)是氧化硅。
进一步的，其中所述分裂栅电极(21)是多晶硅、金属或金属硅化物中的至少一种。
进一步的，其中所述薄电介质层(33)是氧化硅。
进一步的，其中所述半绝缘场板(34)包含氮化钛、多晶硅以及非晶硅。
进一步的，其中所述ILD(32)是氧化硅。
进一步的，其中所述漏极电极(23)以及所述源极电极(22)两者是金属或金属硅化物。
一种分裂栅平面IGBT结构，其包括
在底部处的集电极(23)，
第二导电型的重掺杂集电区(17)，
第一导电型的缓冲区(16)，所述的缓冲区(16)在所述集电区(17)的顶部上，
第一导电型的轻掺杂漂移区(14)，所述的轻掺杂漂移区(14)在所述缓冲区(16)的顶部上，
第二导电型的重掺杂扩散(12)，所述重掺杂扩散(12)由发射极(24)接触，
第二导电型的体区(13)，所述的体区(13)通过所述重掺杂扩散(12)连接到所述发射极(22)，
第一导电型的重掺杂发射区(11)，所述重掺杂发射区(11)由所述发射极(24)接触，
栅电介质(31)，所述栅电介质(31)覆盖所述体区(13)的表面并且在所述重掺杂发射区(11)与所述轻掺杂漂移区(14)之间形成沟道，
分裂栅电极(21)，所述分裂栅电极在所述栅电介质(31)的顶部上，
薄电介质层(33)，所述薄电介质层覆盖所述分裂栅(21)以及所述轻掺杂外延层(14)的所述表面两者，
半绝缘场板(34)，所述半绝缘场板(34)在所述薄电介质层(33)的顶部上并且在侧壁处由所述发射极(24)接触，
层间电介质(ILD)(32)，所述层间电介质在所述半绝缘场板(34)的顶部上，
以及发射极(24)，所述发射极在接触孔(41)中并且在所述ILD(32)的顶部上。
进一步的，其中所述集电极(25)以及所述发射极(24)两者是金属或金属硅化物。
进一步的，其中所述栅电介质(31)是氧化硅。
进一步的，其中所述分裂栅电极(21)是多晶硅、金属或金属硅化物中的至少一种。
进一步的，其中所述薄电介质层(33)是氧化硅。
进一步的，其中所述半绝缘场板(34)包含氮化钛、多晶硅以及非晶硅。
进一步的，其中所述ILD(32)是氧化硅。
一种用于分裂栅平面功率MOSFET结构的制造方法，其包括
(1)通过外延生长在第一导电型的重掺杂衬底(15)的顶部上形成第一导电型的轻掺杂外延层(14)，
(2)通过离子注入以及热扩散形成第二导电型的重掺杂扩散(12)，
(3)形成栅电介质(31)，通过淀积形成栅电极(21)，图案化所述栅电介质(31)以及所述栅电极(21)，
(4)通过自对准离子注入以及热扩散形成第二导电型的体区(13)，
(5)通过图案化所述栅电极(21)以及所述栅电介质(31)形成分裂栅(21)，
(6)通过离子注入以及退火形成第一导电型的重掺杂源极(11)，淀积薄电介质层(33)、半绝缘场板(34)以及ILD(32)，
(7)图案化所述ILD(32)、所述半绝缘场板(34)以及所述薄电介质层(33)以形成接触孔(41)以及
(8)在底部在表面以及漏极电极(23)处形成源极电极(22)。
进一步的，其中所述分裂栅(21)通过光刻以及蚀刻进行图案化。
进一步的，其中离子注入任选地在蚀刻所述分裂栅(21)之后执行，以增加n--外延(14)的上部部分的掺杂浓度。
进一步的，其中所述ILD(32)、所述半绝缘场板(34)以及所述薄电介质层(33)同时通过光刻以及蚀刻进行图案化。
一种用于分裂栅平面IGBT结构的制造方法，其包括
(1)以第一导电型的轻掺杂的衬底晶片(14)开始，
(2)通过离子注入以及热扩散形成第二导电型的重掺杂扩散(12)，
(3)形成栅电介质(31)，通过淀积形成栅电极(21)，图案化所述栅电介质(31)以及所述栅电极(21)，
(4)通过自对准离子注入以及热扩散形成第二导电型的体区(13)，
(5)通过图案化所述栅电极(21)以及所述栅电介质(31)形成分裂栅(21)，
(6)通过注入以及退火形成第一导电型的重掺杂发射区(11)，淀积薄电介质层(33)、半绝缘场板(34)以及ILD(32)，
(7)图案化所述ILD(32)、所述半绝缘场板(34)以及所述薄电介质层(33)以形成接触孔(41)，并且在表面处形成发射极(24)以及
(8)使所述衬底晶片(14)变薄，通过离子注入以及退火形成第一导电型的缓冲层(16)，通过离子注入以及退火形成重掺杂集电区(17)，在底部处形成集电极(25)。
进一步的，其中所述分裂栅(21)通过光刻以及蚀刻进行图案化。
进一步的，其中离子注入任选地在蚀刻所述分裂栅(21)之后执行，以增加n--外延(14)的上部部分的掺杂浓度。
进一步的，其中所述ILD(32)、所述半绝缘场板(34)以及所述薄电介质层(33)同时通过光刻以及蚀刻进行图案化。
附图说明
图1是现有技术功率MOSFET结构的截面图。
图2是另一现有技术功率MOSFET结构的截面图。
图3是又另一现有技术功率MOSFET结构的截面图。
图4是实施于功率MOSFET中的本发明的截面图。
图5是实施于IGBT中的本发明的截面图。
图6A至图6H示出先前在图4中示出的功率MOSFET的关键制造过程步骤。
图7A至图7H示出先前在图5中示出的IGBT的关键制造过程步骤。
具体实施方式
图1是现有技术功率MOSFET结构的截面图。栅电极(21)在栅电介质(31)的顶部上，并且栅电介质(31)覆盖n--外延(14)的整个表面。
图2是另一现有技术功率MOSFET结构的截面图。装置具有分裂栅(21)以及栅(21)下方的栅电介质(31)。仅n--外延(14)的小部分表面由栅电介质(31)覆盖，而剩余的表面由层间电介质(ILD)(32)覆盖。
图3是又另一现有技术功率MOSFET结构的截面图。装置具有分裂栅(21)以及位于分裂栅(21)之间的虚拟栅(22)。虚拟栅(22)连接到源极电极(22)，并且虚拟栅(22)通过ILD(32)与分裂栅(21)隔离。
图4是实施于功率MOSFET中的本发明的截面图。平面功率MOSFET结构包括在底部处的漏极电极(23)；n+衬底(15)；在n+衬底(15)的顶部上的n--外延(14)；p+扩散(12)，所述p+扩散由源极电极(22)接触；p型体区(13)，所述p型体区通过p+扩散(12)连接到源极电极(22)；n+源极(11)，所述n+源极由源极电极(22)接触；栅电介质(31)，所述栅电介质覆盖p型体区(13)的表面并且在n+源极(11)与n--外延(14)之间形成沟道；在栅电介质(31)的顶部上的分裂栅电极(21)；薄电介质层(33)，所述薄电介质层覆盖分裂栅(21)以及n--外延(14)的表面两者；半绝缘场板(34)，所述半绝缘场板在薄电介质层(33)的顶部上并且在侧壁处由源极电极(22)接触；在半绝缘场板(34)的顶部上的层间电介质(ILD)(32)；以及源极电极(22)，所述源极电极在接触孔(41)中并且在ILD(32)的顶部上。源极电极(22)和漏极电极(23)通常是金属或金属硅化物。栅电介质(31)通常是氧化硅，但是其他高介电常数材料(例如，氧化铝、氮氧化物以及二氧化铪)还可以用作栅电介质(31)。装置的栅电极(21)通常是多晶硅，因为其适合于自对准高温过程。然而，出于最小化栅电阻的目的，金属或金属硅化物还可以用作栅电极(21)。薄电介质层(33)通常是氧化硅，但是其他介电材料也可以用于隔离目的。ILD(32)也用于隔离，并且通常ILD(32)是氧化硅。半绝缘场板(34)可以是任何高电阻率材料，其包含(但不限于)氮化钛、多晶硅以及非晶硅。
图5是实施于IGBT中的本发明的截面图。IGBT的结构类似于先前在图4中所示的功率MOSFET的结构。在IGBT中，发射极(24)而不是源极电极(22)位于表面处，并且集电极(25)而不是漏极电极(23)位于底部处。在IGBT中不存在n+衬底(15)，但是n缓冲区(16)以及p+集电区(17)位于n-漂移区(14)的下方。
图6A至图6H示出先前在图4中示出的功率MOSFET的关键制造过程步骤。制造过程包括(1)通过外延生长在n+衬底(15)的顶部上形成n--外延(14)；(2)通过注入以及主扩散形成p+扩散(12)；(3)形成栅电介质(31)，通过淀积形成栅电极(21)，图案化栅电介质(31)以及栅电极(21)两者；(4)通过自对准注入以及主扩散形成p型体区(13)；(5)通过图案化栅电极(21)以及栅电介质(31)形成分裂栅(21)；(6)通过注入以及退火形成n+源极(11)，淀积薄电介质层(33)、半绝缘场板(34)以及ILD(32)；(7)图案化ILD(32)、半绝缘场板(34)以及薄电介质层(33)以形成接触孔(41)；以及(8)在表面处形成源极电极(22)并且在底部处形成漏极电极(23)。在制造过程中，分裂栅(21)通过光刻以及随后蚀刻而形成。通常此种光刻需要额外的掩模。此外，在形成分裂栅(21)之后，离子注入步骤可以任选地在形成n+源极(11)之前添加，以增加n--外延(14)的上部部分的掺杂浓度，并且因此产生减小的导通电阻。ILD(32)、半绝缘场板(34)以及薄电介质层(33)可以通 过使用用于接触孔(41)的掩模光刻并且随后蚀刻而一起进行图案化。
图7A至图7H示出先前在图5中示出的IGBT的关键制造过程步骤。所述制造步骤类似于从图6A至图6H示出的制造步骤。在IGBT的制造中，所述过程以轻掺杂的n-衬底晶片(14)而不是n--外延(14)开始。所述过程与功率MOSFET的过程相同，直到在表面处形成发射极(24)电极，如图7G所示。在此步骤之后，n-衬底晶片(14)变细，并且n缓冲区(16)通过在后侧处的离子注入以及退火形成。随后p+集电区(17)通过在后侧处的离子注入以及退火形成。最终，集电极(25)在晶片的后侧处形成，如图7H中所示。

Claims (22)

  1. 一种分裂栅平面功率MOSFET结构，其包括
    在底部处的漏极电极(23)，
    第一导电型的重掺杂衬底(15)，
    第一导电型的轻掺杂外延层(14)，所述轻掺杂外延层在所述重掺杂衬底(15)的顶部上，
    第二导电型的重掺杂扩散(12)，所述重掺杂扩散(12)由源极电极(22)接触，
    第二导电型的体区(13)，所述的体区(13)通过所述重掺杂扩散(12)连接到所述源极电极(22)，
    第一导电型的重掺杂源极(11)，所述重掺杂源极(11)由所述源极电极(22)接触，
    栅电介质(31)，所述的栅电介质(31)覆盖所述体区(13)的表面并且在所述重掺杂源极(11)与所述轻掺杂外延层(14)之间形成沟道，
    分裂栅电极(21)，所述分裂栅电极(21)在所述栅电介质(31)的顶部上，
    薄电介质层(33)，所述薄电介质层(33)覆盖所述分裂栅(21)以及所述轻掺杂外延层(14)的所述两者表面，
    半绝缘场板(34)，所述半绝缘场板(34)在所述薄电介质层(33)的顶部上并且在侧壁处由所述源极电极(22)接触，
    层间电介质(ILD)(32)，所述层间电介质(32)在所述半绝缘场板(34)的顶部上，
    以及源极电极(22)，所述源极电极在接触孔(41)中并且在所述ILD(32)的顶部上。
  2. 根据权利要求1所述的分裂栅平面功率MOSFET结构，其中所述栅电介质(31)是氧化硅。
  3. 根据权利要求1所述的分裂栅平面功率MOSFET结构，其中所述分裂栅电极(21)是多晶硅、金属或金属硅化物中的至少一种。
  4. 根据权利要求1所述的分裂栅平面功率MOSFET结构，其中所述薄电介质层(33)是氧化硅。
  5. 根据权利要求1所述的分裂栅平面功率MOSFET结构，其中所述半绝缘场板(34)包含氮化钛、多晶硅以及非晶硅。
  6. 根据权利要求1所述的分裂栅平面功率MOSFET结构，其中所述ILD(32)是氧化硅。
  7. 根据权利要求1所述的分裂栅平面功率MOSFET结构，其中所述漏极电极(23)以及所述源极电极(22)两者是金属或金属硅化物。
  8. 一种分裂栅平面IGBT结构，其包括
    在底部处的集电极(23)，
    第二导电型的重掺杂集电区(17)，
    第一导电型的缓冲区(16)，所述的缓冲区(16)在所述集电区(17)的顶部上，
    第一导电型的轻掺杂漂移区(14)，所述的轻掺杂漂移区(14)在所述缓冲区(16)的顶部上，
    第二导电型的重掺杂扩散(12)，所述重掺杂扩散(12)由发射极(24)接触，
    第二导电型的体区(13)，所述的体区(13)通过所述重掺杂扩散(12)连接到所述发射极(22)，
    第一导电型的重掺杂发射区(11)，所述重掺杂发射区(11)由所述发射极(24)接触，
    栅电介质(31)，所述栅电介质(31)覆盖所述体区(13)的表面并且在所述重掺杂发射区(11)与所述轻掺杂漂移区(14)之间形成沟道，
    分裂栅电极(21)，所述分裂栅电极在所述栅电介质(31)的顶部上，
    薄电介质层(33)，所述薄电介质层覆盖所述分裂栅(21)以及所述轻掺杂外延层(14)的所述表面两者，
    半绝缘场板(34)，所述半绝缘场板(34)在所述薄电介质层(33)的顶部上并且在侧壁处由所述发射极(24)接触，
    层间电介质(ILD)(32)，所述层间电介质在所述半绝缘场板(34)的顶部上，
    以及发射极(24)，所述发射极在接触孔(41)中并且在所述ILD(32)的顶部上。
  9. 根据权利要求8所述的分裂栅平面IGBT结构，其中所述集电极(25)以及所述发射极(24)两者是金属或金属硅化物。
  10. 根据权利要求8所述的分裂栅平面IGBT结构，其中所述栅电介质(31)是氧化硅。
  11. 根据权利要求8所述的分裂栅平面IGBT结构，其中所述分裂栅电极(21)是多晶硅、金属或金属硅化物中的至少一种。
  12. 根据权利要求8所述的分裂栅平面IGBT结构，其中所述薄电介质层(33)是氧化硅。
  13. 根据权利要求8所述的分裂栅平面IGBT结构，其中所述半绝缘场板(34)包含氮化钛、多晶硅以及非晶硅。
  14. 根据权利要求8所述的分裂栅平面IGBT结构，其中所述ILD(32)是氧化硅。
  15. 一种用于分裂栅平面功率MOSFET结构的制造方法，其包括
    (1)通过外延生长在第一导电型的重掺杂衬底(15)的顶部上形成第一导电型的轻掺杂外延层(14)，
    (2)通过离子注入以及热扩散形成第二导电型的重掺杂扩散(12)，
    (3)形成栅电介质(31)，通过淀积形成栅电极(21)，图案化所述栅电介质(31)以及所述栅电极(21)，
    (4)通过自对准离子注入以及热扩散形成第二导电型的体区(13)，
    (5)通过图案化所述栅电极(21)以及所述栅电介质(31)形成分裂栅(21)，
    (6)通过离子注入以及退火形成第一导电型的重掺杂源极(11)，淀积薄电介质层(33)、半绝缘场板(34)以及ILD(32)，
    (7)图案化所述ILD(32)、所述半绝缘场板(34)以及所述薄电介质层(33)以形成接触孔(41)以及
    (8)在底部在表面以及漏极电极(23)处形成源极电极(22)。
  16. 根据权利要求15所述的制造方法，其中所述分裂栅(21)通过光刻以及蚀刻进行图案化。
  17. 根据权利要求15所述的制造方法，其中离子注入任选地在蚀刻所述分裂栅(21)之后执行，以增加n--外延(14)的上部部分的掺杂浓度。
  18. 根据权利要求15所述的制造方法，其中所述ILD(32)、所述半绝缘场板(34)以及所述薄电介质层(33)同时通过光刻以及蚀刻进行图案化。
  19. 一种用于分裂栅平面IGBT结构的制造方法，其包括
    (1)以第一导电型的轻掺杂的衬底晶片(14)开始，
    (2)通过离子注入以及热扩散形成第二导电型的重掺杂扩散(12)，
    (3)形成栅电介质(31)，通过淀积形成栅电极(21)，图案化所述栅电介质(31)以及所述栅电极(21)，
    (4)通过自对准离子注入以及热扩散形成第二导电型的体区(13)，
    (5)通过图案化所述栅电极(21)以及所述栅电介质(31)形成分裂栅(21)，
    (6)通过注入以及退火形成第一导电型的重掺杂发射区(11)，淀积薄电介质层(33)、半绝缘场板(34)以及ILD(32)，
    (7)图案化所述ILD(32)、所述半绝缘场板(34)以及所述薄电介质层(33)以形成接触孔(41)，并且在表面处形成发射极(24)以及
    (8)使所述衬底晶片(14)变薄，通过离子注入以及退火形成第一导电型的缓冲层(16)，通过离子注入以及退火形成重掺杂集电区(17)，在底部处形成集电极(25)。
  20. 根据权利要求19所述的制造方法，其中所述分裂栅(21)通过光刻以及蚀刻进行图案化。
  21. 根据权利要求19所述的制造方法，其中离子注入任选地在蚀刻所述分裂栅(21)之后执行，以增加n--外延(14)的上部部分的掺杂浓度。
  22. 根据权利要求19所述的制造方法，其中所述ILD(32)、所述半绝缘场板(34)以及所述薄电介质层(33)同时通过光刻以及蚀刻进行图案化。
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