CN1218290A - 具有伪键合线的半导体集成电路器件 - Google Patents

具有伪键合线的半导体集成电路器件 Download PDF

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Publication number
CN1218290A
CN1218290A CN98100138A CN98100138A CN1218290A CN 1218290 A CN1218290 A CN 1218290A CN 98100138 A CN98100138 A CN 98100138A CN 98100138 A CN98100138 A CN 98100138A CN 1218290 A CN1218290 A CN 1218290A
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China
Prior art keywords
bonding line
bonding
wire
lead
pad
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CN98100138A
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English (en)
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姜帝凤
宋永僖
成始燦
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN1218290A publication Critical patent/CN1218290A/zh
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Abstract

本文提供一种带有伪键合线的半导体集成电路器件。伪键合线将器件中的键合线与注入模具空腔内的液态模制树脂流前端隔开,避免后者与金属线直接接触,防止了键合线的摆动现象。本发明通过放松对增加器件内的金属线的长度的限制,可以减小该半导体集成电路器件的尺寸,提高了产量和降低了生产成本。

Description

具有伪键合线的半导体集成电路器件
本发明涉及半导体集成电路(IC)器件，特别是本发明涉及一种带有伪键合线的半导体集成电路器件，这种伪键合线用于防止在模制操作期间由于金属线的摆动而引起短路。
半导体集成电路器件需要一种与外部设备实现电连接的通信装置，例如键合焊盘。这种电连接的最常用的方式是采用键合线将这些键合焊盘与基片(引线框或印刷电路板)上的相应的引线(或有线连接的图形)相连接。所述的键合线通常是用金、铝或其合金制成。
当前集成电路设计和制造工艺的快速发展迫切要求提高半导体集成电路器件的集成度和减小其尺寸。因此，随着键合焊盘的尺寸和间距以及引线的宽度和间距的减小，引线和键合焊盘的数量呈增多趋势。此外，由于半导体集成电路器件的生产条件所限，引线的间距的减小不可能是无限的。所以，在引线和芯片之间的空间应增大，以使更多的引线能够围绕着芯片布线，而且需要增大将引线与芯片连接的键合线的长度。当模制树脂被注入模具空腔内时，由于树脂流前导的作用，长度长的键合线更易于被移位或被拖动，从而与相邻的键合线发生接触和造成该器件短路。这种情况的存在限制了器件尺寸的进一步减小。
在转化模制操作期间要防止金属线的摆动，同时采用长金属线是实现器件尺寸减小的重要途径。减小器件尺寸，以使每个晶片上的器件数量增加，这样可以提高生产力和降低生产成本。在各种半导体集成电路器件的制造过程中，金属线的摆动是一个共同存在的问题，特别是带有大量I/O管脚的多管脚封装和薄封装，金属线的摆动更是制造中的难题。
当前的批量生产允许所制造的集成电路器件带有的键合线的最大尺寸是200密耳。键合线长度的最大值是由模制操作工艺所决定的，而与金属线连接操作本身无关。也就是说，尽管线键合操作允许采用的金属线尺寸是250密耳，但是由于在模制操作期间模制树脂流动造成金属线摆动，因此不可能使用200密耳长的或更大规格的金属线。
下面将参照附图1-附图4说明在现有的半导体集成电路器件中存在的金属线摆动现象。图1是描述常规的半导体集成电路器件的平面图；图2是沿图1的Ⅱ-Ⅱ剖线剖开的断面图；图3是描述由于模制树脂流动造成的键合线摆动情况的平面图，图4是沿图3的Ⅳ一Ⅳ剖线剖开的断面图，说明了在金属线摆动之前和之后的键合线的位置。
图1中所示的集成电路器件是一种通常称为QFP(方形扁平封装)的多针封装。在制造这种器件进行金属线连接操作时，芯片10由键合线30连接到引线框20上，之后准备进行模制操作。芯片10安装在引线框20的管芯焊垫22上，这种管芯焊垫22通过多个(例如4个)位于引线框20的角落上的连杆26配置在引线框20上。引线框20的引线24通过键合线30与相应的键合焊盘12电连接。
这些器件将接受模制操作。其中的芯片、电连接和管芯焊垫将被模制树脂所密封。在图中虚线40所示的区域内将被树脂灌封。图2是沿图1的Ⅱ-Ⅱ剖线剖开的断面图，表示该器件正位于模具空腔50内，允许模制复合体流注入的门52放置在图1中的四个连杆26之一的附近之处。模制树脂流通过门52注入模具空腔，其流动方向用标号42表示，这些树脂填满了由上和下模具二等分50A,50B所形成的空腔54。
模制树脂是具有高粘度的液体，键合线在模制树脂流注入塑模空腔54时朝着注入方向挠性弯曲或被拖动。图3表示了模制树脂流42造成金属线摆动的情况。图3所示的大部分键合线30在模制树脂流的扭弯力作用下都存在不同幅度的摆动，特别是最靠近连杆26的金属线30a(最外侧的金属线30a)，它承受了朝着相邻金属线30b接触的最大的弯曲力的作用，造成该器件短路(图3的S点)。图4是沿图1和3的Ⅳ一Ⅳ剖线剖开的断面图，说明了在金属线摆动之前和之后的键合线的位移情况。
在图4中，用实线表示在模制操作之前的金属线，用虚线表示在模制操作之后的金属线。如图4所示，最外侧的金属线30a的位移明显大于其他金属线30b和30c，以致使最外侧的金属线30a与相邻的金属线30b相接触和造成短路。其余的金属线30b和30c也经受了一定量的位移，但不会相互间接触和发生短路。下面将分析最外侧的金属线30a经历最大位移的原因。
最外侧的金属线30a与其靠近连杆26侧的相邻的金属线之间的距离(d1)大于金属线30b和另一相邻金属线30c之间的距离(d2)。这是因为连杆26是处于引线框的角落上的缘故。当模制树脂流注入模具空腔时，最外侧的金属线30a比其他金属线30b和30c经受到的弯曲力大得多，朝向其他金属线的接触力也大得多。表示各键合线摆动量的摆动程度，就最外侧的金属线30a而言是4-6％，就其余的金属线30b和30c而言是2-3％。这里，术语‘摆动的幅度’是这样定义的：
【金属线中心的位移/金属线长度】×100。
关于图1-4中所示的集成电路器件，其键合焊盘12的间距是75μm,引线24的间距是200μm(以金属线的内端为基准)，因此相邻线的中心线之间的距离大约为136.5μm。此外，最外侧的金属线30a的长度是218密耳。如果最外侧的金属线30a与相邻的金属线30b的位移比例分别是6％和3％，则最外侧的金属线30a和相邻金属线30b的位移量分别是13密耳(=325μm)和6,5密耳(=162.5μm)。因此，在金属线30a与相邻的金属线30b之间的位移量之差(=162.5μm)远大于它们之间的距离(136.5μm)，从而引起线间接触短路。
为了避免金属线摆动引起的问题，半导体集成电路器件的制造商增加了位于芯片角落上的键合焊盘的间距，以保证在相邻金属线之间具有足够大的空间，这样当出现金属线摆动现象时，不会造成金属线之间的接触或短路。但是这种方案的不可取之处在于：它是与当今减小芯片尺寸的发展趋势背道而驰的。
美国Hara的专利US-P5,302,850提出了另一种方案，致力于模具空腔结构的改进。也就是说，将流入口62a和62b分别设置在上和下模具部件的中心，同时已有的模具在下模具部件的范围内带有一个流入口。根据USP5,302,850，树脂流的流动方向和连接半导体集成电路器件引线的键合线的方向均为大致沿着器件中心线的径向辐射，这样布置是为了防止金属线摆动。
但是，这种方案的不足之处在于，封装当经过模制操作之后形成封装体，由于流入口的存在，它的上和底表面的中心处带有毛刺，这些毛刺有损于随后进行的加标记的工艺的可靠性，在这一工艺中，需将商标名和制造商的名称印到有关封装的外表面上。而且，这种方案需要添置新的模制设备。
因此，本发明的目的是解决在模制操作期间产生的与金属线摆动有关的问题。
本发明允许在增加半导体集成电路器件内的金属线的长度的同时，减小该器件的尺寸。
根据本发明，所提供的半导体集成电路器件提高了生产力，并且降低了生产成本。
本发明提供一种半导体集成电路(IC)器件，它包括：
一个半导体集成电路芯片，具有一个带有多个侧面的有源表面，和多个沿着所述侧面形成于该有源表面上的键合焊盘；
一个衬底，具有多个延伸到所述芯片并且离开所述芯片的引线；
多个键合线，将所述引线与相应的键合焊盘中的对应的一个电连接；
一个包封所述芯片、衬底和键合线的封装体，由灌入模具空腔内的液态模制树脂构成；
其中，所述键合线中的一根或多根(外露线)直接暴露在注入模具空腔内的模制树脂流的前端处，因此它们比其他键合线更易于产生金属线的摆动；
其中所述器件还具有至少一根伪键合线，它保护所述外露线直接暴露在模制树脂流的前端处。
本发明还提供一种半导体集成电路(IC)器件，它包括：
一个半导体集成电路芯片，具有一个带有多个侧面的有源表面，和多个沿着所述侧面形成于该有源表面上的键合焊盘；
一个衬底，具有多个延伸到所述芯片并且离开所述芯片的引线；
多个键合线，将所述引线与相应的键合焊盘中的对应的一个电连接；
一个包封所述芯片、衬底和键合线的封装体，由灌入模具空腔内的液态模制树脂构成；
其中，所述键合线包括一或多根特定的键合线，所述特定的键合线与相邻的键合线之间比与其他的键合线之间分隔有较大的空隙，并且所述键合线还具有至少一根伪键合线，它的高度与所述特定的键合线的高度相同，所述伪键合线布置在所述特定的键合线和其相邻的键合线之间。
本发明还提供一种半导体集成电路(IC)器件，它包括：
一个半导体集成电路芯片，具有一个带有多个侧面的有源表面，和多个沿着所述侧面形成于该有源表面上的键合焊盘；
一个衬底，具有多个延伸到所述芯片并且离开所述芯片的引线；
多个键合线，将所述引线与相应的键合焊盘中的对应的一个电连接；
一个包封所述芯片、衬底和键合线的封装体，由灌入模具空腔内的液态模制树脂构成；
其中，所述键合线包括至少一根第一键合线和至少一根第二键合线，所述的第一键合线的高度小于第二键合线的高度，并且与所述第二键合线相邻布置，其中所述的键合线还包括至少一根伪键合线，它的高度与所述第一键合线的高度相同，所述伪键合线布置在所述第一键合线和其相邻的第二键合线之间。
下面将结合附图详细描述本发明，相信通过以下说明，将更有助于对本发明的各特征及其优越性的理解。各图中类似的标号表示这些部件具有类似的结构。这些附图的内容是：
图1是描述常规的半导体集成电路器件的平面图；
图2是沿图1的Ⅱ-Ⅱ剖线剖开的断面图；
图3是描述由于模制树脂流造成的键合线摆动情况的平面图；
图4是沿图3的Ⅳ一Ⅳ剖线剖开的断面图，说明了在金属线摆动之前和之后的键合线的位置；
图5是说明模具的断面图，其中灌入模制树脂流的门的位置改变到图中的防止金属线摆动的位置；
图6是说明模制操作之前的键合线布线方案的示意图，这种布线用于分析金属线摆动现象的仿真设备中；
图7是模制操作之后的图6的键合线布线方案的示意图；
图8是说明本发明的第一个实施例的采用伪键合线的半导体集成电路器件封装的局部剖开的示意图；
图9是说明在图8的器件的模制操作期间伪键合线的布线方案的局部放大平面图；
图10是沿图9的Ⅹ-Ⅹ线剖开的断面图；
图11是说明根据本发明的第二个实施例在半导体集成电路器件中采用伪键合线及其布线方案的局部平面图；
图12是沿图11的Ⅻ一Ⅻ线剖开的断面图；
图13是说明本发明的采用伪键合线的半导体集成电路器件另一个封装的平面图；
图14是说明根据本发明的第三个实施例在半导体集成电路器件中采用伪键合线及其布线方案的局部平面图；
图15是沿图14的ⅩⅤ-ⅩⅤ线剖开的断面图；以及
图16是说明根据本发明的第四个实施例在半导体集成电路器件中采用伪键合线及其布线方案的局部平面图。
根据本发明的第一个方案，所提供的半导体集成电路器件包括一个半导体集成电路芯片，具有一个带有多个侧面的有源表面，和多个沿着所述侧面形成于该有源表面上的一个衬底，具有多个延伸到所述芯片并且离开所述芯片的引线；通过键合线，键合焊盘与相应的引线中的对应的一根电连接；一个包封所述芯片、衬底和键合线的封装体，由注入模具空腔内的模制树脂构成。
根据本发明的第一个方案的这种器件具有一根或多根外露的键合线，术语外露的含义指在模制操作期间金属线直接暴露在灌入模具空腔内的模制树脂流的前端处，因此如上所述它们比其他键合线承受更大的使金属线产生摆动的力。
根据本发明的第一个方案的这种器件还具有至少一根伪键合线，它保护所述外露线直接暴露在模制树脂流的前端处。本发明的器件中所用的外露线可以是连接最外侧的键合焊盘到相对应的最外侧金属线的键合线，或是第一金属线，它是指与具有与第一金属线的高度不同的第二金属线相邻的第一金属线。在模制时，伪键合线可以是连接管芯焊垫到连杆的两根第一金属线，或可以是连接伪键合焊盘到最外侧引线的键合线。对于后者的情况，伪键合线可以是连接绝缘焊盘到上述外露金属线所连接的引线的键合线。或者，伪金属线可以是连接绝缘焊盘到上述伪引线的键合线。
本发明的第一方案所述的半导体集成电路器件中的衬底可以是引线框或是一个印刷电路板，所述的器件可以选用QFP,TQFP,PLCC,SOP或TSOP。
根据本发明的第二个方案，半导体集成电路器件包括一或多个特定的键合线，它们与相邻的键合线之间具有比与其他的金属线之间的间距更大的间隔。该器件还包括至少一个高度与所述特定的键合线相同的伪键合线，伪键合线配置在所述确定的键合线和它们的相邻金属线之间。
本发明的第二方案所述的半导体集成电路器件中的伪键合线是连接最外侧键合焊盘到相应的某个最外侧引线的键合线。所述伪键合线是连接管芯焊垫到连杆的两个键合线。
根据本发明的第三个方案，半导体集成电路器件包括至少一个第一键合线和至少一个第二键合线，所述的第一和第二金属线具有不同的高度。第一金属线带有特定的键合线，它们与相邻的第一键合线之间具有比与其他的金属线之间的间距更大的间隔。并且伪键合线高度与所述特定的键合线相同，伪键合线配置在所述特定的键合线和它们的相邻金属线之间。
本发明的第三方案所述的半导体集成电路器件中的第二金属线可以是连接键合焊盘到电源端或地端的键合线。伪键合线可以是连接绝缘焊盘到上述特定金属线所连接的引线的键合线。或者，伪键合线可以是连接绝缘焊盘到上述伪引线的键合线。
下面将结合附图详细说明本发明。各附图中的类似的和相同的部件采用类似的和相同的标号表示。
图6是说明在模制操作之前键合线如何布线的示意图，这种布线方案用于分析金属线摆动现象的仿真实验；图7是说明在模制操作之后图6的键合线如何布线的示意图。影响金属线摆动的参数是模制树脂流的粘度和流量，金属线的长度和高度，以及模制树脂流相应于键合线的角度等等。使最外侧的金属线摆动的最主要的和起支配作用的原因是相邻的金属线之间的距离或间隔。因此，金属线摆动的程度与金属线暴露在模制树脂流前导的程度密切相关。为了证实此点，我们进行了仿真实验。
如同图6所示，将芯片110的四个边之一分成A、B、C、D四段。段A内包含具有较低高度的键合线，段B和D内包含具有较高高度的键合线，段C内没有金属线。在完成如图7所示的模制操作后，每段出现了最严重的金属线摆动情况，使直接暴露在模制树脂流前导的最外侧的金属线130a,130b,130d发生短路。
仿真实验的条件和结果如下：
·封装类型：208QFP
·引线框120的引线间距：200μm
·芯片110的尺寸：4675μm×4675μm
·键合焊盘112的间距：75μm
·键合线130的直径：1.3密耳(=32.5μm)
·键合线130的高度：180-200μm(h1)
                   450-470μm(h2)
·键合线130的长度：182-218μm
·金属线摆动的幅度：2.6％(对于130a)
                    1.0-1.3％(对于所有分段A的金属线，除了
                    最外侧金属线130b)
                    4％(对于130d)
                    1-2％(对于所有分段D的金属线，除了最外
                       侧金属线130d)
这个结果表明最早接触模制树脂流前端的最外侧金属线130a,130b,130d承受了最严重的金属线摆动，因此使集成电路器件发生短路。分段B的金属线的相邻金属线之间的间隔与分段A类似，但是各相邻金属线具有不同的高度，分段B的金属线所经受的金属线摆动的严重程度几乎与分段D的金属线摆动幅度相同。分段D位于没有金属线的分段C之后，因此在分段D内的金属线130d经受到模制树脂流的严重和直接的弯曲力的作用。另一方面，分段A内的金属线比其他分段内的金属线经受较小的摆动。但是分段A内的金属线的高度太小，所提供的连接强度不够，这会对集成电路器件的大批量生产带来困难。
可以认为，特定的金属线(最早受到流入模具空腔的模制树脂流的冲击)的摆动是非常有意义的，可以减少上述的金属线外部受力问题，能够防止或有效地减少金属线的摆动。而且，所有接触树脂流前端的金属线具有相类似的程度，使每根线的摆动幅度相同或相类似。此外，该器件的设计使金属线的摆动和短路不会影响器件的正常功能。下面介绍本发明的特定的实施例。
图8是说明根据本发明的第一实施例的采用伪键合线的半导体集成电路封装的局部断面图；图9是在图8的器件模制操作期间说明伪键合线的布线方案的局部放大的平面图；图10是沿图9的剖线Ⅹ-Ⅹ剖开的断面图。参照图8-10，半导体集成电路器件包括一个半导体芯片110，它带有一个包括多个(例如四个)侧边的有源表面114，和多个形成于所述有源表面上的沿着侧边的键合焊盘112。芯片110装在引线框120的管芯焊垫122上。连杆126从管芯焊垫122的角落延伸，在封装组装过程中支撑管芯焊垫122和芯片110。引线框120的引线124从芯片110向外引出，并且围绕该芯片布线，引线124从四面径向朝芯片110延伸。
引线124通过键合线130与相应的某个键合焊盘112实现电连接。芯片110、引线124和键合线130被密封在图示的封装体140中，引线124向140外延伸的局部形成了适于安装到外部的印刷电路板PCB(图中未示出)上的构形，从而制成了一个封装100。图8所示的封装是QFP的一个实施例。除了最外部的金属线130e,130f以外，每根金属线130在相邻的金属线之间具有相同的间隔或间距。在连杆126两侧的最外部的金属线130e,130f的间距比其他金属线的间距要大。当模制树脂流入模具空腔时，最早接触树脂流前端的最外部的金属线130e出现最强的摆动和使相邻的金属线发生短路。为了避免金属线摆动和发生短路，多个(例如两个)伪键合线132(132a,132b)安装在连杆126附近，以便减小最外部的金属线130e,130f的间隔，使最外部的金属线130e摆动的幅度接近于其他的金属线，防止了短路的发生。
伪键合线132可以通过将连杆126与未装有芯片110的管芯焊垫的其余部分耦连而形成。为了减小模制树脂流施加到最外部的金属线130e上的作用力，最好使伪键合线132的高度与最外部的金属线130e的高度相同。作为一个实际问题，很容易将伪键合线132的高度控制到恰好是一个耦合点，因为线键合操作完全是自动完成的。
非常重要的是应当配置伪键合线132，使伪键合线132和最外侧金属线130e之间的间隔几乎相同或与其他金属线130相同。相反，在伪键合线132和相对面的最外侧金属线130f之间的间隔不具有上述特点。采用这种布线方案，即使最早面对模制树脂流的伪键合线132a经受了最强烈的摆动和与相邻的伪键合线132b短接，也不会造成集成电路器件的短路问题，因为伪键合线132a和132b是与连杆126耦连的，不带电。这说明了为什么应当采用伪键合线132a和132b的原因。
图11是说明根据本发明的第二个实施例在半导体集成电路器件中如何布置伪键合线的局部平面图。图12是沿图11的Ⅻ一Ⅻ剖线剖开的断面图。根据图11和12，该半导体集成电路器件具有与上述第一个实施例相同的结构，不同点在于伪键合线134的结构不同。根据第二个实施例，一个伪键合焊盘116形成在芯片110的有源表面上，它位于最外侧的键合焊盘112e以外，并且朝向芯片110的角落布线。伪键合焊盘116具有与最外侧的键合焊盘112e相同的功能。伪键合焊盘116通过伪键合线134与最外层的引线124e相连接。因此，最外层的引线124e连接到最外侧的键合焊盘112e和伪键合焊盘116上。当模制树脂流流入所述模具空腔时，伪键合线134最早接触该树脂流前端，因此承受最大的摆动。可是，由于最外层金属线130e连接到伪键合焊盘116以及最外侧的键合焊盘112e，除了位置不同以外，该金属线也具有同样的功能，因此最外层金属线130e与伪键合线134的接触和短路还会带来问题。
尽管上述的第一和第二实施例均以QFP多针封装为例，但是本发明的器件也可以采用其他类型的封装。实际上，例如多针封装可以采用PLCC(塑料引线芯片载流子)，薄型封装可以采用SOP(小轮廓线封装),TSOP(薄型小轮廓线封装)或TQFP(薄型方扁平封装)以及BGA封装(球珊格阵列)。
图13是说明BGA封装的平面图，作为另一种封装，它包括本发明的伪键合线。在该BGA封装200中，印刷电路板(PCB)220用作电连接装置，这一点与QFP封装不同，后者的引线框用作电连接装置。PCB220包括一个安装在芯片110上的管芯焊垫222，引线224(或代连线的图形)通过金属线与芯片110连线，类似于QFP的引线框。PCB220与引线框是不同的，管芯焊垫222和引线224形成在一个绝缘树脂体221上，并且通过绝缘树脂体221上的孔225与焊球228电连接。图13中的标号240代表一个封装体。
这种BGA封装200也会由于金属线的摆动发生短路。BGA封装可以用在上述本发明的第一和第二实施例中。BGA封装的管芯焊垫和引线之间可以配置电源端子或接地端子。这些端子通常围绕管芯焊垫环形布置，并且电连接到芯片上的有关的一个或多个键合焊盘上。
连接到电源端或接地端上的键合线的高度一般比其他键合线的高度低，具有较低高度的金属线产生的效果就象在具有较高的高度的金属线上没有金属线一样。因此，在这种情况下，还会发生金属线摆动和使器件短路的问题。本发明的第三和第四实施例对此提出了对策。
图14是说明根据本发明的第三个实施例在半导体集成电路器件中采用伪键合线及其布线方案的局部平面图；图15是沿图14的ⅩⅤ-ⅩⅤ剖线剖开的断面图。参见图14和15，电源端子或接地端子223位于芯片110所在的管芯焊垫222和引线224之间。键合焊盘之一112g通过键合线130g电连接到电源端子223上，键合线130g的高度为‘h1’，它比其他金属线的高度‘h2’要低。因此，与键合线130g相邻的金属线130h(外露金属线)直接暴露在模制树脂流前导142面前，承受最大的摆动力和发生短路。
为了避免金属线由于金属线的高度不同产生摆动，在外露金属线130h和较短的金属线130g之间具有一个伪键合线136。伪键合线136将绝缘焊盘222a与引线224h相连接，其中引线224h与外露线130h相连接。伪键合线136的高度与外露金属线130h的高度‘h2’相同，因此，伪键合线136发生摆动和短路不会带来问题。
图16是说明根据本发明的第四个实施例在半导体集成电路器件中采用伪键合线及其布线方案的局部平面图。这个模制实施例与第三个实施例的不同在于伪键合线138从绝缘焊盘222a连接到伪引线224i，伪引线224i是一个绝缘引线，它不与外部电触点例如焊球(图13中228)电连接。
本发明可以防止在模制操作期间发生金属线摆动和使半导体集成电路器件短路，因此能够有效地放松对增加键合线长度的限制程度。而且还减少了芯片的尺寸，增加了每个晶片上的芯片的数量，提高了产量，降低了生产成本。
此外，本发明的优越性在于可以利用已有的设备，只需对涉及金属线布线操作的程序稍作改进，就能够实施和应用在各种不同的封装制造上。
以上对本发明的优选的实施例已经进行了详细的说明，所属领域的一般技术人员在本发明的基本发明概念的启示下，可以作出许多改进和/或完善，显然，这些改进和/或完善将依然不违背在权利要求书中所定义的精神和落入权利要求书所限定的范围内。

Claims (24)

1．一种半导体集成电路器件(IC)，包括：
一个半导体集成电路芯片，具有一个带有多个侧面的有源表面，和多个沿着所述侧面的形成于所述有源表面上的键合焊盘；
一个衬底，具有多个延伸到所述芯片并且离开所述芯片的引线；
多个键合焊盘，用于将所述引线与所述相应的键合线中的对应的一根电连接；
一个包封所述芯片、衬底和键合线的封装体，由注入模具空腔内的液态模制树脂构成；
其中，一根或多根(外露金属线)所述的键合线直接暴露在灌入模具空腔内的模制树脂流的前端处，因此它们比其他键合线承受更大的使金属线产生摆动的力；而且
其中所述的器件还具有至少一根伪键合线，它保护所述外露线直接暴露在模制树脂流的前端处。
2．根据权利要求1所述的半导体IC器件，其特征在于，所述伪键合线的高度与所述外露金属线的高度相同。
3．根据权利要求2所述的半导体IC器件，还包括布置在所述芯片的角落上的最外侧的键合焊盘，其特征在于，所述外露金属线是将所述最外侧的键合焊盘与相关的最外侧的引线连接的键合线。
4．根据权利要求3所述的半导体IC器件，其特征在于，所述衬底还包括一个其上安装芯片的管芯焊垫和沿着所述管芯焊垫的各角落延伸的与所述管芯焊垫的角落整体形成的连杆，其中所述伪键合线是两根相邻的金属线，连接所述管芯焊垫到所述连杆之一，所述的一个连杆是指位于布置有外露键合线的那个角落上的连杆。
5．根据权利要求3所述的半导体IC器件，还包括相邻于所述最外侧的焊盘的伪焊盘，它具有与所述最外侧的焊盘相同的功能，并且其特征在于，所述伪键合线将所述伪焊盘与所述最外端引线中的相应的一根相连接。
6．根据权利要求2所述的半导体IC器件，还包括第一和第二金属线，所述第一金属线的高度与所述第二金属线的高度不同，并且与第二金属线相邻布置，其特征在于，所述第一金属线是指外露金属线。
7．根据权利要求6所述的半导体IC器件，其特征在于，所述衬底还包括一个其上安装芯片的管芯焊垫和位于所述的管芯焊垫的一个表面上的绝缘焊盘，其中所述伪键合线连接所述绝缘焊盘到连接所述外露金属线的引线上。
8．根据权利要求6所述的半导体IC器件，其特征在于，所述衬底还包括一个其上安装芯片的管芯焊垫，绝缘焊盘位于所述的管芯焊垫的一个表面上，伪引线与外部设备没有电相连，其中所述伪键合线连接所述绝缘焊盘到所述伪引线。
9．根据权利要求2所述的半导体IC器件，其特征在于，所述衬底是一个引线框。
10．根据权利要求9所述的半导体IC器件，其特征在于，所述衬底是QFP,TQFP,PLCC,SOP或TSOP之一。
11．根据权利要求2所述的半导体IC器件，其特征在于，所述衬底是一个印刷电路板，所述印刷电路板包括一个绝缘树脂衬底，在所述绝缘树脂衬底上的一个管芯焊垫，在所述树脂衬底上的引线从所述树脂衬底的通孔中穿出。
12．根据权利要求11所述的半导体IC器件，它是一种BGA封装。
13．一种半导体集成电路器件(IC)，包括：
一个半导体集成电路芯片，具有一个带有多个侧面的有源表面，和多个沿着所述侧面形成于所述有源表面上的键合焊盘；
一个衬底，具有多个延伸到所述芯片并且离开所述芯片的引线；
多个键合线，用于将所述引线与所述相应的键合焊盘中的对应的一个电连接；
一个包封所述芯片、衬底和键合线的封装体，由注入模具空腔内的液态模制树脂构成；
其特征在于，所述键合线包括一或多个特定的键合线，所述特定的键合线与相邻的键合线之间具有比与其他的金属线之间的间距更大的间隔，并且所述键合线还包括至少一个高度与所述特定的键合线相同的伪键合线，所述伪键合线配置在所述确定的键合线和它们的相邻键合线之间。
14．根据权利要求13所述的半导体集成电路器件，包括布置在所述芯片角落上的最外侧键合焊盘，所述的特定的键合线是连接所述最外侧键合焊盘到相应的某个最外侧引线的键合线，所述的最外侧引线是最早接触注入模具空腔内的模制树脂流前端的引线。
15．根据权利要求14所述的半导体集成电路器件，其特征在于，所述衬底还包括一个其上安装芯片的管芯焊垫和沿着所述管芯焊垫的各角落延伸的与所述管芯焊垫的角落整体形成的连杆，其中所述伪键合线是两根相邻的金属线，连接所述管芯焊垫到所述连杆之一，金属线连接所述伪键合焊盘到相关的一根最外侧的引线，所述的一个连杆是指位于布置有确定的键合线的那个角落上的连杆。
16．根据权利要求14所述的半导体IC器件，还包括相邻于所述最外侧的键合焊盘的伪键合焊盘，它具有与所述最外侧的键合焊盘相同的功能，并且其特征在于，所述伪键合线将所述伪焊盘与所述最外端引线中的相应的一根相连接。
17．根据权利要求13所述的半导体IC器件，其特征在于，所述衬底是一个引线框。
18．根据权利要求17所述的半导体IC器件，其特征在于，该器件是QFP,TQFP,PLCC,SOP或TSOP中的一个。
19．根据权利要求13所述的半导体IC器件，其特征在于，所述衬底是一个印刷电路板，所述印刷电路板包括一个绝缘树脂衬底，在所述绝缘树脂衬底上的一个管芯焊垫，在所述树脂衬底上的引线从所述树脂衬底的通孔中穿出。
20．根据权利要求19所述的半导体IC器件，它是一种BGA封装。
21．一种半导体集成电路器件(IC)，包括：
一个半导体集成电路芯片，具有一个带有多个侧面的有源表面，和多个沿着所述侧面形成于所述有源表面上的键合焊盘；
一个衬底，具有多个延伸到所述芯片并且离开所述芯片的引线；
多个键合线将所述引线与所述相应的键合焊盘中的对应的一个电连接；
一个包封所述芯片、衬底和键合线的封装体，由注入模具空腔内的液态模制树脂构成；
其特征在于，所述键合线包括至少一根第一键合线和至少一根第二键合线，所述的第一键合线的高度小于第二键合线的高度，并且与所述第二键合线相邻布置，其中所述的键合线还包括至少一根伪键合线，它的高度与所述第一键合线的高度相同，所述伪键合线布置在所述第一键合线和其相邻的第二键合线之间。
22．根据权利要求21所述的半导体集成电路器件，其特征在于，所述衬底还包括一个其上安装芯片的管芯焊垫和至少一个位于所述管芯焊垫附近的电源端或接地端，其中所述第二键合线连接所述管芯焊垫到所述的端子。
23．根据权利要求22所述的半导体集成电路器件，其特征在于，所述第一键合线还包括特定的键合线，它们与相邻的第一键合线之间的间隔大于与其他的第一键合线之间的间隔，其中所述管芯焊垫的一个表面上带有绝缘焊盘，其中所述伪键合线连接绝缘焊盘到上述特定金属线所连接的引线。
24．根据权利要求22所述的半导体集成电路器件，其特征在于，所述管芯焊垫的一个表面上还带有绝缘焊盘，并且在所述引线之间还包括伪引线，所述伪引线不与外部设备电连接；和其中所述伪键合线将所述绝缘焊盘与所述伪引线中相应的一根相连接。
CN98100138A 1997-11-21 1998-01-16 具有伪键合线的半导体集成电路器件 Pending CN1218290A (zh)

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