CN2619367Y - 应用于高频ic的导线架 - Google Patents

应用于高频ic的导线架 Download PDF

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CN2619367Y
CN2619367Y CNU032399537U CN03239953U CN2619367Y CN 2619367 Y CN2619367 Y CN 2619367Y CN U032399537 U CNU032399537 U CN U032399537U CN 03239953 U CN03239953 U CN 03239953U CN 2619367 Y CN2619367 Y CN 2619367Y
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徐嘉昌
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Abstract

本实用新型是一种应用于高频IC的导线架，包括复数引脚阵列，而在复数引脚阵列上系用于承载至少一芯片，并在引脚底部系形成至少一凹部，且在引脚承载芯片端的底部外缘亦形成一凹部。在进行半导体组件封装时，本实用新型可提供更好接合性及结构支撑，且可使封装后的结构达到更好电性效能并可应用于高频产品。

Description

应用于高频IC的导线架
技术领域
本实用新型涉及一种导线架结构，特别是一种可提供半导体组件封装的导线架，使封装后的结构电性效能更好且体积更小并可应用于高频集成电路。
背景技术
目前半导体的封装结构要求更小的体积、更好的电性效能、更多的功能及更低的价格等。其中，导线架(Lead Frame)的主要功能是提供芯片承载的强度以便进行半导体组件封装，并传送芯片的讯号与外界沟通，因为导线架系直接与芯片接触，所以导线架的热膨胀系数，必须与芯片的热膨胀系数兼容；而导线架的电导性要低，以降低电讯传送的干扰，因此导线架结构的影响相当地深远。
其中，具有低接脚电感(pin inductance)效能的方形扁平无引脚(QuadFlat No-Lead，QFN)封装技术较为新颖，QFN封装主要是以导线架为基础的封装方法，传统的在QFN封装中的导线架结构如图1所示，此导线架10包括一芯片垫片12，以及位于芯片垫片12周围的复数个引脚14。
在进行半导体组件封装时，如图2及图3所示，一芯片(Chip)16利用一环氧树脂(Epoxy)22粘接于芯片垫片12上，并使芯片16的输入/输出(I/O)接点18朝上，再以复数条金线(Gold Wire)20连接芯片16上的I/O接点18与引脚14，最后再以一封装胶体(Molding Compound)24将上述组件包覆成型，此QFN封装结构系符合JEDEC(MO-220)的规格要求。
在半导体组件封装结构中，金线为影响整体电性的主要关键组件之一，但在上述的QFN封装结构中，金线长度太长，而导致电阻(Resistance)及电感(Inductance)等电性效能(Electrical Performance)无法达到须求，此外，当在电性效能无法达到要求时，将传统的QFN封装结构应用于高频产品时，无法确保更快速的传递延迟及更小的输出歪曲率，相对地会出现许多问题及麻烦，而且在整体封装体积亦无法有效减小的情况下，对于传统的导线架结构而言，还是无法提供可以满足目前趋势的半导体组件封装。
发明内容
本实用新型的主要目的是提供一种应用于高频IC的导线架，可大幅缩短引线的长度，因此，比传统的导线架提供更好的封装结构，以达到更好电性效能，亦可减少封装结构的体积，使封装后的结构可应用于高频产品。
本实用新型的另一目的是提供一种应用于高频IC的导线架，可提供更好的接合性，以达到更佳的封装可靠度，亦可提供更好的结构支撑，以利半导体组件封装的制造。
本实用新型的又一目的是提供一种应用于高频IC的导线架，可不必更改引脚原本的尺寸，因此，亦可不必变更印刷电路板的设计。
本实用新型的上述目的是这样实现的，一种应用于高频IC的导线架，其特征在于包括：复数引脚阵列，其上承载至少一芯片，该引脚底部形成至少一凹部，并在该引脚承载该芯片端的底部外缘形成一凹部。
下面结合附图以具体实例对本实用新型进行详细说明，以便对本实用新型的结构特征及所达成的功效有更进一步的了解与认识。
附图说明
图1为传统的导线架的结构仰视图；
图2为应用传统的导线架封装后的结构仰视图；
图3为应用传统的导线架封装后的结构侧视图；
图4为本实用新型的结构仰视图；
图5为应用本实用新型封装后的结构侧视图；
图6为应用本实用新型封装后的结构仰视图；
图7为应用传统的导线架封装后与应用本实用新型封装后引脚与金线结构侧视图；
图8为本实用新型另一实施例的结构仰视图；
图9为应用本实用新型另一实施例封装后的结构侧视图
图10为应用本实用新型另一实施例封装后的结构仰视图。
附图标记说明：10导线架；12芯片垫片；14引脚；16芯片；18输入/输出接点；20金线；22环氧树脂；24封装胶体；30导线架；32芯片垫片；322环状凹部；34引脚；342、344凹部；36芯片；38输入/输出接点；40金线；42环氧树脂；44封装胶体；50导线架；52引脚；522、524凹部；54芯片；56输入/输出接点；58金线；60环氧树脂；62封装胶体。
具体实施方式
本实用新型是利用导线架上凹部的设计，使其应用于半导体组件封装时，可大幅缩短金线长度，以达到更好电性的效能，亦可达到更好的封装可靠度。
如图4及图5所示，一种应用于高频IC的导线架，此导线架(Leadframe)30包括一芯片垫片32，在芯片垫片32底部外缘蚀刻形成一环状凹部322，复数个引脚(Leads)34位于芯片垫片32周围，并在引脚34靠近芯片垫片32的底部外缘蚀刻一凹部342，亦在中间底部亦蚀刻形成一凹部344，且使环状凹部322及凹部342、344的高度为芯片垫片32及引脚34高度的一半。
利用上述导线架30进行半导体组件封装时，请在同时参考图5及图6所示，首先，将一芯片36的输入/输出(I/O)接点38朝下，并利用一环氧树脂42将芯片36粘接于芯片垫片32上，接着，再利用复数引线(较佳者为金线(Gold Wire)40)连接芯片36的I/O接点38及引脚34的凹部342或芯片垫片32的凹部322，之后，再利用一封装胶体44包覆芯片36、导线架30及金线40，并使封装胶体44与引脚34外端缘平齐。
因此，利用上述的导线架30完成半导体组件封装之后，可使金线40的长度比传统的金线的长度还要短许多，这是因为导线架30内芯片垫片32的凹部322及引脚34的凹部342的设计，可使芯片36的I/O接点38朝下粘接于芯片垫片32上，故可缩短金线40连接I/O接点及芯片垫片32的凹部322或引脚34的凹部342的长度，而金线40为影响整个封装结构的电性效能的重要因素的一，故金线40越短整体封装结构的电阻及电感等电性效能越优异，请参考图7A及图7所示，其中，图7A所表示的是应用传统导线架进行封装后的引脚14及金线20的结构侧视图，而图7B所表示的是应用本实用新型进行封装后的引脚34及金线40的结构侧视图。下表所示为电性仿真结果比较表：
Package Wire Length  Lead Length        电感            电阻
附图     mm     mm     nH(wire+lead) m(wire+lead)@100MHz
图7     2.4     0.4  2.4154+0.1150＝2.530 101.4+0.172＝101.5720
图7B     0.4     2.4  0.2670+0.0125＝0.279 16.9+0.0118＝16.9118
由电性仿真结果比较表可以得知，利用本实用新型进行封装后结构的电感(Inductance)为0.2795nH、电阻(Resistance)为16.9118Ω，而利用传统导线架进行封装后结构的电感为2.5304nH、电阻为101.5720Ω，故应用本实用新型进行的封装结构可以得到更好的电性特性，以可确保更快速的传递延迟及更小的输出歪曲率。此外，因芯片36的I/O接点38朝下利用金线40与芯片垫片32及引脚34连接，亦使整体的高度减少许多，而达到整体体积变小且更轻薄的要求，且引脚34上的凹部344可提供更好接合性，亦可提供更佳的结构支撑以利封装制造，因此，利用本实用新型进行封装后的结构，可应用于无线射频、高速内存等高频的产品。
另外，如图8及图9所示，为本实用新型另一实施例，此实施例系可应用于芯片的I/O接点位于芯片的中央位置，如图所示，导线架50包括了复数引脚52阵列，在引脚52阵列上表面用于承载一芯片，每一引脚52底部系蚀刻至少一凹部524，并在引脚52承载芯片端的底部外缘亦蚀刻一凹部522，且使凹部522、524的高度为引脚52高度的一半。
利用上述导线架50进行半导体组件封装时，如图9及图10所示，首先，系将芯片54的I/O接点56朝下，并利用一环氧树脂60粘接于引脚52阵列上，再利用复数金线58连接芯片54的I/O接点56及引脚52的端部凹部522，且再利用一封装胶体62包覆芯片54、导线架50及金线58，并使封装胶体62与引脚54外端缘平齐。
上述应用于I/O接点位于芯片中央的结构中，芯片54的I/O接点56亦为朝下的粘接于引脚52阵列上，再利用金线58连接芯片54的I/O接点56与引脚52的端部凹部522，可使金线58的长度比传统的金线大幅缩短，故整体的封装结构的电阻及电感等电性效能也会较优异，亦可确保更快速的传递延迟及更小的输出歪曲率，而整体的高度亦减少许多，且引脚上52的凹部524同样地可提供更好接合性，也可提供更佳的结构支撑，以利封装制造，故封装后的结构亦可适用于无线射频和高速内存等高频产品。
本实用新型提出了一种应用于高频IC的导线架，可大幅缩短金线的长度，亦可将封装后的整体高度降低，因此，可提供比传统的导线架更好的封装结构，以达到更佳的电性效能并可应用于高频产品；且可提供更好接合性，以达到更佳的封装可靠度，亦可提供更好的结构支撑，以利半导体组件封装的制造；而本实用新型亦可不必更改引脚原本的尺寸，故亦可不必变更印刷电路板的设计。
以上所述仅为本实用新型的较佳实施例，并非用来限定本实用新型的实施范围。故凡依本实用新型权利要求所述的形状、构造、特征及精神所为的均等变化或修饰，均应包括于本实用新型的保护范围内。

Claims (3)

1、一种应用于高频IC的导线架，其特征在于包括：
复数引脚阵列，其上承载至少一芯片，引脚底部形成至少一凹部，并在引脚承载该芯片端的底部外缘形成一凹部。
2、如权利要求1所述的应用于高频IC的导线架，其中，在该导线架粘接一芯片，是将该芯片的输入/输出接点朝下粘接于该引脚阵列上，再利用复数引线连接该芯片的该输入/输出接点及该引脚的该凹部，以形成电性连接。
3、如权利要求2所述的应用于高频IC的导线架，其中，该引脚的凹部以蚀刻成型。
CNU032399537U 2003-03-05 2003-03-05 应用于高频ic的导线架 Expired - Fee Related CN2619367Y (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113690662A (zh) * 2021-08-04 2021-11-23 苏州浪潮智能科技有限公司 一种连接器和印刷线路板总成

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113690662A (zh) * 2021-08-04 2021-11-23 苏州浪潮智能科技有限公司 一种连接器和印刷线路板总成
CN113690662B (zh) * 2021-08-04 2023-08-11 苏州浪潮智能科技有限公司 一种连接器和印刷线路板总成

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