US5296743A - Plastic encapsulated integrated circuit package and method of manufacturing the same - Google Patents
Plastic encapsulated integrated circuit package and method of manufacturing the same Download PDFInfo
- Publication number
- US5296743A US5296743A US08/058,424 US5842493A US5296743A US 5296743 A US5296743 A US 5296743A US 5842493 A US5842493 A US 5842493A US 5296743 A US5296743 A US 5296743A
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- United States
- Prior art keywords
- chip
- leads
- flow direction
- given flow
- integrated circuit
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title abstract description 5
- 239000000463 material Substances 0.000 claims abstract description 15
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 13
- 230000001154 acute effect Effects 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims description 15
- HUWSZNZAROKDRZ-RRLWZMAJSA-N (3r,4r)-3-azaniumyl-5-[[(2s,3r)-1-[(2s)-2,3-dicarboxypyrrolidin-1-yl]-3-methyl-1-oxopentan-2-yl]amino]-5-oxo-4-sulfanylpentane-1-sulfonate Chemical compound OS(=O)(=O)CC[C@@H](N)[C@@H](S)C(=O)N[C@@H]([C@H](C)CC)C(=O)N1CCC(C(O)=O)[C@H]1C(O)=O HUWSZNZAROKDRZ-RRLWZMAJSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01076—Osmium [Os]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49121—Beam lead frame or beam lead device
Definitions
- the present invention relates generally to integrated circuit packages, and more particularly to a specific method of making a particular plastic encapsulated integrated circuit package and the package itself.
- a typical plastic encapsulated integrated circuit package is comprised of (1) an IC chip including an array of chip output/input terminals, (2) means for supporting the chip, for example, either a lead frame or substrate, including an array of electrically conductive leads, all of which are provided for connection with the output/input terminals of the IC chip, (3) bonding wires connecting the chip output/input terminals with respective ones of the leads, and (4) plastic material encapsulating the IC chip, support means and bonding wires.
- This overall integrated circuit package is typically manufactured by initially supporting the IC chip on its support means as a unit with the bonding wires connecting the chip's output/input terminals with respective ones of the leads forming part of the support means. Thereafter, this unit is placed in a cooperating mold and plastic material is caused to flow into the mold through a cooperating gate and in a given flow direction so as to encapsulate the IC chip, support means and bonding wires.
- FIG. 1 diagrammatically illustrates an intermediate step in the formation of a plastic encapsulated integrated circuit package which is generally indicated at 10.
- This package as seen in FIG. 1, includes a die (IC chip) 11 including an array of chip output/input terminals or pads 12.
- This chip is supported on a suitable support member 14 which can be, for example, a standard lead frame or a dielectric substrate.
- the support member includes an array of electrically conductive leads 16, all of which are provided for connection with the output/input terminals of IC chip 11.
- the electrically conductive leads extend out from and are integrally formed with a chip supporting section also forming part of the lead frame.
- the leads 16 are printed on the same surface thereof that supports the IC chip.
- the support member has heretofore typically been designed, more recently by means of CAD tools, such that its leads extend out from the die 11 in a symmetric pattern around the die, as illustrated in FIG. 1. As seen there, one group of leads extend horizontally to the left, another group horizontally to the right, a third group vertically upward and, finally, a fourth group vertically downward.
- leads are provided in a more radial pattern so as to fill up the areas left blank in FIG. 1.
- the various leads 16 are connected to respective output/input terminals 12 of die 11 by means of bonding wires 18 which, more or less, extend in line with their respective leads.
- the overall plastic encapsulated integrated circuit package 10 which includes die 11, its support 14, leads 16 and bonding wires 18, these latter components are interconnected in the manner illustrated in FIG. 1 to form an overall unit.
- This unit is placed in a conventional closed mold which is generally indicated at 20 and which contains a gate or opening 22 for accommodating the flow of plastic material 23 under suitable pressure into the mold and over the die, bonding wires and end segments of the leads from an external source so as to encapsulate these latter components.
- a conventional closed mold which is generally indicated at 20 and which contains a gate or opening 22 for accommodating the flow of plastic material 23 under suitable pressure into the mold and over the die, bonding wires and end segments of the leads from an external source so as to encapsulate these latter components.
- the flow path of plastic material is diagonally from the upper lefthand corner at gate 22 toward the bottom righthand corner, as indicated by arrow 24. It should be apparent from FIG.
- FIG. 2 where a bonding wire is diagrammatically illustrated in three positions, namely 18a, 18b and 18c, with respect to the flow direction 24 of plastic material, as the latter enters mold 20.
- the bond wire shown in position 18a defines an approach angle ⁇ 90° with the flow path of plastic
- position 18b defines a lesser, acute approach angle ⁇
- position 18c defines an approach angle of zero, that is, where the bonding wire is parallel to the direction of flow.
- an integrated circuit package and its method of manufacture wherein the package is encapsulated by plastic which, during formation of the package, is caused to flow over the latter in a given flow direction.
- the package itself comprises an IC chip including an array of chip output/input terminals and a support member, for example a lead frame or a substrate, for supporting the IC chip and including an array of electrically conductive leads, all of which are provided for connection with the input/output terminals of the IC chip.
- the integrated circuit package also includes bonding wires connecting the chip output/input terminals with respective ones of the electrically conductive leads such that each bonding wire extends in a direction that defines an acute angle of less than 45° with the given flow direction of the plastic material.
- bonding wires connecting the chip output/input terminals with respective ones of the electrically conductive leads such that each bonding wire extends in a direction that defines an acute angle of less than 45° with the given flow direction of the plastic material.
- at least a portion of the bonding wires are substantially parallel with the given flow direction of plastic material and, in a most preferred embodiment, substantially all of the bonding wires are parallel or approximately parallel with the given flow direction.
- FIG. 1 diagrammatically illustrates an intermediate step in the formation of a plastic encapsulated integrated circuit package manufactured in accordance with the prior art
- FIG. 2 diagrammatically illustrates how a bonding wire forming part of the package of FIG. 1 is subjected to drag forces caused by the flow of plastic encapsulating material during formation of the package of FIG. 1;
- FIG. 3 diagrammatically illustrates an intermediate step in the formation of a plastic encapsulated integrated circuit package designed in accordance with the present invention to minimize drag forces on its bonding wires during formation of the package;
- FIG. 4 diagrammatically illustrates an intermediate step in the formation of a plastic encapsulated integrated circuit package designed in accordance with a further embodiment of the present invention.
- FIG. 3 diagrammatically illustrates an intermediate step in the formation of a plastic encapsulated integrated circuit package designed in accordance with the present invention and generally indicated by the reference numeral 10'.
- package 10' includes a die or IC chip 11 having an array of chip output/input terminals 12 and supported on a lead frame, substrate or other suitable support means 14' including an array of electrically conductive leads 16', all of which are provided for connection with the output/input terminals of die 11 by means of respective bonding wires 18'.
- Package 10' is shown in the same condition as package 10, that is, within mold 20 awaiting the receipt of plastic material 23 as the latter flows into the mold through gate 22 in the flow direction indicated by arrow 24.
- each of the electrically conductive leads 16' extends in a direction that defines an approach angles ⁇ of less than 45° with the given flow direction 24. Indeed, all of these leads are substantially parallel to flow direction 24, as indicated in FIG. 3. As a result, the various bonding wires 18' extend in substantially corresponding directions. Therefore, the drag on each and every one of these bonding wires due to the inflow of plastic material is minimized. Where support member 14' is a substrate and the leads 16' are printed on one surface thereof, it is relatively easy to provide the leads in the parallel relationship illustrated, regardless of the number of leads in question (within reason).
- the support member is a lead frame
- the desired parallel relationship for high pin count lead frames that is, lead frames of 60 leads or more. Therefore, in the case of lead frames, the configuration illustrated in FIG. 3 is most applicable to low pin count lead frames.
- the present invention has been described in conjunction with a single IC chip on a substrate or lead frame with all of its bonding wires extending substantially parallel with a flow direction 24 of plastic material, it is to be understood that the present invention is not limited to this particular arrangement.
- the present invention contemplates an arrangement where all of the bonding wires are not necessarily parallel to the plastic flow direction but at least define acute angles of less than 45° therewith, in contrast to the prior art configuration illustrated in FIG. 1, thereby decreasing drag resistance across the bonding wires.
- the present invention contemplates more than one die, as illustrated in FIG. 4. As seen there, three dies 30, 32 and 34 are shown supported on a substrate 36 which, in turn, is shown supported on a lead frame 38.
- This overall package is shown receiving a plastic encapsulating compound 40 flowing over the package in the flow direction 42.
- some of the bonding wires interconnecting the dies to cooperating leads on the substrate extend in directions parallel to the flow direction 42 and the rest extend in directions that define acute angles less than 45° with the flow direction 42.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
Claims (15)
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/058,424 US5296743A (en) | 1993-05-07 | 1993-05-07 | Plastic encapsulated integrated circuit package and method of manufacturing the same |
US08/171,713 US5437095A (en) | 1993-05-07 | 1993-12-21 | Method of making plastic encapsulated integrated circuit package |
EP94914128A EP0698291A1 (en) | 1993-05-07 | 1994-04-12 | Plastic encapsulated integrated circuit package and method of manufacturing the same |
JP6525430A JPH08510092A (en) | 1993-05-07 | 1994-04-12 | Plastic-encapsulated integrated circuit package and manufacturing method thereof |
PCT/US1994/004009 WO1994027320A1 (en) | 1993-05-07 | 1994-04-12 | Plastic encapsulated integrated circuit package and method of manufacturing the same |
KR1019950704702A KR960702178A (en) | 1993-05-07 | 1995-04-12 | Integrated circuit package encapsulated in plastic and manufacturing method (PALSTIC ENCAPSULATED INTEGRATED CIRCUIT PACKAGE AND METHOD OF MANUFACTURING THE SAME) |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/058,424 US5296743A (en) | 1993-05-07 | 1993-05-07 | Plastic encapsulated integrated circuit package and method of manufacturing the same |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/171,713 Division US5437095A (en) | 1993-05-07 | 1993-12-21 | Method of making plastic encapsulated integrated circuit package |
Publications (1)
Publication Number | Publication Date |
---|---|
US5296743A true US5296743A (en) | 1994-03-22 |
Family
ID=22016730
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/058,424 Expired - Lifetime US5296743A (en) | 1993-05-07 | 1993-05-07 | Plastic encapsulated integrated circuit package and method of manufacturing the same |
US08/171,713 Expired - Lifetime US5437095A (en) | 1993-05-07 | 1993-12-21 | Method of making plastic encapsulated integrated circuit package |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/171,713 Expired - Lifetime US5437095A (en) | 1993-05-07 | 1993-12-21 | Method of making plastic encapsulated integrated circuit package |
Country Status (5)
Country | Link |
---|---|
US (2) | US5296743A (en) |
EP (1) | EP0698291A1 (en) |
JP (1) | JPH08510092A (en) |
KR (1) | KR960702178A (en) |
WO (1) | WO1994027320A1 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6031281A (en) * | 1997-11-21 | 2000-02-29 | Samsung Electronics Co., Ltd. | Semiconductor integrated circuit device having dummy bonding wires |
US6297078B1 (en) * | 1997-12-31 | 2001-10-02 | Intel Corporation | Integrated circuit package with bond wires at the corners of an integrated circuit |
US6737739B2 (en) * | 1999-11-01 | 2004-05-18 | Chartered Semiconductor Manufacturing Ltd. | Method of vacuum packaging a semiconductor device assembly |
US20050012224A1 (en) * | 2003-06-09 | 2005-01-20 | Hideki Yuzawa | Semiconductor device, semiconductor module, electronic device and electronic equipment, and method for manufacturing semiconductor module |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5628031A (en) * | 1993-07-19 | 1997-05-06 | Elonex Ip Holdings Ltd. | Personal digital assistant module implemented as a low-profile printed circuit assembly having a rigid substrate wherein IC devices are mounted within openings wholly between opposite plane surfaces of the rigid substrate |
KR19990025704A (en) * | 1997-09-13 | 1999-04-06 | 윤종용 | LOC package and manufacturing method |
JP3019821B2 (en) * | 1997-10-22 | 2000-03-13 | 日本電気株式会社 | Semiconductor device |
US6434726B1 (en) | 1999-06-29 | 2002-08-13 | Lucent Technologies Inc. | System and method of transmission using coplanar bond wires |
DE19955649C2 (en) | 1999-11-19 | 2002-01-10 | Bosch Gmbh Robert | Electronic engine control of an internal combustion engine |
JP2009049072A (en) * | 2007-08-15 | 2009-03-05 | Panasonic Corp | Lead frame, semiconductor apparatus, method for manufacturing lead frame and semiconductor apparatus |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5126823A (en) * | 1990-03-06 | 1992-06-30 | Kabushiki Kaisha Toshiba | Lead frame having at least two islands and resin molded semiconductor device using it |
US5155578A (en) * | 1991-04-26 | 1992-10-13 | Texas Instruments Incorporated | Bond wire configuration and injection mold for minimum wire sweep in plastic IC packages |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5775434A (en) * | 1980-10-28 | 1982-05-12 | Nec Corp | Resin sealing metal mold for semiconductor device |
JPS5789230A (en) * | 1980-11-25 | 1982-06-03 | Hitachi Ltd | Semiconductor device |
US4556896A (en) * | 1982-08-30 | 1985-12-03 | International Rectifier Corporation | Lead frame structure |
EP0257681A3 (en) * | 1986-08-27 | 1990-02-07 | STMicroelectronics S.r.l. | Method for manufacturing plastic encapsulated semiconductor devices and devices obtained thereby |
JPH01170034A (en) * | 1987-12-25 | 1989-07-05 | Hitachi Ltd | Lead frame and semiconductor device |
JPH01315149A (en) * | 1988-08-05 | 1989-12-20 | Hitachi Ltd | Manufacture of semiconductor device |
JP2505569B2 (en) * | 1988-10-20 | 1996-06-12 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
US5197183A (en) * | 1991-11-05 | 1993-03-30 | Lsi Logic Corporation | Modified lead frame for reducing wire wash in transfer molding of IC packages |
-
1993
- 1993-05-07 US US08/058,424 patent/US5296743A/en not_active Expired - Lifetime
- 1993-12-21 US US08/171,713 patent/US5437095A/en not_active Expired - Lifetime
-
1994
- 1994-04-12 JP JP6525430A patent/JPH08510092A/en active Pending
- 1994-04-12 EP EP94914128A patent/EP0698291A1/en not_active Withdrawn
- 1994-04-12 WO PCT/US1994/004009 patent/WO1994027320A1/en not_active Application Discontinuation
-
1995
- 1995-04-12 KR KR1019950704702A patent/KR960702178A/en not_active Application Discontinuation
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5126823A (en) * | 1990-03-06 | 1992-06-30 | Kabushiki Kaisha Toshiba | Lead frame having at least two islands and resin molded semiconductor device using it |
US5155578A (en) * | 1991-04-26 | 1992-10-13 | Texas Instruments Incorporated | Bond wire configuration and injection mold for minimum wire sweep in plastic IC packages |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6031281A (en) * | 1997-11-21 | 2000-02-29 | Samsung Electronics Co., Ltd. | Semiconductor integrated circuit device having dummy bonding wires |
US6297078B1 (en) * | 1997-12-31 | 2001-10-02 | Intel Corporation | Integrated circuit package with bond wires at the corners of an integrated circuit |
US6420651B1 (en) | 1997-12-31 | 2002-07-16 | Intel Corporation | Integrated circuit package with bond wires at the corners of an integrated circuit |
US6737739B2 (en) * | 1999-11-01 | 2004-05-18 | Chartered Semiconductor Manufacturing Ltd. | Method of vacuum packaging a semiconductor device assembly |
US20050012224A1 (en) * | 2003-06-09 | 2005-01-20 | Hideki Yuzawa | Semiconductor device, semiconductor module, electronic device and electronic equipment, and method for manufacturing semiconductor module |
Also Published As
Publication number | Publication date |
---|---|
KR960702178A (en) | 1996-03-28 |
WO1994027320A1 (en) | 1994-11-24 |
US5437095A (en) | 1995-08-01 |
EP0698291A1 (en) | 1996-02-28 |
JPH08510092A (en) | 1996-10-22 |
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