CN1206325A - 印刷线路板 - Google Patents

印刷线路板 Download PDF

Info

Publication number
CN1206325A
CN1206325A CN98102735A CN98102735A CN1206325A CN 1206325 A CN1206325 A CN 1206325A CN 98102735 A CN98102735 A CN 98102735A CN 98102735 A CN98102735 A CN 98102735A CN 1206325 A CN1206325 A CN 1206325A
Authority
CN
China
Prior art keywords
outboard flanges
flange
printed substrate
size
medial flange
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN98102735A
Other languages
English (en)
Other versions
CN1193651C (zh
Inventor
滝上耕太郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujifilm Corp
Original Assignee
Fuji Photo Film Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Photo Film Co Ltd filed Critical Fuji Photo Film Co Ltd
Publication of CN1206325A publication Critical patent/CN1206325A/zh
Application granted granted Critical
Publication of CN1193651C publication Critical patent/CN1193651C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/111Pads for surface mounting, e.g. lay-out
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452Solder masks
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09218Conductive traces
    • H05K2201/09227Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09372Pads and lands
    • H05K2201/0939Curved pads, e.g. semi-circular or elliptical pads or lands
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09372Pads and lands
    • H05K2201/094Array of pads or lands differing from one another, e.g. in size, pitch, thickness; Using different connections on the pads
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09818Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/099Coating over pads, e.g. solder resist partly over pads
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10734Ball grid array [BGA]; Bump grid array
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3436Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

印刷线路板适于安装端子间距是0.5mm左右的CSP等有多列球状端子且端子间距窄的部件,外侧凸缘的列方向尺寸D2小于0.15mm,且比内侧凸缘的列方向尺寸D1小,内侧凸缘引出的布线从外侧凸缘间通过,把外侧凸缘的形状作成与列方向相垂直方向的尺寸D3比列方向的尺寸D2大的椭圆形,提高由温度循环等影响的锡焊部分的可靠性,把内外各个凸缘和布线的连接部分形成落泪状,能防止因热冲击或温度循环引起细的布线的切断。

Description

印刷线路板
本发明涉及印刷线路板,特别是适于安装以窄的间距设有多列球状端子的部件的印刷线路板。
已知IC(集成电路部件)的端子形状有针状(也称为引线状)和球状(也称为凸块状)。有针状端子列的IC被称为PGA(pin GridArray)。而具有球状端子列的IC被称为BGA(Ball Grid Array)。
BGA与PGA相比,由于有下述原因,因而适干高密度实际安装。
1,能使IC的端子间距较窄。因此,即使端子数多也能使IC小型化。
2,在印刷线路板的凸缘(ラン ド)不必开设IC的端子穿通用的孔。因此能使凸缘本身小型化。而且能将凸缘的间距减小。
图8表示把BGA安装在印刷线路板上的状态。在BGA上有球状端子列61。因此在印刷线路板70上与球状端子列相对应地形成凸缘列71。用焊锡80将各个球状端子61与凸缘71相连接。
端子间距为0.8mm以下的BGA被称为CSP。CSP是芯片尺寸封装(Chip Size Package)的略语,它的含义是来自端子间距是0.8mm以下的BGA、其封装尺寸接近内部集成电路小片的尺寸。
但是,由于下述原因,把端子间距是0.5mm左右、而且有内外2列端子列的CSP实际安装到印刷线路板上在技术上是困难的。
(1)考察图9所示的印刷线路板70。在这印刷线路板70上、以0.5mm的凸缘间距形成一列圆形的内侧凸缘72、一列圆形的外侧凸缘73。而且将布线74从内侧凸缘72引出并在外侧凸缘73之间通过。
(2)以前,内侧凸缘72和外侧凸缘73的直径是相同的,是0.4mm。
(3)如果把布线74的宽度取成一般使用的150μm,则由于外侧凸缘73之间的间隙变成0.5-0.4=0.1mm(100μm),因而布线74不能从外侧凸缘73之间通过。
(4)即使把布线74的宽度取成所谓实用的最小尺寸50μm,由于布线74和邻接的外侧凸缘73之间的间隙只是标准值(100-50)/2=25μm,因此布线74在外侧凸缘73之间通过是很勉强的。
另一方面,考虑过这样的方案,即不将布线74从外侧凸缘73之间通过,在内侧凸缘72围着的区域75里形成通孔,由此将布线74引出。但是,由于在CSP的场合下,区域75极窄,而且布线74的根数又多,因而必需把通孔做成极小。这样,用通常的多层基片的技术不能实现,又使印刷线路板的造价变成极高,因此是不实用的。
本发明是为了解决上述现有技术存在的问题而作出的,其目的是提供一种能适于安装端子间距是0.5mm左右的CSP等有多列球状端子而且端子间距窄的部件的印刷线路板。
为了达到上述目的,本发明采取以下技术方案:
所述发明的印刷线路板,它是用来搭载内外有多列球状端子的部件的,其特征在于:设有内外多列与上述球状端子对应的凸缘,从内侧凸缘引出的布线在外侧凸缘之间通过,外侧凸缘的列方向的尺寸比内侧凸缘的列方向的尺寸小。
所述发明的印刷线路板,其特征在于:外侧凸缘的与列方向相垂直方向的尺寸比外侧凸缘的列方向的尺寸大。
所述发明的印刷线路板,其特征在于:外侧凸缘的列方向的尺寸是0.15mm以下,内侧凸缘的凸缘间距是0.5mm以下、而且外侧凸缘的凸缘间距也是0.5mm以下。
所述发明的印刷线路板,其特征在于:外侧凸缘和从这外侧凸缘引出的布线的连接部分是将宽度渐渐加宽地将布线与外侧凸缘相连接,而且、内侧凸缘和从这内侧凸缘引出的布线的连接部分也是将宽度渐渐加宽地将布线与内侧凸缘相连接。
所述发明的印刷线路板,其特征在于:沿着外侧凸缘的全周、从外侧凸缘的外部侧到这外侧凸缘上的内部侧地涂敷保护膜,而且、沿着内侧凸缘的全周、从内侧凸缘的外部侧到这内侧凸缘上的内部侧地涂敷保护膜。
本发明的效果:
若采用所述的印刷线路板,由于外侧凸缘的列方向的尺寸比内侧凸缘的列方向的尺寸小,因而从内侧凸缘引出的布线就能在外侧凸缘之间顺利地通过。因此,能制得这样的印刷线路板,即、它适于安装CSP等具有多列球状端子,而且端子间距在0.5mm以下的极狭窄的部件。
若采用所述发明的印刷线路板,由于与列方向相垂直方向的外侧凸缘的尺寸比外侧凸缘的列方向的尺寸大,因而能使焊锡量增多。这样,能防止因温度循环等引起的锡焊部分的破损,能确保可靠性。
若采用所述发明的印刷线路板,由于外侧凸缘的列方向的尺寸是0.15mm以下,内侧凸缘和外侧凸缘之间的凸缘间距是0.5mm以下,因而能安装有多列球状端子而且端子间距是0.5mm以下的CSP等部件。
若采用所述发明的印刷线路板,由于外侧凸缘和从这外侧凸缘引出的布线的连接部分、以及内侧凸缘和从这内侧凸缘引出的布线的连接部分都是将宽度渐渐加宽地将布线与凸缘相连接,因而这些连接部分都形成所谓落泪状,即使受到锡焊时的热冲击、温度循环等作用,连接部分上的布线也难切断。因此能使布线更细。
若采用所述发明的印刷线路板,由于保护膜沿着外侧凸缘的全周、从外侧凸缘的外部侧到这外侧凸缘上的内部侧地覆盖,而且、保护膜沿着内侧凸缘的全周、从内侧凸缘的外部侧到这内侧凸缘上的内部侧地覆盖,因而保护膜增强了内外各个凸缘和布线的连接部分。因此,即使使布线变细也难切断。又因为通过涂敷保护膜使各个凸缘的露出部之间的间隙加大,所以难发生焊锡桥接。
以下参照附图,详细说明本发明的实施例:
图1是表示本发明实施方式的印刷线路板的基本结构的顶视图。
图2是表示本发明实施方式的印刷线路板的另一种结构的顶视图。
图3是表示本发明实施方式的印刷线路板的再一种结构的顶视图。
图4是表示本发明实施方式的印刷线路板的再一种结构的顶视图。
图5是沿图4中的Ⅴ-Ⅴ线取得的断面图。
图6是表示本发明实施方式的印刷线路板的再一种结构的顶视图。
图7是沿图6中的Ⅶ-Ⅶ线取得的断面图。
图8是表示把BGA装在印刷线路板上的样子的侧视图。
图9是现有技术的印刷线路板的顶视图。
下面,参照着图1~图7来说明本发明的实施方式的印刷线路板。
图1表示印刷线路板的基本结构。图1所示的印刷线路板10是用来安装CSP的。在这个实例中,CSP具有内外2列端子间距为0.5mm的球状端子。在印刷线路板10上、以凸缘间距P=0.5mm形成1列内侧凸缘1和1列外侧凸缘2。而且形成布线4。布线4是从内侧凸缘1引出、从外侧凸缘2之间通过。外侧凸缘2的顺着列方向的尺寸D2比内侧凸缘的顺着列方向的尺寸D1小。由此,外侧凸缘2之间的间隙L21就比内侧凸缘1之间的间隙L11大。这样,布线4就能在外侧凸缘2的较大间隙上通过。
结果,即使在凸缘间距P是0.5mm以下的印刷线路板中,也能将布线4从内侧凸缘1引出并在外侧凸缘2之间通过。因此,能制得这样的印刷线路板,即、它适于安装CSP等具有多列球状端子而且端子间距在0.5mm以下的极狭窄的部件。
下面举1个尺寸和形状的具体实例。在图1所示的印刷线路板10上,把内侧凸缘1制成直径为0.4mm的圆形凸缘,把外侧凸缘2制成直径为0.15mm的圆形凸缘,把布线4的幅度W制成0.15mm。在这种场合下,外侧凸缘2的列方向的尺寸D2是0.15mm,内侧凸缘1的列方向的尺寸D1是0.4mm。布线4和外侧凸缘2间的间隙就为0.1mm。
图2表示印刷线路板的另一种结构的实例。图2所示的印刷线路板20与图1所示的印刷线路板10相比较,除了将外侧凸缘的形状从圆形变成椭圆形之外,其他都是相同的。也就是说,在图2所示的印刷线路板20上,外侧凸缘3是椭圆形,与列方向成直角方向的尺寸D3比列方向的尺寸D2大。因此,即使外侧凸缘3的列方向的尺寸D2比以前的小,由于尺寸D3较大,因而能充分确保连接外侧凸缘3和CSP的球形端子锡焊部分的可靠性。
也就是说,在圆形外侧凸缘2的场合下(参照图1),当它的直径为0.15mm以下时,焊锡量就减少。因此,在受到温度循环升高等作用时,容易因印刷线路板和IC的膨胀系数之差而引起锡焊部分破损等。所以,注意到与列方向垂直的方向上、外侧凸缘的尺寸几乎没限制,并如图2所示地使外侧凸缘3的尺寸D3增大。这样,就能增加焊锡量,也可由此提高锡焊部分的可靠性。
也就是说,如果D3>D2,则即使凸缘间距是0.5mm以下,也能确保极高的可靠性,同时能将外侧凸缘的列方向的尺寸D2取成0.15mm以下。因此,能制得这样的印刷线路板,即、它适于安装CSP等具有多列球状端子,而且端子间距在0.5mm以下的极狭窄的部件。
下面列举一个在D3>D2的场合下的尺寸和形状的具体实例。在图2所示的印刷线路板20上,把凸缘间距P制成0.5mm,把内侧凸缘1制成直径为0.4mm的圆形凸缘,把外侧凸缘3制成宽度是0.15mm、长度是0.4~1.0mm的椭圆形凸缘,把布线4的宽度W制成0.15mm。在这种场合下,外侧凸缘3的列方向的尺寸D2是0.15mm,与列方向相垂直方向的尺寸D3是0.4~1.0mm,内侧凸缘1列方向的尺寸D1是0.4mm。布线4和外侧凸缘3之间的间隙是0.1mm。
图3表示印刷线路板的另一种结构的实例。图3所示的印刷线路板30与图2所示的印刷线路板20相比较,除了改变布线与凸缘的连接形状和使布线宽度变细之外,其他都是相同的。即、在内侧凸缘1和布线4的连接部分5上,使布线4的宽度渐渐加宽地将布线4与内侧凸缘1相连接。在外侧凸缘3和从这外侧凸缘3引出的布线6的连接部分7上,也是使布线6的宽度渐渐加宽地将布线6与外侧凸缘3相连接。而且,各条布线4、6都比图2的布线4细。这样,由于各个连接部分5、7都形成所谓落泪状(テイァドロツプ形),因而各条布线4、6即使较细,也难切断。
也就是说,由于从内外各凸缘1、3到ICT(在线测试)的凸缘等的布线宽度极细,在没对连接部分5、7的形状下功夫进行改进的场合下,就有各条布线4、6因受到锡焊时的热冲击或其他温度循环等作用,在与凸缘1、3的连接部分上被切断的问题。但是,如图3所示地、当把连接部分5、7形成落泪状时,由于各条布线4、6是渐渐将宽度加宽而且平滑地与凸缘1、3相连,因而就难切断。
下面举1个尺寸和形状的具体实例。在图3所示的印刷线路板30上,把凸缘间距P制成0.5mm,把内侧凸缘1制成直径为0.4mm的圆形凸缘,把外侧凸缘3制成宽度是0.15mm、长度是0.4~1.0mm的椭圆形凸缘,把布线4、6的宽度W制成50μm。在这种场合下,外侧凸缘3的列方向的尺寸D2是0.15mm,与列方向相垂直方向的尺寸D3是0.4~1.0mm,内侧凸缘1的列方向的尺寸D1是0.4mm。布线4和外侧凸缘3之间的间隙是0.15mm。
图4和图5表示印刷线路板的另一种结构的实例。图4和图5所示的印刷线路板40与图3所示的印刷线路板30相比较,除了涂敷保护膜8之外,其他都是相同的。在这印刷线路板40上,与通常的保护膜涂敷手法相同地完全避开各个凸缘1、3、把保护膜8涂敷在含有布线4、6的印刷线路板上。
图6和图7表示印刷线路板的另一种结构的实例。图6和图7所示的印刷线路板50与图4和图5所示的印刷线路板40相比较,除了保护膜8的涂敷范围不同之外,其他都是相同的。即、把保护膜8沿着外侧凸缘3的全周,从外侧凸缘3的外部侧直到这外侧接合部3上的内部侧地加以涂敷。而且、把保护膜8沿着内侧凸缘1的全周、从内侧凸缘1的外部侧直到这内侧接合部1上的内部侧地加以涂敷。不在内外凸缘1、3的中央部分1A、3A上涂敷保护膜8、使它们分别露出。由此,用保护膜8把各个凸缘1、3和布线4、6的连接部分5、7完全覆盖。因此布线4、6就更难被切断。又因为除了中央部分之外、各个凸缘1、3的全周都用保护膜8覆盖,所以内侧凸缘1的露出部分1A之间的间隙L12比内侧凸缘1之间的间隙L11大,而且、外侧凸缘3的露出部分3A之间的间隙L22也比外侧凸缘3之间的间隙L21大。因此就难发生焊锡桥接(半田ブリツジ)。

Claims (5)

1.印刷线路板,它是用来搭载内外有多列球状端子的部件的,其特征在于:
设有内外多列与上述球状端子对应的凸缘;
从内侧凸缘引出的布线在外侧凸缘之间通过,外侧凸缘的列方向的尺寸比内侧凸缘的列方向的尺寸小。
2.如权利要求1所述的印刷线路板,其特征在于:
外侧凸缘的与列方向相垂直方向的尺寸比外侧凸缘的列方向的尺寸大。
3.如权利要求2所述的印刷线路板,其特征在于:
外侧凸缘的列方向的尺寸是0.15mm以下;
内侧凸缘的凸缘间距是0.5mm以下;
而且外侧凸缘的凸缘间距是0.5mm以下。
4.如权利要求1或2或3所述的印刷线路板,其特征在于:
外侧凸缘和从这外侧凸缘引出的布线的连接部分是将宽度渐渐加宽,将布线与外侧凸缘相连接;而且,内侧凸缘和从这内侧凸缘引出的布线的连接部分也是将宽度渐渐加宽地将布线与内侧凸缘相连接。
5.如权利要求4所述的印刷线路板,其特征在于:
沿着外侧凸缘的全周,从外侧凸缘的外部侧到这外侧凸缘上的内侧地涂敷保护膜,而且,沿着内侧凸缘的全周、从内侧凸缘的外部侧到这内侧凸缘上的内侧地涂敷保护膜。
CNB981027350A 1997-06-30 1998-06-25 印刷线路板 Expired - Fee Related CN1193651C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP173489/1997 1997-06-30
JP173489/97 1997-06-30
JP9173489A JPH1126919A (ja) 1997-06-30 1997-06-30 プリント配線板

Publications (2)

Publication Number Publication Date
CN1206325A true CN1206325A (zh) 1999-01-27
CN1193651C CN1193651C (zh) 2005-03-16

Family

ID=15961463

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB981027350A Expired - Fee Related CN1193651C (zh) 1997-06-30 1998-06-25 印刷线路板

Country Status (3)

Country Link
US (1) US6218630B1 (zh)
JP (1) JPH1126919A (zh)
CN (1) CN1193651C (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI399146B (zh) * 2007-08-13 2013-06-11 Broadcom Corp 一種印刷電路板及其製作方法和球柵陣列焊盤圖案
CN112752398A (zh) * 2020-11-24 2021-05-04 广州朗国电子科技有限公司 一种pcb板的芯片焊盘结构

Families Citing this family (57)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000315843A (ja) * 1999-04-30 2000-11-14 Fujitsu Ltd プリント基板及び半導体装置
JP2001068836A (ja) * 1999-08-27 2001-03-16 Mitsubishi Electric Corp プリント配線基板及び半導体モジュール並びに半導体モジュールの製造方法
WO2001022488A1 (fr) * 1999-09-22 2001-03-29 Suzuka Fuji Xerox Co., Ltd. Composant electronique a reseau en grille, procede de renfort de ses conducteurs et son procede de fabrication
EP1098555B1 (en) * 1999-11-02 2008-07-23 Canon Kabushiki Kaisha Printed-wiring board
KR100817646B1 (ko) 2000-03-10 2008-03-27 스태츠 칩팩, 엘티디. 플립칩 상호연결 구조물
US10388626B2 (en) * 2000-03-10 2019-08-20 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming flipchip interconnect structure
US6527162B2 (en) * 2000-08-04 2003-03-04 Denso Corporation Connecting method and connecting structure of printed circuit boards
US6815621B2 (en) 2000-10-02 2004-11-09 Samsung Electronics Co., Ltd. Chip scale package, printed circuit board, and method of designing a printed circuit board
WO2002076329A1 (en) * 2001-03-26 2002-10-03 Glidewell James R Back casting prefabricated incisal veneers
JP4790157B2 (ja) * 2001-06-07 2011-10-12 ルネサスエレクトロニクス株式会社 半導体装置
KR100416000B1 (ko) * 2001-07-11 2004-01-24 삼성전자주식회사 다수의 핀을 갖는 부품이 실장되는 인쇄회로기판
TW533555B (en) * 2001-11-21 2003-05-21 Siliconware Precision Industries Co Ltd Substrate for passive device
GB2384119B (en) * 2002-01-10 2006-03-01 Nec Technologies A printed circuit board
JP2004040056A (ja) * 2002-07-08 2004-02-05 Shinko Electric Ind Co Ltd 配線パターンの構造及びバンプの形成方法
US7098408B1 (en) * 2003-10-14 2006-08-29 Cisco Technology, Inc. Techniques for mounting an area array package to a circuit board using an improved pad layout
US7023075B2 (en) * 2003-11-06 2006-04-04 Crydom Technologies Teardrop shaped lead frames
US8853001B2 (en) 2003-11-08 2014-10-07 Stats Chippac, Ltd. Semiconductor device and method of forming pad layout for flipchip semiconductor die
US7034391B2 (en) * 2003-11-08 2006-04-25 Chippac, Inc. Flip chip interconnection pad layout
US20070105277A1 (en) 2004-11-10 2007-05-10 Stats Chippac Ltd. Solder joint flip chip interconnection
US8350384B2 (en) * 2009-11-24 2013-01-08 Stats Chippac, Ltd. Semiconductor device and method of forming electrical interconnect with stress relief void
US7659633B2 (en) 2004-11-10 2010-02-09 Stats Chippac, Ltd. Solder joint flip chip interconnection having relief structure
TWI534915B (zh) 2003-11-10 2016-05-21 恰巴克有限公司 引線上凸塊之倒裝晶片互連
USRE47600E1 (en) 2003-11-10 2019-09-10 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming electrical interconnect with stress relief void
US8216930B2 (en) 2006-12-14 2012-07-10 Stats Chippac, Ltd. Solder joint flip chip interconnection having relief structure
US9029196B2 (en) 2003-11-10 2015-05-12 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US8026128B2 (en) 2004-11-10 2011-09-27 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US8076232B2 (en) 2008-04-03 2011-12-13 Stats Chippac, Ltd. Semiconductor device and method of forming composite bump-on-lead interconnection
US8574959B2 (en) * 2003-11-10 2013-11-05 Stats Chippac, Ltd. Semiconductor device and method of forming bump-on-lead interconnection
US8129841B2 (en) * 2006-12-14 2012-03-06 Stats Chippac, Ltd. Solder joint flip chip interconnection
USRE44500E1 (en) 2003-11-10 2013-09-17 Stats Chippac, Ltd. Semiconductor device and method of forming composite bump-on-lead interconnection
US8841779B2 (en) 2005-03-25 2014-09-23 Stats Chippac, Ltd. Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate
KR20070107154A (ko) 2005-03-25 2007-11-06 스태츠 칩팩, 엘티디. 기판상에 좁은 상호접속 사이트를 갖는 플립 칩 상호접속체
US9258904B2 (en) * 2005-05-16 2016-02-09 Stats Chippac, Ltd. Semiconductor device and method of forming narrow interconnect sites on substrate with elongated mask openings
US20060255473A1 (en) * 2005-05-16 2006-11-16 Stats Chippac Ltd. Flip chip interconnect solder mask
JP2007067019A (ja) * 2005-08-29 2007-03-15 Kyocera Corp 回路基板、電子機器、及び回路基板の製造方法
JP4211828B2 (ja) * 2006-09-12 2009-01-21 株式会社日立製作所 実装構造体
US9847309B2 (en) 2006-09-22 2017-12-19 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming vertical interconnect structure between semiconductor die and substrate
US7713782B2 (en) * 2006-09-22 2010-05-11 Stats Chippac, Inc. Fusible I/O interconnection systems and methods for flip-chip packaging involving substrate-mounted stud-bumps
US20080182398A1 (en) * 2007-01-30 2008-07-31 Carpenter Burton J Varied Solder Mask Opening Diameters Within a Ball Grid Array Substrate
JP2008187074A (ja) * 2007-01-31 2008-08-14 Nitto Denko Corp 配線回路基板およびその製造方法
US8349721B2 (en) 2008-03-19 2013-01-08 Stats Chippac, Ltd. Semiconductor device and method of forming insulating layer on conductive traces for electrical isolation in fine pitch bonding
US9345148B2 (en) 2008-03-25 2016-05-17 Stats Chippac, Ltd. Semiconductor device and method of forming flipchip interconnection structure with bump on partial pad
US7759137B2 (en) * 2008-03-25 2010-07-20 Stats Chippac, Ltd. Flip chip interconnection structure with bump on partial pad and method thereof
US20090250814A1 (en) * 2008-04-03 2009-10-08 Stats Chippac, Ltd. Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method Thereof
JP4770884B2 (ja) * 2008-06-26 2011-09-14 住友金属鉱山株式会社 Cof基板及びその製造方法
US7897502B2 (en) * 2008-09-10 2011-03-01 Stats Chippac, Ltd. Method of forming vertically offset bond on trace interconnects on recessed and raised bond fingers
US8659172B2 (en) * 2008-12-31 2014-02-25 Stats Chippac, Ltd. Semiconductor device and method of confining conductive bump material with solder mask patch
US8198186B2 (en) 2008-12-31 2012-06-12 Stats Chippac, Ltd. Semiconductor device and method of confining conductive bump material during reflow with solder mask patch
US20100237500A1 (en) * 2009-03-20 2010-09-23 Stats Chippac, Ltd. Semiconductor Substrate and Method of Forming Conformal Solder Wet-Enhancement Layer on Bump-on-Lead Site
US8039384B2 (en) 2010-03-09 2011-10-18 Stats Chippac, Ltd. Semiconductor device and method of forming vertically offset bond on trace interconnects on different height traces
US8409978B2 (en) 2010-06-24 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of forming vertically offset bond on trace interconnect structure on leadframe
US8492197B2 (en) 2010-08-17 2013-07-23 Stats Chippac, Ltd. Semiconductor device and method of forming vertically offset conductive pillars over first substrate aligned to vertically offset BOT interconnect sites formed over second substrate
US8435834B2 (en) 2010-09-13 2013-05-07 Stats Chippac, Ltd. Semiconductor device and method of forming bond-on-lead interconnection for mounting semiconductor die in FO-WLCSP
JP2015056228A (ja) * 2013-09-10 2015-03-23 株式会社小糸製作所 プリント基板および車両用灯具
JP6916453B2 (ja) * 2017-04-21 2021-08-11 日亜化学工業株式会社 光源装置
JP2020061406A (ja) * 2018-10-05 2020-04-16 株式会社村田製作所 半導体装置
CN111885815A (zh) * 2020-08-20 2020-11-03 苏州浪潮智能科技有限公司 一种pcb板及其适用于窄中心距bga芯片的焊盘结构

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4600970A (en) * 1984-05-29 1986-07-15 Rca Corporation Leadless chip carriers having self-aligning mounting pads
US5285352A (en) * 1992-07-15 1994-02-08 Motorola, Inc. Pad array semiconductor device with thermal conductor and process for making the same
DE69523010T2 (de) * 1994-10-04 2002-07-04 Nec Corp Mittels automatischer Bandmontage hergestelltes Halbleitergehäuse
US5547740A (en) * 1995-03-23 1996-08-20 Delco Electronics Corporation Solderable contacts for flip chip integrated circuit devices
US5585162A (en) * 1995-06-16 1996-12-17 Minnesota Mining And Manufacturing Company Ground plane routing
KR100192766B1 (ko) * 1995-07-05 1999-06-15 황인길 솔더볼을 입출력 단자로 사용하는 볼그리드 어레이 반도체 패키지의 솔더볼 평탄화 방법 및 그 기판구조
JP2894254B2 (ja) * 1995-09-20 1999-05-24 ソニー株式会社 半導体パッケージの製造方法
US5982186A (en) * 1995-09-28 1999-11-09 Texas Instruments Incorporated Contactor for test applications including membrane carrier having contacts for an integrated circuit and pins connecting contacts to test board
US5906042A (en) * 1995-10-04 1999-05-25 Prolinx Labs Corporation Method and structure to interconnect traces of two conductive layers in a printed circuit board
JP3458036B2 (ja) * 1996-03-05 2003-10-20 メック株式会社 銅および銅合金のマイクロエッチング剤
JP3351706B2 (ja) * 1997-05-14 2002-12-03 株式会社東芝 半導体装置およびその製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI399146B (zh) * 2007-08-13 2013-06-11 Broadcom Corp 一種印刷電路板及其製作方法和球柵陣列焊盤圖案
CN112752398A (zh) * 2020-11-24 2021-05-04 广州朗国电子科技有限公司 一种pcb板的芯片焊盘结构

Also Published As

Publication number Publication date
US6218630B1 (en) 2001-04-17
CN1193651C (zh) 2005-03-16
JPH1126919A (ja) 1999-01-29

Similar Documents

Publication Publication Date Title
CN1193651C (zh) 印刷线路板
US6864586B2 (en) Padless high density circuit board
US7396753B2 (en) Semiconductor package substrate having bonding pads with plated layer thereon and process of manufacturing the same
JP3294740B2 (ja) 半導体装置
US20050253231A1 (en) Semiconductor package with encapsulated passive component
US7199478B2 (en) Printed circuit board having an improved land structure
US20120164854A1 (en) Packaging substrate and method of fabricating the same
CN1214459C (zh) 半导体器件的载体衬底的电极结构
CN1099131C (zh) 栅阵列球半导体封装
US6054757A (en) Semiconductor apparatus, circuit board and combination thereof
JP6109078B2 (ja) リードクラックが強化された電子素子用テープ
KR20040083192A (ko) 솔더 볼 패키지
KR0146063B1 (ko) 반도체 패키지 및 그 제조방법
US7918668B1 (en) Socket connector assembly with conductive posts
US6734546B2 (en) Micro grid array semiconductor die package
KR100233864B1 (ko) 리드프레임을 이용한 에어리어 어레이 범프드 반도체 패키지의 입출력 범프 형성방법
KR100349561B1 (ko) Lsi 패키지 및 그 인너리드 배선방법
US20050270755A1 (en) Method for preventing pins of semiconductor package from short circuit during soldering
KR100790993B1 (ko) 범프 구조체를 구비한 플립 칩 패키지 및 그 제조방법
KR100348322B1 (ko) 반도체 패키지 제조용 회로기판 구조
KR100196992B1 (ko) 리드 프레임 및 이를 구비한 칩 스케일 패키지
KR19980039676A (ko) 실장이 용이한 바텀 리드 패키지형 칩 스케일 패키지의 구조
KR20030005565A (ko) 반도체 패키지용 인쇄회로기판의 제조방법
KR100348320B1 (ko) 반도체 제조용 회로기판의 구조
CN117678082A (zh) 光电半导体部件及制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: FUJI PHOTO FILM CO., LTD.

Free format text: FORMER OWNER: FUJIFILM HOLDINGS CORP.

Effective date: 20070420

C41 Transfer of patent application or patent right or utility model
C56 Change in the name or address of the patentee

Owner name: FUJIFILM HOLDINGS CORP.

Free format text: FORMER NAME OR ADDRESS: FUJI PHOTO FILM CO., LTD.

CP01 Change in the name or title of a patent holder

Address after: Tokyo, Japan

Patentee after: Fujifilm Corp.

Address before: Saitama Prefecture, Japan

Patentee before: Fuji Photo Film Co.,Ltd.

TR01 Transfer of patent right

Effective date of registration: 20070420

Address after: Tokyo, Japan

Patentee after: FUJIFILM Corp.

Address before: Tokyo, Japan

Patentee before: Fujifilm Corp.

C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20050316

Termination date: 20100625