CN1199283C - 绝缘栅晶体管 - Google Patents

绝缘栅晶体管 Download PDF

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CN1199283C
CN1199283C CNB001019988A CN00101998A CN1199283C CN 1199283 C CN1199283 C CN 1199283C CN B001019988 A CNB001019988 A CN B001019988A CN 00101998 A CN00101998 A CN 00101998A CN 1199283 C CN1199283 C CN 1199283C
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内海智之
大关正一
须田晃一
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Hitachi Ltd
Hitachi Power Semiconductor Device Ltd
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Hitachi Haramachi Electronics Ltd
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Abstract

绝缘门控晶体管包括第一半导体区、包括多个部分的第二半导体区、第三半导体区、第四半导体区、第一主电极和第二主电极，其中在第一主表面平面上经由绝缘层设置金属布线层，通过上述的主电极设置与第一主电极绝缘的多个区域，以及金属布线层通过绝缘层经由与主电极绝缘的区域与控制电极电连接。

Description

绝缘栅晶体管
技术领域
本发明涉及绝缘栅晶体管，特别是涉及在避免晶体管的闩锁现象或电流聚集方面有优势的绝缘栅晶体管。
背景技术
目前，具有快速操作和低导通电阻的绝缘栅双极晶体管(在下文简称为IGBT)被用作功率开关器件。IGBT具有一种结构，在结构中：在n型半导体衬底主表面的起漂移作用的一侧上形成从主表面延伸到其内部的P型基区和从基区延伸到其内部的n型发射区；在半导体衬底主表面的另一侧上形成与基区分开的P型集电区；发射极装在发射区和基区上；以及集电极装在集电区上。IGBT具有下列特点。在把使集电极具有比发射极正的电位的电压施加于集电极，并且把正电压施加于栅极时，在发射区中的电子通过沟道和漂移区到达集电区。到达集电区的电子从集电区增加正空穴的注入。因此，具有高电阻的漂移区被电导调制成低电阻区，并且在结构大致与MOSFET一样的情况下获得比使集电区变成不具有注入正空穴功能的n型漏区的MOSFET低的导通电阻。
在通过把IGBT和其他电路元件聚集获得IC时，为了便于电极之间连接，最理想的是在半导体衬底的同一表面上设置发射极、集电极和栅极的横向结构。例如在JP-A-5-29614(1933)中公开这种结构。
另一方面，根据IGBT，能够通过由一对集电极-发射极组成的元件的电流受到限制。所以，通过使大量的元件IGBT在半导体衬底内集成化获得最理想的电流量。
在JP-A-5-29614(1993)中公开的IGBT具有发射区、基区和集电区分别为梳状的结构而且发射区和基区的相应的齿状部分与集成区互相啮合。在基区、基区附近的漂移区和发射区上经由绝缘薄膜设置栅极。在相应的发射区和基区上分别设置发射极和集电极。发射极和集电极分别为梳状，并且发射极和集电极的齿状部分互相啮合。
按常规，用多晶硅作栅极材料。然而，根据具有通常结构的横向IGBT，由于栅极的纵向电阻造成栅电阻的不均匀性并且在关断操作中在具有大的栅电阻的部分上使关断动作延迟。
变换器件的大部分负载通常是电感负载。因此，在那个时候，除了维持大电流流动的操作外在电感延迟关断动作的部分上产生电流聚集。结果，在那部分上发生闩锁现象。因此，就有IGBT能控制的电流被限制在低于规定值的强度的问题。
为了在元件中减少操作时间的延迟，在JP-A-10-173176(1998)等等中公开了减小栅极电阻的技术。然而，该技术涉及纵向IGBT的结构，并且没有考虑为构成集成电路而使IGBT和驱动电路集成化的主意。
发明内容
本发明的目的是通过减小栅极电阻而提供具有改进闩锁防止性能的绝缘栅晶体管。
为了达到上述的目的，本发明的一方面，提供一种绝缘栅晶体管，包括：第一导电类型的第一半导体区，具有主表面平面；第二导电类型的第二半导体区，包括从所述主表面平面延伸到所述第一半导体区内形成的多个部分，所述多个部分分别包括条状形状，所述多个部分在长度方向上对直并平行设置；第二导电类型的第三半导体区，包括从所述主表面平面延伸到所述第一半导体区内形成的多个部分；第一导电类型的第四半导体区，沿所述第二半导体区的长度方向，从所述主表面平面延伸到在所述第二半导体区中所述多个部分的每个部分而形成；第一绝缘层，在所述主表面平面上形成，横跨所述第一、第二和第四半导体区；控制电极，由多晶硅半导体构成，通过所述第一绝缘层横跨所述第一、第二和第四半导体区形成；第一主电极，与所述第二和第四半导体区电连接；和第二主电极，在所述主表面上与所述第三半导体区电连接；和第二绝缘层，在所述主表面上形成，横跨所述第一绝缘层、第一主电极和第二主电极，其中，在所述主表面平面上的第二绝缘层上形成有金属布线层，设在所述第一主电极之上，且在其长度方向的两端和中部区域穿过所述第二和第一绝缘层与所述控制电极电连接。
为了达到上述的目的，本发明的又一方面，提供一种半导体器件，包括：绝缘栅晶体管阵列，和驱动电路，用于驱动所述绝缘栅晶体管阵列中排列的至少一个绝缘栅晶体管，其中所述绝缘栅晶体管包括：第一导电类型的衬底，具有主表面平面；第二导电类型的基区和集电区，从所述主表面平面延伸到所述衬底内，所述基区和集电区沿规定的方向纵向延伸且相对于所述规定方向的横向相间隔；第一导电类型的发射区，从所述主表面平面延伸到所述基区内；第一绝缘层，在所述主表面平面上形成，横跨所述基区、集电区和发射区；栅极，设在所述第一绝缘层上横跨所述基区和发射区；发射极，沿所述规定的方向配置，与所述基区和发射区电连接；集电极，沿所述规定的方向配置，与所述集电区电连接；和第二绝缘层，在所述主表面上形成，横跨所述发射极、所述集电极和所述第一绝缘层，其中，在所述主表面平面上的第二绝缘层上形成有金属栅极线，设在所述发射极之上，且在长度方向的两端和中部区域穿过所述第二和第一绝缘层与所述栅极电连接。
附图说明
图1是本发明实施例中的横向绝缘栅双极晶体管的示意部分平面图，
图2是沿图1中的A-A′线切取的横截面图，
图3是沿图1中的B-B′线切取的横截面图，
图4是本发明另一实施例中的横向绝缘栅双极晶体管的示意部分平面图，和
图5是本发明另一实施例中的纵向绝缘栅双极晶体管的示意横截面图。
具体实施方式
在下文，参考图1、图2和图3说明本发明实施例的详细情况。
图1是本发明实施例中的横向绝缘栅双极晶体管的示意部分平面图，而图2是沿图1中的A-A′线切取的横截面面图。根据图2，标号1表示包括靠近主表面平面2的n导电类型漂移区3(第一半导体区)的半导体衬底；从主表面平面2延伸到漂移区3并且互相分离地形成含有比漂移区3高的杂质浓度的P导电类型基区4(第二半导体区)和P导电类型集电区5(第三半导体区)；以及从主表面平面2延伸到基区4含有比基区4高的杂质浓度的n导电类型发射区6(第四半导体区)。
如图1所示，相应的基区4和集电区5具有条状结构，而这些区域在长度方向上对直并且在与长度方向垂直的方向上交替地设置。发射区6具有条状形状，并且二个发射区在基区4中以其长度方向沿基区4的长度方向延伸的方向排列。由图1中的实线表示的发射极(第一主电极)具有梳状形状；在主表面平面2上沿基区4设置其齿状部分7a，并且与发射区6和基区4电连接。集电极8(第二主电极)具有梳状形状(由图1中的实线表示)；在主表面平面2上沿集电区5设置其齿部状部分8a，并且与集电区5电连接。在基区4以及在基区4相近的两侧上相应的漂移区3和发射区6之上分别在主表面平面2上经由栅绝缘薄膜10以其长度方向沿基区4的长度方向排列的方向配置具有条状结构的多晶硅栅极9、9a(控制电极)。栅极9与相邻的栅极9a在三个部位上，即其长度方向中的二个末端和中部上，用多晶硅电连接。标号11表示在部分基区、栅极和漂移区上形成的第一绝缘薄膜，如图2所示。相应的发射极7中的齿状部分7a和集电极8中的齿状部分8a在第一绝缘薄膜11上延伸抵达漂移区3。标号12表示在集电极8、发射极7和第一绝缘薄膜11上面形成的第二绝缘薄膜。在第二绝缘薄膜12上沿发射极7用例如铝-硅形成具有梳状形状的栅线13。栅线13与在三个部位(长度方向中的二个末端和中部)上形成的栅极9、9a中的连接部位9b处的多晶硅电连接。图3表示沿图1中的B-B′线切取的，也就是栅线13的齿状部分13a与栅极9、9a中的连接部分9b的接触部分的横截面图。栅极9、9a中的连接部分9b通过切开部分的发射电极7、第一绝缘薄膜11和第二绝缘薄膜12经由铝-硅层14与栅线13接触。
根据本发明的结构，通过沿栅极9的长度方向设置栅极9、9a中的朝栅线13的多个连接部分9b，能够减小在长度方向上的栅极电阻，以便在关断状态时使电流经由最近的连接点通到铝-硅线。在平行地连接元件IGBT中的多个零件时，栅线13能够容易地连接相邻的多个元件IGBT。使全部IGBT的栅电阻能够均匀。结果，在关断操作时使元件IGBT的操作时间和全部IGBT的操作时间能够一致。所以，能够避免电流聚集，从而改进闩锁防止性能。
根据本实施例，在晶体管的主表面平面上能够实现减小栅电阻。因此，因为IGBT和用于驱动IGBT的驱动电路在同一表面平面上能够与各绝缘衬底、SOI衬底或各由PN结隔离的元件连接，所以能够容易地构成IC。
图4是本发明另一实施例的横向绝缘栅双极晶体管的示意平面图。根据图4，为了减小栅极9和9a在长度方向上的电阻在三点位置，即各栅极9和9a的二个末端和中部位置上设置与栅线的连接点。在长度方向上减小栅电阻的重点是在多晶硅栅极上在长度方向上设置多个连接点，并且是使相应的连接点与低电阻线例如铝-硅线电连接。
图5是本发明实施例的纵向绝缘栅双极晶体管的示意平面图。集电区5从主表面2延伸到部分漂移区3，正好在基区4和发射区6下面。相应的区域和电极的操作与图2所示的横向绝缘栅双极晶管一样。就纵向绝缘栅双极晶体管来说，能够获得与横向绝缘栅双极晶体管同样的优点。
根据本发明，不仅能够减小横向绝缘栅双极晶体管的栅电阻而且也能够减小纵向绝缘栅双极晶体管的栅电阻。因此，能够在元件中在关断操作时使操作时间一致，并且能够改进闩锁防止性能。
对于像MOSFET(金属-氧化物-半导体场效应晶体管)之类的横向绝缘栅晶体管和纵向绝缘栅晶体管都可以应用本发明。在绝缘栅晶体管中，图2和图5中的集电区5具有与绝缘栅双极晶体管中的导电类型相反的n导电类型。根据本发明，减小栅电阻并且使元件中关断操作一致。所以，防止电流聚集或者电流堵塞。另外，本发明应用于实施例中的P导电类型和n导电类型变换到n和P导电类型，也就是分别为相反的导电类型的绝缘栅晶体管。在这种情况中同样减小栅电阻。

Claims (13)

1.一种绝缘栅晶体管，包括：
第一导电类型的第一半导体区，具有主表面平面；
第二导电类型的第二半导体区，包括从所述主表面平面延伸到所述第一半导体区内形成的多个部分，所述多个部分分别包括条状形状，所述多个部分在长度方向上对直并平行设置；
第二导电类型的第三半导体区，包括从所述主表面平面延伸到所述第一半导体区内形成的多个部分；
第一导电类型的第四半导体区，沿所述第二半导体区的长度方向，从所述主表面平面延伸到在所述第二半导体区中所述多个部分的每个部分而形成；
第一绝缘层，在所述主表面平面上形成，横跨所述第一、第二和第四半导体区；
控制电极，由多晶硅半导体构成，通过所述第一绝缘层横跨所述第一、第二和第四半导体区形成；
第一主电极，与所述第二和第四半导体区电连接；和
第二主电极，在所述主表面上与所述第三半导体区电连接；和
第二绝缘层，在所述主表面上形成，横跨所述第一绝缘层、第一主电极和第二主电极，
其中，在所述主表面平面上的第二绝缘层上形成有金属布线层，设在所述第一主电极之上，且在其长度方向的两端和中部区域穿过所述第二和第一绝缘层与所述控制电极电连接。
2.如权利要求1所述的绝缘栅晶体管，其中：
所述第二半导体区的多个区域按长度方向配置在第一主电极之下。
3.如权利要求1所述的绝缘栅晶体管，其中：
所述绝缘栅晶体管是横向型绝缘栅双极晶体管。
4.如权利要求1所述的绝缘栅晶体管，其中：
所述金属布线层通过在所述两端和中部区域设置的所述绝缘层的接触孔与所述控制电极电连接。
5.如权利要求1所述的绝缘栅晶体管，其中：所述金属布线层是金属栅线。
6.如权利要求5所述的绝缘栅晶体管，其中：
所述第一导电类型为n型，所述第二导电类型为p型。
7.如权利要求5所述的绝缘栅晶体管，其中：
所述第一半导体区是衬底的n型漂移区，所述第二半导体区是p型基区，所述第三半导体区是p型集电区，所述第四半导体区是n型发射区。
8.如权利要求7所述的绝缘栅晶体管，其中：第一主电极至少部分在所述控制电极之上延伸，并由所述第一绝缘层相分离。
9.如权利要求5所述的绝缘栅晶体管，其中：第一主电极至少部分在所述控制电极之上延伸，并由所述第一绝缘层相分离。
10.一种半导体器件，包括：
绝缘栅晶体管阵列，和
驱动电路，用于驱动所述绝缘栅晶体管阵列中排列的至少一个绝缘栅晶体管，其中所述绝缘栅晶体管包括：
第一导电类型的衬底，具有主表面平面；
第二导电类型的基区和集电区，从所述主表面平面延伸到所述衬底内，所述基区和集电区沿规定的方向纵向延伸且相对于所述规定方向的横向相间隔；
第一导电类型的发射区，从所述主表面平面延伸到所述基区内；
第一绝缘层，在所述主表面平面上形成，横跨所述基区、集电区和发射区；
栅极，设在所述第一绝缘层上横跨所述基区和发射区；
发射极，沿所述规定的方向配置，与所述基区和发射区电连接；
集电极，沿所述规定的方向配置，与所述集电区电连接；和
第二绝缘层，在所述主表面上形成，横跨所述发射极、所述集电极和所述第一绝缘层，
其中，在所述主表面平面上的第二绝缘层上形成有金属栅极线，
设在所述发射极之上，且在长度方向的两端和中部区域穿过所述第二和第一绝缘层与所述栅极电连接。
11.如权利要求10所述半导体器件，其中：
所述第一导电类型为n型，所述第二导电类型为p型。
12.如权利要求10所述半导体器件，其中：
所述发射极至少部分在所述栅极之上延伸，并由所述第一绝缘层相分离。
13.如权利要求10所述半导体器件，其中：
所述金属栅极线是与所述栅极的两端和中部电连接的铝硅层，以减小所述栅极在所述规定方向的电阻。
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