CN1197156C - 半导体设备 - Google Patents
半导体设备 Download PDFInfo
- Publication number
- CN1197156C CN1197156C CNB011357762A CN01135776A CN1197156C CN 1197156 C CN1197156 C CN 1197156C CN B011357762 A CNB011357762 A CN B011357762A CN 01135776 A CN01135776 A CN 01135776A CN 1197156 C CN1197156 C CN 1197156C
- Authority
- CN
- China
- Prior art keywords
- semiconductor chip
- pad
- pressure pad
- metal wire
- stacked
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 393
- 239000002184 metal Substances 0.000 claims abstract description 118
- 229910052751 metal Inorganic materials 0.000 claims abstract description 118
- 239000000463 material Substances 0.000 claims abstract description 45
- 230000002093 peripheral effect Effects 0.000 claims description 15
- 239000008393 encapsulating agent Substances 0.000 claims description 10
- 238000009958 sewing Methods 0.000 claims description 10
- 238000005096 rolling process Methods 0.000 claims description 2
- 238000007789 sealing Methods 0.000 abstract description 92
- 239000011347 resin Substances 0.000 abstract description 80
- 229920005989 resin Polymers 0.000 abstract description 80
- 239000003566 sealing material Substances 0.000 abstract 1
- 238000003466 welding Methods 0.000 description 74
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 33
- 239000010931 gold Substances 0.000 description 33
- 229910052737 gold Inorganic materials 0.000 description 33
- 238000000034 method Methods 0.000 description 26
- 238000004519 manufacturing process Methods 0.000 description 16
- 230000008901 benefit Effects 0.000 description 13
- 238000005538 encapsulation Methods 0.000 description 12
- 239000000725 suspension Substances 0.000 description 11
- 230000008569 process Effects 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000012545 processing Methods 0.000 description 4
- 241000272168 Laridae Species 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 239000011230 binding agent Substances 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000001125 extrusion Methods 0.000 description 2
- 230000004927 fusion Effects 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000001143 conditioned effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 238000007373 indentation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000013532 laser treatment Methods 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- 239000003351 stiffener Substances 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 238000005303 weighing Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45015—Cross-sectional shape being circular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48095—Kinked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4945—Wire connectors having connecting portions of different types on the semiconductor or solid-state body, e.g. regular and reverse stitches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8512—Aligning
- H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8512—Aligning
- H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
- H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
- H01L2224/8518—Translational movements
- H01L2224/85191—Translational movements connecting first both on and outside the semiconductor or solid-state body, i.e. regular and reverse stitches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
- H01L2224/85205—Ultrasonic bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Credit Cards Or The Like (AREA)
Abstract
在一种半导体设备中,层叠半导体芯片由具有其上被安排焊盘的主面和背面的半导体芯片构成,将上层半导体芯片的背面固定到下层半导体芯片的主面上,呈阶梯状错位,使焊盘不重叠,层叠半导体芯片的背面被固定到提供压料垫沉埋的引导框架到压料垫一个面。在层叠半导体芯片上的焊盘和相应的内部引线被用反向金属线焊接通过金属线连接,内部引线,层叠半导体芯片,金属线,接合材料,和压料垫的五个主要的面被用密封材料覆盖,从密封材料的外部面露出压料垫的背面。
Description
技术领域
本发明涉及减小通过层叠半导体芯片构成的半导体设备的焊封厚度。
背景技术
在现有技术中,对于闪烁存储器卡,例如用作照相机Cam Corder,等的存储媒体的小型闪烁卡,采用TSOP(Thin Small OutlinePackage),它允许在卡中有相当大的空间,其标准类型的封装厚度尺寸最大是1.2mm。近来为了减小卡中的空间开发出了较小的闪烁卡,要求封装的厚度应该减小到大约标准TSOP的一半。也有增加容量的强烈要求。除了可通过单个半导体芯片获得较大的容量外,开发出了称为MCP(Multi Chip Package)的半导体设备,在其中将两个半导体芯片用密封剂焊封。
图11是在现有技术中的MCP剖面图,例如,被公开在日本专利申请出版物(KOHYO)平10-506226中,通过将两个半导体芯片粘贴到压料垫的两个面而构成,将该压料垫设在一片引导框架上,使这样的两个半导体芯片安装在上面。
将半导体芯片3通过接合材料2接合到该压料垫1的第一面(示于图11中的该压料垫1的上边),将半导体芯片5通过接合材料4接合到该压料垫1的第二面(示于图11中的该压料垫1的下边)。因此,在图11中,这样构成层叠半导体芯片(该半导体芯片有两个有效面),使得有效面3a和有效面5a分别将压料垫1和接合材料2,4放在预部面和底部面之间。
金丝6的一端被连到焊盘(未示出),通过球形焊接6c提供给有效面3a和5a。金丝6的其他端被连到内部引线7的一个面7a和内部引线7的另一面7b,以便移动缝合形焊接6d的位置。在现有技术中通常实施金属线焊接方法,其中球形焊接6c被加到半导体芯片3,5上所提供的焊盘上,缝合形焊接6d被加到内部引线7上,将此称为前向金属线焊接方法。
在图11中,金丝6的最高部分6a,6b被涂以尺寸为E的焊接树脂8以便密封和保护。从图11中所示的有效面3a向上延伸的金丝的最高部分6b的高度尺寸A的和E+A+B+A+E,层叠半导体芯片的厚度B(半导体芯片3,5,接合材料2,4和压料垫1之和),从有效面5a向下延伸的金丝的最高部分6b的高度尺寸A,和涂抹金丝6的最高部分的尺寸E给出了MCP的总厚度尺寸。
在以上现有技术所描述的半导体设备中,存在缺陷,因为层叠半导体芯片的厚度B由半导体芯片3,5,接合材料2,4和压料垫1之和给出,故该压料垫1的厚度增加了该两个面的半导体芯片的厚度。
在该前向金属线焊接方法中,也有缺陷,因为在球形焊接6c的位置和金丝的最高部分6a或6b之间的尺寸A和从球形焊接6c的位置到金丝的最高部分6a的尺寸C的和D=A+C给出从缝合形焊接位置到金丝的最高部分的高度尺寸,这样的尺寸A与以上的高度尺寸交迭,因此金丝被这样的尺寸延伸得更长。
另外,如果将前向金属线焊接应用到中心焊盘方案的半导体芯片上,其中将这些焊盘安排在该半导体芯片的有效面的中心,这有缺陷,因为金丝与层叠半导体芯片的外部外围接触,不可能将金属线焊接应用到这样的半导体芯片。
如果该半导体设备的厚度必须通过现有技术的结构减少到0.5mm,则有问题,对于两片接合材料的厚度为2×0.025mm,金属线环的高度A=0.15mm到0.18mm,和引导框架板的厚度0.125mm,则除非该层叠半导体芯片的厚度可被减少到小于0.025mm,金属线6就会从密封树脂8的外部面露出。
如果半导体芯片的厚度被减少到小于0.1mm,引起了要新克服的各种问题,例如,晶片的抛光变得困难的问题,当晶片在抛光以后被运送时产生故障的问题,当把晶光分成单独的芯片时出现故障的问题,当将分开的半导体芯片组装时出现故障的问题,等。因此,存在着在现有技术中大批生产设备不可能处理这些问题的问题。
而且,如果半导体设备的厚度是薄的,例如0.5mm,外部引线的高度被降低,例如0.25mm,当将板的厚度是0.125mm的外部引线从半导体设备的中心侧面抽出时,其高度几乎是半导体设备的厚度0.5mm的一半,如日本专利申请出版物(KOHYO)平10-506226中所述。因此,在此引起了问题,因为不可能充分地吸收在半导体设备被封装在封装基片上以后,由于环境温度的变化引起的热应变,焊接接合部分的可靠性容限被降低。
发明内容
因此,通过克服以上提到的现有技术中的缺陷,本发明提供一种半导体设备,其厚度是现有技术中半导体设备标准化厚度的一半。
本发明的一个目的是提供一种半导体设备,通过如阶梯似地层叠来构成层叠半导体芯片,能够缩短金属线的无用的和多余的传送路线并降低密封厚度,且金属线的环路高度并不增加半导体设备的厚度。
为了达到以上的目的,根据本发明,在此提供一种半导体设备,沉埋包括:
层叠半导体芯片,设置一个上层半导体芯片和一个下层半导体芯片,两者分别具有一个上面设有焊盘的主面和与一个与所述主面相对的背面,通过接合材料将所述上层半导体芯片的背面固定到所述下层半导体芯片的所述主面上,呈阶梯状错位,使所述焊盘不重叠,
内部引线,连续形成外部引线,
压料垫,连续形成压料垫沉埋了的压料垫悬挂引线,
接合材料,
金属线,
密封材料;
将所述层叠半导体芯片的背面用接合材料固定到所述压料垫的一个面上,将所述层叠半导体芯片的焊盘与对应的所述内部引线用所述金属线反向金属线焊接连接,将所述内部引线、所述层叠半导体芯片、所述金属线、所述接合材料、和压料垫的五个主要面用所述密封材料覆盖,使所述压料垫的背面露出在密封材料的外面,从所述密封材料的侧面伸出所述外部引线,所述压料垫断面露出在所述密封材料侧面,所述层叠半导体芯片背面通过接合材料被固定在所述压料垫板厚作薄的部分上,用所述金属线连接在所述层叠半导体芯片上设置的焊盘和对应的所述内部引线。
根据本发明,所述层叠半导体芯片被固定成,将所述上层半导体芯片在与半导体芯片平行的面中旋转180度,并且呈台阶状错位层叠,与所述下层半导体芯片的焊盘不重叠。
另外,,所述层叠半导体芯片由两个分别具有不同尺寸的半导体芯片构成,使在被载放的所述下层半导体芯片的所述主面上设置的焊盘在载放的所述上层半导体芯片的外围区域上露出。
进一步,所述层叠半导体芯片的背面被用接合材料固定到压料垫的板厚作薄的部分上。
而且,在所述内引线前端设有薄板轧制台阶。
所述金属线的一端被用球形焊接连到位于所述层叠半导体芯片的层叠厚度范围内的内部引线的一个面上,所述金属线的另一端被用缝合形焊接连到设置在所述层叠半导体芯片的所述上层半导体芯片主面上的焊盘上。
附图说明
图1是作为实施方案1的一种半导体设备的剖面图;
图2是作为实施方案1的半导体设备的一种剖面图,与图1正交地横断;
图3是省略密封树脂时,示出作为实施方案1的半导体设备的平面图;
图4是金属线的侧视图;
图5是示出作为实施方案1的半导体设备的另一种实施方案的剖面图;
图6是作为实施方案2的一种半导体设备的剖面图;
图7是省略密封树脂时,示出作为实施方案2的半导体设备的平面图;
图8是示出作为实施方案2的半导体设备的另一种实施方案的剖面图;
图9是作为实施方案3的一种半导体设备的剖面图;
图10是示出作为实施方案3的半导体设备的另一种实施方案的剖面图;
图11是用现有技术的一种半导体设备的剖面图。
具体实施方式
往后将参考附图解释实施方案。在这种情况下,在用作说明本发明的实施方案的各个附图中,通过对具有相同功能的部分标上相同符号将省略它们的多余的解释。
实施方案1
将参考所构成的一个半导体设备解释实施方案1,该半导体设备具有的密封厚度基本上是TSOP(Thin Small Outline Package)半导体设备的一半,在其中两个相同的半导体芯片被用密封树脂密封得到的密封厚度为1mm,并在两个方向中抽出外部引线。
图1是作为实施方案1的一个半导体设备的剖面图。图2是作为实施方案1的半导体设备的一个剖面图,与图1正交。图3是省略密封树脂时,示出作为实施方案1的半导体设备的平面图。图4是金属线的侧视图。
图1中所示的第一半导体芯片13的背面13b通过接合材料12固定在压料垫11的第一面11a上。第二半导体芯片15的背面15b通过接合材料14固定,像阶梯似地,层叠在第一半导体芯片13的有效面(主面)13a上,以便构成层叠半导体芯片。当如图3中所示,第二半导体芯片被层叠在第一半导体芯片13上时,使第二半导体芯片15被通过如阶梯似的移动L3固定,这样,被提供到第一半导体芯片13的主面13a上的焊盘并不与第二半导体芯片15重迭。在图3中,相互具有相同尺寸和相同功能并且其中焊盘被沿着外部外围一侧安排的两个半导体芯片13、15被按相同方向层叠,然后第二半导体芯片15在相同平面中相对于第一半导体芯片13旋转180度,然后在长边方向移动L3。
提供给图3中所示的半导体芯片13和15的焊盘10和20与内部引线17的第一面17a通过图4中所示的金属线16被相应地电气上连接,借助于前向金属线焊接方法和反向金属线焊接方法将球形焊接16c应用到内部引线17的一端,将缝合形焊接16d应用到金属线16的另一端。
在该实施方案1中,图4所示的金属线16被用所谓的反向金属线焊接方法连接,也就是,球形焊接16c被应用到安排在由图1中L4所指明的层叠半导体芯片侧面区域中的内部引线17(描绘在图1的右侧)的第一面17a,然后金属线16被弯曲,在从直线部分16e所连接的点垂直上升的位置上(环形高度A的部分)基本正交,然后水平方向延伸尺寸L5,接着缝合形焊接16d被应用到提供给第二半导体芯片15的主面15a的焊盘20(图3中所示)。
作为对照,金属线16被用所谓的前向金属线焊接方法连接,也就是球形焊接16c被应用到层叠半导体芯片的下层半导体芯片13上的焊盘10,然后将金属线16弯曲,在从上升的直线部分16e所连接的点垂直上升的位置上(环形高度AA部分)基本正交,然后水平延伸,接着缝合形焊接16d被加到在图1中左侧所示的内部引线17的第一面17a上。
根据反向金属线焊接方法,从第二半导体芯片15的主面15a到金属线16的最高部分的尺寸D可以减少到几乎达到金属线的直径。作为对照,根据前向金属线焊接方法,被应用到将第一半导体芯片13上的焊盘和内部引线17的第一面17a连接,从第二半导体芯片15的有效面15a向上突出的量可被减少,因为这样的方法是在第二半导体芯片15和接合材料14的和L4的范围内实施的。
如图1,2和3中所示,由内部引线17,第一和第二半导体芯片13,15,金属线16,接合材料12,14和压料垫11组成的所有主要的五个面(其中压料垫11的第一面11a和除第二面11b以外的四个在平面厚度方向中的侧面被称为主要的五个面)被用密封树脂18覆盖,使得外部引线19和用于支撑压料垫11的悬挂引线11d的四个压料垫被从密封边界侧的面突出。同时,压料垫11的一个面(图1中所示的背面11b)被从密封树脂18的外部面露出来。
在密封以后,通过切去在引导框架上连续组成的它们的系杆部分(未示出)和它们的顶部构成如鸥翼似的外部引线19。然后,在引导框架(未示出)上连续组成的悬挂引线11d的压料垫被在密封树脂18的外部外围侧面的边界部分上切除(在图2中密封树脂18的边界部分上所示的四个位置11e),从而可以完成在图1中所示的根据实施方案1的半导体设备。
接着,以下将解释一种制造方法。引导框架被准备好,在其中在图3中所示的两相对的边被分别用一对悬挂引线11d握持,内部引线17和外部引线19也在两个相对的外部外围侧上调成一致,与压料垫11和压料垫悬挂引线11d所在的边正交,利用隔离间隙相继组成。
这种引导框架可以与在TSOP半导体设备中所采用压料垫沉埋(图2中L6所示)被施加在其上的引导框架具有相同的结构。关于提供给引导框架的矩阵结构,通过孔的传送和提供给引导框架的孔的定位,密封树脂溢出保护系杆,等的解释将被省略。首先,第一半导体芯片13的后部面13b被接合材料12固定到压料垫11的第一面11a。然后,通过用接合材料14将第二半导体芯片15粘贴到第一半导体芯片13上,同时将第二半导体芯片15象阶梯似地移动尺寸L3,如图3中所示,使得当芯片15被层叠到第一半导体芯片13时,在半导体芯片13上的焊盘10并未被第二半导体芯片15覆盖,从而完成压料焊接的步骤。同时,可以完成层叠半导体芯片。
然后,内部引线17的顶端和相应的焊盘,如图4中所示,被利用在现有技术的金属线焊接中所采用的金丝,铜线,金属线(金属细线)16通过金属线焊接方法电气上连接。在前向金属线焊接和反向金属线焊接中,通过提供热能和化学能的焊接力和超声振动的融合/焊接方法的解释在此将被略去。
作为分级支撑的夹具和引线固定支架,采用现有技术中批量生产时所用的型架。分级支撑的夹具具有第一支撑面,用于支撑内部引线17的第二面17b,和为支撑压料垫11在第一支撑面中所提供的第二被压印的凹形平面。引线固定支架支撑内部引线17的第二面17b和悬挂引线11d的压料垫,和在内部引线17的第一面17a的顶部部分上有通孔,围绕球形焊接或缝合形焊接所应用的区域。
内部引线17的第二面17b被放在支撑支架的第一支撑面上,然后压料垫11的背面11b被放在第二被压印的凹形平面上,接着内部引线17和悬挂引线11d的压料垫被支撑夹具和引线固定支架夹在中间并被夹紧,同时将引线固定支架放在内部引线17的第一面17a上。
在此之后,金属线16被用反向金属线焊接方法电气连接,也就是,如图1中所示,金属线16的一端被通过在引线固定支架的通孔的入口区域中球形焊接16c连接到内部引线17的第一面17a,然后,上升的直线部分16e被与层叠半导体芯片的侧面平行抬起,缝合形焊接16d被应用到相应的焊盘20上。
然后,金属线16被通过前向金属线焊接方法电气连接,也就是,球形焊接16c被应用到第一半导体芯片13的主面13a的焊盘上,然后,直线部分16e被与第二半导体芯片15的侧面平行抬起(环形高度AA),接着缝合形焊接16d被应用到内部引线17的第一面17a的顶端部分。这样,可以完成金属线焊接步骤。
然后,内部引线17的第二面17b和压料垫11的背面11b被与下部的模子接触,上部模子被放在内部引线17的第一面17a上,然后上部模子和下部模子被夹紧,接着密封树脂18,例如,热成形的树脂,等,在高温下被融化,在高压下,被注入在上部模子和下部模子之间所提供的凹部。这样,由层叠半导体芯片组成的五个主要面,金丝16,和压料垫11被密封,从而可以完成密封步骤。在实施方案1中所采用的密封树脂18,并未被特别规定是否这样的材料是为半导体设备开发的。因为在密封步骤(融合步骤)中所采用的上部模子和下部模子并没有被从在现有技术的半导体设备制造步骤中所采用的加以改变,它们的解释将被省略。
如果采用其中有多个压料垫象一个单列的或多列的矩阵组成的引导框架,则多个半导体设备可通过外部引线19的顶端部分和悬挂引线11d的压料垫在引导框架部分(未示出)相继地被构成,然后多个半导体设备在后继的阶段中被分成单独的半导体设备,在划分的步骤中,外部引线19的顶端部分被通过切割装置,例如激光处理,机械加工,等与引导框架分离。
在用于成型被切割装置断开的象鸥翼似的外部引线的顶端部分的引线成型步骤被完成的阶段,压料垫悬挂引线11d被在引导框架部分上连续地构成。因此,在必要的组装步骤,例如打标记和其他等被执行以后,多个半导体设备最好通过从引导框架最终切除压料垫悬挂引线11d被分成小片,在图2中的密封树脂侧面的边界上按压料垫悬挂引线11d的剖面形状11e进行。这样,可以获得根据在图1到图3中所示的实施方案1的层叠半导体设备。
例1
将参考图5解释厚度为0.55mm的半导体设备。引导框架被准备好,其中内部引线17,压料垫11,压料垫悬挂引线,系杆,框架,分段带,等被类似于在TSOP封装中所采用的引导框架来构成并具有0.125mm的厚度。
压料垫11的平面部分11c被构成得比压料悬挂引线11d和内部引线17薄,通过将0.125mm的厚度减少0.075mm,使压料垫11的平面部分11c的厚度成为0.050±0.02mm。压料垫11的背面11b也在压料垫悬挂引线11d部分被弯曲,如图5所示,给出对于内部引线17的背面的水平差为L6=0.1mm(在此以后称为“压料垫沉埋”)。
作为半导体芯片,准备两个半导体存储器芯片13,15,其中焊盘10被安排成沿着靠近有效面的外部外围的一侧,具有厚度为145±10μm,并具有相同的尺寸和相同的功能。下部的半导体存储器芯片13被通过具有厚度为25μm的带状接合材料12固定所述金属线的一端被用球形焊接连到位于所述层叠半导体芯片的层叠厚度范围内的内部引线的一个面上,所述金属线的另一端被用缝合形焊接连到设置在所述层叠半导体芯片的所述上层半导体芯片主面上的焊盘上。
11的平面部分11c,然后上部半导体存储器芯片15(在例1的情况下,该芯片与半导体存储器芯片13是相同的)被通过具有厚度为25μm的接合材料14固定到下部半导体存储器芯片13的有效面13a。
在此时,上部半导体存储器芯片15被通过将上部半导体存储器芯片15相对于下部半导体存储器芯片13旋转180度并将上部半导体存储器芯片15在长边方向象阶梯似地移L3=1.0mm,固定在下部半导体存储器芯片13上,使得上部半导体存储器芯片15并不覆盖在下部半导体存储器芯片13上的焊盘10,从而可获得层叠的存储器芯片,其中图3所示的焊盘10和20被安排在两个相对的左和右侧。
因为在上部半导体存储器芯片15上的焊盘20被定位在高出内部引线17的相应的第一面17a L8=0.170mm,金丝16被通过反向金属线焊接在环形高度A=0.22mm处连到焊盘20。如果这么做了,金丝16的最高部分(环形高度A)从上部半导体存储器芯片15的有效面15a向上突出的尺寸可被设置到0.05mm。
作为对照,下部焊盘10被定位在低于上部焊盘20,低过上部半导体存储器芯片15本身的厚度和接合材料14的厚度之和,也就是0.01725±0.012mm,金属线16被通过前向金属线焊接连到焊盘10,得到环形高度AA=0.18±0.03mm。
根据以上的结构,从层叠半导体存储器芯片的上部主面到压料垫11的背面11b的尺寸成为0.395±0.044mm。在上部模子和下部模子之间的密封树脂注入空间(空腔)被设置到0.550mm,使得半导体设备的厚度成为0.550±0.025mm。然后,密封树脂18被注入空腔,同时使压料垫11的背面11b与下部模子的底部面接触,将层叠半导体存储器芯片密封。
然后,在划分步骤和外部引线形成步骤完成以后,制成TSOP层叠半导体芯片的非常薄的半导体设备可以得到。在这样的半导体设备中,如图5中所示,从密封树脂18的面到压料垫11露出的背面的厚度尺寸是0.550±0.025mm,从外部引线19到压料垫露出的面的密封树脂18的尺寸L7是0.1mm,从密封树脂18的面到外部引线19(图5中外部引线19的上面)的尺寸L6是0.325mm,外部引线19被从偏离半导体设备的密封树脂18的侧面中心的位置突出0.1125mm,L1大于0.325mm。
在例1中,用于覆盖层叠半导体存储器芯片的上部主面的密封树脂18的厚度尺寸是0.15mm(0.550-0.395=0.155)。从上部有效面到压料垫11的背面11b的尺寸是0.395mm。如果考虑大批生产中的生产误差±0.044mm,上部有效面可以用密封树脂18覆盖至少0.111mm(0.155-0.044=0.111mm)。从缝合形焊接位置(压料垫11的第一面11a)的金丝最高位置通过反向金属线焊接用密封树脂18可以覆盖0.1mm,如果考虑生产误差±0.044mm,它们可被用密封树脂18覆盖至少0.056mm。这样,可以保证足够的密封质量。
而且,在前向金属线焊接中的环形高度尺寸AA是0.180mm。金丝的最高部分可以用密封树脂18覆盖0.145mm,如果考虑生产误差±0.044mm,它们可被用密封树脂18覆盖至少0.056mm。因而,可以保证足够的密封质量。
根据以上的解释,因为压料垫11被从封装的外部面露出,从压料垫11的平面部分11c到密封树脂18的最上部面的尺寸L2可以设置得大,具有厚度为0.55mm的半导体设备可由两个半导体芯片组成,每个具有芯片厚度为0.1475±0.010mm,除非半导体芯片13,15的厚度被减至小于0.100mm,这是难以加工的。如果采用每个具有芯片厚度为0.147±0.010mm的半导体芯片,可通过现有的设备大批生产层叠半导体设备而不改变生产过程的条件,因而不需要新设备投资。
而且,因为通过组成压料垫沉埋提供的离内部引线安放面的水平差为L6=0.100mm,如果用密封树脂实行密封露出压料垫,弯曲的悬挂引线和内部引线17被用密封树脂覆盖,悬挂引线和外部引线被安排在偏离密封树脂侧面中心0.1125mm(在图5中它们被向下偏移0.1125mm)。当外部引线19被在与压料垫11的露出的后部面11b相反的方向中弯曲时,外部引线19的顶端被成型如鸥翼,外部引线19的封装高度L1可被延长超过0.1125mm,而不是外部引线19从密封树脂18的侧面中心突出的情况。
因为外部引线19的封装高度L1存在着L1的体积对于外部引线19的刚度对热形变的影响,取决于偏置的存在,刚度被改变3.6倍。即使根据例1的半导体设备在它被焊剂固定到封装基片以后经受到热应力,封装可靠性可得到改善,因为在焊剂接合部分中产生的热应变可被外部引线19的L1部分的形变吸收。
另外,通过层叠相同的半导体存储器芯片构成层叠半导体存储器芯片将半导体存储器的容量增加两倍是可能的。
此外,反向金属线焊接方法可以降低从层叠半导体存储器芯片的最上部的面到金丝的最高部分的高度D,并且也将误差总数压得少些。因而,如金丝从密封树脂18的面露出的故障可被减少,并且从层叠半导体存储器芯片的有效面到密封面的树脂厚度尺寸也可被减小。结果,半导体芯片的厚度可被减小得更多。
例2
以下将参考图1和图2解释例2,其中将现有技术的TSOP中厚度为1mm的密封树脂应用到具有厚度为0.625mm的半导体设备上。
在例2的层叠半导体设备中,采用引导框架,其中压料垫11和压料垫悬挂引线11e被连续地构成,并组成内部引线17提供0.1mm的压料垫散热,如图2中所示,且外部引线19,两者均具有平面厚度为0.125mm,被连续地构成。两个半导体存储器芯片,每个具有厚度为0.147mm,被层叠在图1中所示的压料垫11的第一面上,然后如阶梯似地由0.025mm的接合材料固定,然后在层叠半导体芯片上的焊盘和相应的内部引线17被金属线焊接,然后通过利用上部模子和下部模子应用树脂密封,上下模子被制成具有空腔尺寸为0.625mm。因此,可获得这样的半导体设备,其中L4为0.345mm,用于覆盖层叠半导体芯片的主面的树脂密封尺寸为0.1555mm,L2是0.500mm,如图1中所示,作为L2和压料垫厚度0.125mm之和的总厚度为0.625mm。
参考例1和例2解释根据实施方案1的层叠半导体设备。在这种设备中,外部引线17可被通过压料垫沉埋埋藏在密封树脂18中,因为采用具有压料垫沉埋的引导框架,通过将两个相同的半导体存储器芯片层叠,同时将一个芯片13的主面和另一芯片15的背面象阶梯似地推移,层叠半导体芯片的背面被固定到压料垫11的一个面,金属线16被分别通过反向金属线焊接方法和正向金属线焊接方法连接到层叠半导体芯片上的上部焊盘20和下部焊盘10,密封被实施,从密封树脂18的外部面露出压料垫11的背面11b。但以下所描述的应用可被采用。
在实施方案1中,解释了通过将上层半导体芯片15相对于下层半导体芯片13旋转180度,然后将上层半导体芯片15在一侧方向象阶梯似地移动构成的层叠半导体芯片。作为对照,当采用焊盘被安排成沿着半导体芯片主面的两个正交外部外围侧的半导体芯片时,层叠半导体芯片可通过将上层半导体芯片在相同平面上相对于下层半导体芯片旋转180度,然后将上层半导体芯片分别在两个正交方向象阶梯似地移动并不覆盖在半导体芯片上形成的焊盘而被构成。这样层叠半导体芯片可被应用到非常薄的半导体设备,其厚度是TQFP(薄四边形平面封装)半导体设备厚度1.4mm的一半,在其中外部引线被从密封树脂的四个外部侧面伸出。
在例1中,解释该非常薄的层叠半导体设备,其中通过采用具有深度为0.1mm的压料垫沉埋的0.125mm厚度的引导框架和将层叠半导体芯片安装面压印0.075mm以将压料垫的厚度减少到0.05mm,可以实现0.55mm的密封树脂厚度。作为对照,如果0.1mm厚度的引导框架被采用,压印深度被设置为0.045mm,可以构成完全与例1类似的具有厚度为0.55mm的非常薄的半导体设备。
在例2中,解释0.625mm厚度的非常薄的半导体设备,其中使成本增加的压料垫面加工被省略,具有在压料垫背面和内部引线背面之间的水平差0.1mm的0.125mm厚度的引导框架被采用,当厚度小于1mm的TSOP时,对于要求减少密封树脂的厚度到0.55mm来说,成本具有优先权的情况下进行以上考虑。作为对照,如果0.1mm厚度的引导框架被采用,可以构成具有0.6mm厚度的非常薄的半导体设备而不改变模子。
实施方案2
以下在这实施方案2中将解释一种通过利用层叠半导体芯片构成非常薄的半导体设备的方法,其中当利用两个相同的半导体存储器芯片组成这样的层叠半导体芯片时,上部半导体存储器芯片直接与下部半导体存储器芯片平行地推移如同阶梯,然后被固定。
图6是作为实施方案2的一种半导体设备的剖面图。图7是当略去图6中密封树脂时,示出作为实施方案2的半导体设备的平面图。图8是示出作为实施方案2的半导体设备的另一种实施方案的剖面图。在这种情况下,与在实施方案1中所解释的相同的制造过程的重达部分的多余解释以下将被略去。
如图6中所示,通过对在实施方案1所用的引导框架内部引线17的顶端部分的腐蚀或挤压加工构成水平差,提供对内部引线17的顶端部分的薄的平面17c。与实施方案1中所采用的引导框架的配置相同的在实施方案2中所采用的引导框架的配置的解释在此将被省略。
图6中所示的第一半导体芯片13的背面13b被通过接合材料12固定到压料垫11的平面部分11c。第二半导体芯片15的背面15b(具有与第一半导体芯片的背面相同的尺寸和相同的功能)被通过接合材料14固定到第一半导体芯片13的主面13a,就这样构成层叠半导体芯片。在此时,通过将上层半导体芯片15与下层半导体芯片13平行地从图7中所示的状态移动L3,被如阶梯似地固定,两个芯片被层叠使它们的焊盘放在相同的一侧(在图6中在左边的一侧上),并不覆盖由上部台阶上构成的第二半导体芯片15在下面台阶上构成的第一半导体芯片13上所提供的焊盘10。
然后,在第一和第二半导体芯片13,15上所提供的焊盘10,20分别被通过反向金属线焊接经金属线16连到内部引线17的薄平面17c和内部引线17的第一面17a。在图7中的左侧所示的内部引线17被通过球形焊接连接,在图7中的右侧所示的内部引线17是并不连接的无效引线。
金属线焊接被实施两次。在第一金属线焊接中,金属线16被通过球形焊接连到如图6中下顶部所示的内部引线17的薄平面17c,也通过缝合形焊接连到环形高度从上的下部焊盘10。当反向金属线焊接被应用到在层叠半导体芯片的下层半导体芯片13上的所有必要的焊盘10时,第一金属线焊接被完成。
然后,在第二金属线焊接中,球形焊接被应用到内部引线17的第一面17a,在此时,球形焊接被应用到这样的位置上,从在第一金属线焊接中球形焊接16c被应用的位置向密封树脂18的外部侧面移动。金属丝16被从焊接点在环形高度A上基本正交地弯曲,然后平行地延伸到上部焊盘20,并通过缝合形焊接16d连接到焊盘20,当反向金属线焊接被应用到所有必要的上部焊盘20时,第二金属线焊接被完全成。
当金属线焊接被完成时,通过利用密封树脂18将由内部引线17,第一和第二半导体芯片13,15,金属线16,接合材料12,14和除背面11b以外的压料垫11组成的所有主要的五个面覆盖完成密封,使得外部引线19被从密封树脂18的密封边界的侧面伸出,压料垫11的背面被从密封树脂18的外部面露出。当外部引线19在它们的顶端部分被切除以后成型时,可以获得在图7中所示的根据实施方案2的非常薄的半导体设备。
在实施方案2中,被球形焊接到相同的内部引线17并移动它们的位置的金丝16的一端被通过缝合形焊接连到低部的焊盘10和上部的焊盘20。金丝16被延伸的连线部分在图7的平面图中相互交叉。然而,如果从侧面观看交叉部分,图6中所示的空隙可被保证。即使金丝在这些交叉部分相互接触,短路问题并不发生,因为在实施方案2的层叠半导体芯片中金丝16相互在电气上具有相同的相位和相同的极性。
例1
以下将参考例1中的图6和图7解释一个例子,其中将根据实施方案2的层叠半导体设备被应用到0.55mm厚度的非常薄的半导体设备。0.125mm厚度的引导框架被预备,其中内部引线17,压料垫11,压料垫悬挂引线11d,系杆,框架,分段杆,和其他零件的构成与TSOP封装中所采用的引导框架类似。
通过压印,也就是腐蚀下层半导体芯片13被接合的区域,如图7中所示,其深度为0.075±0.025mm,在图6中所示的压料垫11的第一面11a上构成平面部分11c。压料垫11的两个相对的边(长边)分别通过一对压料垫悬挂引线11d被固定到引导框架的框架部分(未示出)。
内部引线17和外部引线19,它们被调节到具有隔离的空隙,被在两个相对边(短边)的外部外围侧上连续地构成,与压料垫11和压料垫悬挂引线11d被提供的边正交,并用引导框架的框架部分(未示出)固定。
在压料垫11的第一面11a和内部引线17的第一面17a之间提供水平差,在图6中所示L7=0.1mm,这种水平差是通过将压料垫悬挂引线11d部分弯曲作为0.1mm的压料垫沉埋构成的。
通过将它们除去深度为0.075mm,在引导框架的内部引线17的顶端部分上构成薄的平面17c。
厚度为0.1475mm的下部半导体存储器芯片13被通过0.025mm厚度的接合材料12固定到具有平面厚度为0.05mm的压料垫11的平面部分11c。然后,上层半导体芯片15的背面15b被层叠,并通过厚度为0.025mm的接合材料固定到下部半导体存储器芯片13的有效面13a。因而,在下层半导体芯片13上的焊盘10和上层半导体芯片15上的焊盘20被形成在层叠半导体芯片的外部外围的一侧,同时平行移动L3如阶梯一般。
因为层叠半导体芯片的上部焊盘20高出内部引线17的第一面17aL4=0.17mm,通过反向金属线焊接,在环形高度A=0.22mm的内部引线17的第一面17a侧实施第二球形焊接。
作为对照,因为下部焊盘10比内部引线17的薄的平面17c的位置高出0.0725mm,金属线16的环形高度尺寸A=0.18mm比上部半导体存储器芯片15的厚度0.1475mm和接合材料的厚度0.025mm之和0.1725mm高,第一金属线焊接也用反向金属线焊接实现。因此,如果从边上看,在平面图中,金属线焊接的金属线16相互交叉的延伸部分的点上可以保证空隙尺寸为0.085mm。
在图6中,因为从层叠半导体芯片的上部主面15a到压料垫11的背面11b的尺寸是0.395mm,上部模子和下部模子被夹紧得到密封树脂注入空间(空腔)为0.550mm,使得半导体设备的厚度为0.550mm。压料垫11的背面11b被与下部模子的底部面接触,然后密封树脂18被注入,从而完成密封步骤。然后,当划分步骤和外部引线形成步骤被完成时,可以获得非常薄的半导体设备,在其中构成TSOP两层层叠半导体芯片,从密封树脂18的前面到压料垫11被露出的背面具有厚度尺寸为0.550mm。
在例1中,因为用于覆盖层叠半导体芯片的上部有效面的密封树脂的厚度尺寸是0.155mm,从半导体芯片的有效面到压料垫11的背面11b的尺寸是0.395mm,考虑到在大批生产中的生产误差±0.044mm,层叠半导体芯片的有效面至少可用0.111mm厚度的密封树脂覆盖。而且,因为从主面15a到金丝16的最高部分的尺寸是0.04mm,金丝16的最高部分至少可用0.071mm厚度的密封树脂覆盖,因此可保证足够的质量。
而且,因为被通过反向金属线焊接连到下部的半导体芯片的所有金丝是在层叠半导体芯片的厚度尺寸范围内构成的,球形焊接的位置,缝合形焊接的位置,金丝的最高部分可用密封树脂18充分地覆盖。
例2
以下将参考例2解释作为根据实施方案2的层叠半导体设备,与现有技术中TS0P的密封树脂1.0mm厚度相对照,通过利用具有厚度为0.125mm的较廉价的引导框架构成具有厚度为0.625mm的半导体设备。
与实施方案重迭的解释在此将被略去。在例2的半导体设备中,在层叠半导体芯片上阶梯式的焊盘20,10和内部引线17的两个相应的顶端部分17a,17c被用反向金属线焊接在高度位置A=0.22mm和AA=0.15mm上连接,同时移动焊接位置,上层半导体芯片15的主面15a被在厚度方向移动,因为施加到压料垫11的第一面11a深度为0.075mm的压印加工被略去。与此相联系,在密封模子中的空腔尺寸被从0.075mm增加直到0.625mm。
以下将参考图8解释例2。如果每个具有厚度为0.147mm的两个半导体存储器芯片被用厚度为0.025mm的接合材料如阶梯式地层叠在0.125mm厚度的压料垫11上,可以获得这样的半导体设备,其中L4是0.345mm,从层叠半导体芯片的主面到密封树脂18的最外部面的尺寸是0.155mm,L2是0.5mm,总厚度是0.625(=0.500+0.125)mm。
在金属线延伸部分的交叉点上,图8中所示的金属线16之间的空隙成为0.04mm(=0.22-0.15-0.03),因此可以保证足够的间隙。
实施方案3
在实施方案3中,以下将解释一种半导体设备,其中层叠半导体芯片被通过层叠两个具有不同尺寸的半导体芯片构成水平差,使得上部的小半导体芯片被接合材料固定到下部大半导体芯片,没有覆盖在下层半导体芯片上的焊盘,这个层叠半导体芯片的背面被固定到压料垫。
在实施方案3中,将解释一种构成半导体设备的方法,其中TQFP半导体设备的密封树脂的厚度被基本上减至一半,其中从四个侧面伸出外部引线的密封树脂厚度被规格化为1.4mm。
图9是作为实施方案3的一种半导体设备的剖面图。图10是示出作为实施方案3的半导体设备另一种实施方案的剖面图。在这种情况下,相同制造过程中多余部分的解释在以下将被省略。
如图9所示,通过将引导框架的内部引线17的顶端部分腐蚀或挤压加工,作为在内部引线17的顶端部分上的薄平面17c构成水平差。如果半导体芯片被固定在其上的压料垫11的平面部分11c可被构成为薄的,在现有技术中的TQFP半导体设备所采用的引导框架可被用作压料垫11的第一面11a。在这种情况下,在现有技术中提供给TQFP的关于系杆,框架,分段杆,应力吸收槽,传送孔等的解释被略去。
如图9中所示,第一半导体芯片13的背面13b被接合材料12固定到压料垫11的平面部分11c。第二半导体芯片15的背面15b被接合材料14固定到第一半导体芯片13的主面13a,从而构成层叠半导体芯片。在此时,如图8中所示,第一和第二半导体芯片13,15被如阶梯似地固定,使得小尺寸的半导体芯片被作为上部的第二半导体芯片15层叠,如图8中所示,并不覆盖提供给下部第一半导体芯片13的焊盘10。
然后,提供在第一半导体芯片13上的焊盘10和提供在第二半导体芯片15上的焊盘20相应地和分别地用反向金属线焊接,经金属线16电气上连到内部引线17的薄平面17c和内部引线17的第一面17a。
金属线焊接被分别实施两次。在第一金属线焊接中,作为下顶部构成的内部引线17的薄平面17c被利用反向球形焊接在环形高度AA上经金属线16连到层叠半导体芯片中半导体芯片13的下部焊盘10。当反向金属线焊接被应用到层叠半导体芯片中下层半导体芯片13上的所有必要的焊盘10时,第一金属线焊接被完成。
然后,在第二金属线焊接中,球形焊接被应用到内部引线17的第一面17a。在此时,球形焊接被应用到从在第一金属线焊接中球形焊接16c所应用的位置向密封树脂18的外部面移动的位置。金属线16被在从焊接点的环形高度A上基本正交地弯曲,然后平行地延伸到上部焊盘20,并通过缝合形焊接16d连到焊盘20。当反向金属线焊接被应用到所有必要的上部焊盘20时,第二金属线焊接被完成。
当金属线焊接被完成时,通过将由内部引线17,第一和第二半导体芯片13,15,金属线16,接合材料12,14和除了背面11b外的压料垫组成的所有主要的五个面用密封树脂18覆盖完成密封,使得外部引线19被从密封树脂18的密封边界的侧面伸出和压料垫11的背面11b被从密封树脂18的外部面露出。当外部引线19在它们的连到引导框架的顶端部分被切除以后成型时,可获得图8中所示的半导体设备。
在根据实施方案3的半导体设备中,如果提供在半导体芯片上的焊盘数目与外部引线数目不同,金属线被球形焊接到一个内部引线顶端部分的两个不同的位置的情况和金属线被球形焊接到一个位置的情况是混合存在的。这些金属线被缝合形焊接到相应的下部焊盘10和相应的上部焊盘20。因为层叠半导体芯片是通过将具有不同尺寸和功能的半导体芯片象阶梯似地层叠构成的,具有相同极性和相同相位的金丝不可能始终相互相交。因此,在金丝之间的空气隙,如图8的剖面图中所示,必须以三自由度方式提供,务必使金属线的部分相交。
如实施方案1和实施方案2那样,在根据实施方案3的半导体设备中,层叠半导体芯片的厚度L4,压料垫的厚度,和从层叠半导体芯片的最上部面到密封树脂的外部面的尺寸之和是层叠半导体设备的厚度。
例1
在例1中,将解释根据实施方案3的层叠半导体设备被应用到厚度为0.55mm的半导体设备的一个例子,通过利用层叠半导体芯片来实现,其中10mm平方的外围焊盘方案半导体芯片和8mm平方的外围焊盘方案半导体芯片被层叠,使各个半导体芯片的中心点一致。
具有平面厚度为0.125mm的引导框架被准备着,然后在图9中所示的压料垫11的第一面11a区域的厚度通过腐蚀掉0.075mm被减少到0.05mm。压料垫11的四个角落部分被四个压料垫悬挂引线(未示出)固定到引导框架的框架部分。
内部引线17的顶端部分被调节并带着隔离间隙安排在压料垫11的外部外围侧,围绕着压料垫11。继续构成外部引线19和内部引线17并被固定到引导框架的框架部分。
通过将压料垫悬挂引线11d部分弯曲,构成压料垫沉埋,在压料垫11的第一面11a和内部引线17的第一面17a之间提供水平差,L7=0.1mm。
通过将顶端部分腐蚀,从内部引线17的第一面17a除去0.075mm的深度,在引导框架的内部引线17的顶端部分上形成薄平面17c。
0.1475mm厚度的下部和上部半导体存储器芯片13,15被用0.025mm厚度的接合材料12固定到压料垫11的平面部分11c,其中焊盘10,20分别被安排在靠近主面外部外围的一侧。当下部半导体存储器芯片13的主面13a被用0.025mm厚度的接合材料14固定到上层半导体芯片15的背面15b,使它们的中心点一致时,层叠半导体芯片被固定,同时与下层半导体芯片平行地移动上层半导体芯片15 L3=1mm,如同阶梯,因为在上层半导体芯片15和下层半导体芯片13之间的一侧中的差是2mm。
层叠半导体芯片的上部焊盘20和位于比焊盘20低L8=0.17mm的内部引线17的第一面17a被用第二反向金属线焊接连在环形高度A=0.22mm处。
作为对照,因为下部焊盘10比内部引线17的薄平面17c的位置高0.0475mm,通过在环形高度尺寸AA=0.15mm处用反向金属线焊接来实现第一金属线焊接。因为上层半导体芯片15的厚度0.1475mm和接合材料的厚度0.025mm之和是0.1725mm,可以保证在第一和第二焊接的金属线16之间的空隙为0.115mm。
在例1中,从层叠半导体芯片的上部有效面(主面)到压料垫11的背面11b的尺寸是0.395±0.044mm,作为L4=0.345±0.024mm和压料垫11的厚度0.05±0.02mm之和。因此,如果上部模子和下部模子被夹紧提供0.550mm的密封树脂注入空间(空腔),在压料垫11的背面11b与下部模子的底部面接触时,注入密封树脂18,可以获得这样的半导体设备,在其中构成TQFP两层层叠半导体芯片,从密封树脂18的上部面到压料垫11露出的背面11b的厚度尺寸为0.550mm。
在以上例1中所解释的半导体设备中,用于覆盖层叠半导体芯片上部主面的密封树脂18的厚度尺寸是0.155mm(0.550-0.395=0.155)。因为从层叠半导体芯片的有效面到压料垫11的背面11b的尺寸是0.395mm。层叠半导体芯片的有效面至少可用0.111mm厚度的密封树脂覆盖,考虑到大批生产中生产误差±0.044mm。
而且,因为从主面15a到金丝16的最高部分的尺寸是0.05mm,金丝16的最高部分至少可用0.061mm厚度的密封树脂覆盖,因此可以保证足够的质量。
而且,因为用反向金属线焊接连到层叠半导体芯片的下层半导体芯片13上的焊盘的所有球形焊接位置,缝合形焊接位置,和用于金丝的金丝最高部分被在层叠半导体芯片的厚度尺寸L4的范围内实现,这样的球形焊接位置,这样的缝合形焊接位置,和金丝的这样的最高部分可充分地被密封树脂18所覆盖。
例2
以下将参考例2解释层叠半导体设备,通过利用廉价的引导框架构成,具有的厚度基本上是现有技术中TQFT密封树脂的厚度1.4mm的一半,因为压料垫和内部引线顶端部分被构成为具有平面厚度为0.125mm。与例1中所解释的层叠半导体芯片相同的配置和相同的制造过程的解释将被略去。
在例2中,下层半导体芯片13的背面13b被用接合材料12固定到压料垫11的第一面11a。因此,0.075mm的压印加工并不需要,内部引线的顶端部分并不除去0.075mm。因为这个原因,如果在第一反向金属线焊接中的球形焊接在环形高度AA=0.15mm处被应用到内部引线17的第一面17a,在环形高度A=0.22mm处应用第二反向金属线焊接,当从侧面观看时,在交叉部分上的间隙尺寸成为0.04mm。
为了像例1那样保证间隙尺寸为0.115mm,在第二反向金属线焊接中的环形高度被设置为A=0.295mm。因此,在密封模子之间的空腔尺寸被增加到0.15mm以后,层叠半导体设备被密封,这样可获得具有密封树脂的厚度为0.7mm的层叠半导体设备。
在例2的层叠半导体设备中,具有平面厚度为0.7mm的压料垫和内部引线被利用上部密封模子和下部密封模子密封,其中空腔尺寸被构成为0.7mm,0.147mm厚度的半导体芯片被用两个0.025mm厚度的接合材料象阶梯似地层叠和固定到压料垫。因此,L4=0.345mm,从层叠半导体芯片的主面15a到密封树脂最外部面的尺寸是0.23mm,L2=0.575mm,层叠半导体设备的总厚度是0.7(=0.575±0.125)mm。
如果层叠半导体设备的背面被固定到提供压料垫沉埋的压料垫,然后金属线被通过反向金属线焊接方法焊接到层叠半导体设备的上部焊盘,则可以获得这样的半导体设备,其中压料垫被从密封树脂的外部面露出来,外部引线被用压料垫沉埋较深地埋入密封树脂,当层叠半导体设备被用密封树脂密封时,同时使压料垫的背面接触下部模子。
例2参考层叠半导体芯片进行解释,其中具有密封树脂厚度为1.4mm的两个TQFP被层叠在具有平面厚度为0.125mm的引导框架上。然而,在密封树脂的厚度没有限制和要求添加功能或增加容量具有优先权的情况下,在现有技术中不可能获得的具有薄密封厚度的半导体设备可以得到,如果层叠半导体芯片是通过将半导体芯片层叠到三层或多层构成的话。
本发明利用一片低价可得到的引导框架进行解释。但如果用于支撑层叠半导体芯片的压料垫部分被用压料垫框架独立地构成,与内部引导框架分离,虽然成本变得贵些,或者如果引导框架用层状的基片代替,这样可造得比引导框架更薄,或者如果引导框架被用带状基片代替,可以实现相同的优点。
如果当层叠半导体芯片被构成时需要接线的焊盘未被覆盖,并且在主面上的焊盘也都有象阶梯似地可被露出的不同水平面,半导体芯片并不限于半导体存储器芯片。因此,类似的优点可通过或者具有任何功能的半导体芯片,或者具有不同尺寸和相同尺寸的半导体芯片来实现。
因为构成层叠半导体芯片的上层半导体芯片上的焊盘被从层叠半导体芯片面露出,半导体芯片并不限于外围垫装置的半导体存储器芯片。因此,通过或者是中心焊盘装置的半导体芯片或者是焊盘在主面上被分开排列的半导体芯片来实现类似的优点。
如果,上层半导体芯片象阶梯似地移动并固定到下层半导体芯片,此后,上层半导体芯片在相同平面中相对于下层半导体芯片旋转180度,然后在两个正交方向中平行地移动,在构成层叠半导体芯片中露出下部焊盘,可以实现类似的优点。
如果上层半导体芯片象阶梯似地移动并固定到下层半导体芯片,此后,上层半导体芯片在两个正交方向中与下层半导体芯片平行地移动,在构成层叠半导体芯片中露出两个正交边上的下部焊盘,可以实现类似的优点。
如果尺寸小于其焊盘被安排在外围上的下层半导体芯片的上层半导体芯片被象阶梯似地移动并固定到下层半导体芯片,露出下部焊盘,在构成层叠半导体芯片中不管上部焊盘如何排列,甚至当上部和下层半导体芯片的中心点相互一致还是不一致时,可以实现类似的优点。
通过利用压料垫解释实施方案1,实施方案2,和实施方案3,其中具有压料垫沉埋的压料垫在尺寸上大于半导体芯片。在这种情况下,采用小的压料垫可以实现类似的优点,在其中具有压料垫沉埋的压料垫在尺寸上小于半导体芯片或者装框架的小压料垫,这种焊盘具有象框架似地构成的压料垫悬挂引线加强条。
因为本发明是如以上所述的那样构成的,可以实现以下给出的优点。
在本发明中,因为压料垫的一个面是从密封树脂的外部面露出的并且构成压料垫沉埋,外部引线可以伸出,偏离密封树脂侧面的中心。因此,可以实现这些优点,即,半导体设备密封树脂的厚度可被减小,设备对于封装以后热应变的寿命可被延伸得更长。
在TSOP半导体设备中也可以实现这些优点,即,半导体设备的厚度可被减小,设备对于封装以后热应变的寿命可被延伸得更长。
另外,在TQFP半导体设备中可以实现这些优点,即,半导体设备的厚度可被减小,设备对于封装以后热应变的寿命也可被延伸得更长。
而且,可以实现这些优点,即,半导体设备的厚度可被减小得更多和设备对于封装以后热应变的寿命也被延伸得更长。
另外,可以实现这些优点,即,半导体设备的厚度可被进一步减少得更多和设备对于封装以后热应变的寿命也可被延伸得更长。
此外,可以实现这些优点,即,金属线的长度可通过使距离最短被构成基本上象L形和半导体设备的厚度可被减小。
Claims (5)
1.一种半导体设备,包括:
层叠半导体芯片,设置一个上层半导体芯片和一个下层半导体芯片,两者分别具有一个上面设有焊盘的主面和与一个与所述主面相对的背面,通过接合材料将所述上层半导体芯片的背面固定到所述下层半导体芯片的所述主面上,呈阶梯状错位,使所述焊盘不重叠,
内部引线,连续形成外部引线,
压料垫,连续形成压料垫沉埋了的压料垫悬挂引线,
接合材料,
金属线,
密封材料;
将所述层叠半导体芯片的背面用接合材料固定到所述压料垫的一个面上,将所述层叠半导体芯片的焊盘与对应的所述内部引线用所述金属线反向金属线焊接连接,将所述内部引线、所述层叠半导体芯片、所述金属线、所述接合材料、和压料垫的五个主要面用所述密封材料覆盖,使所述压料垫的背面露出在密封材料的外面,从所述密封材料的侧面伸出所述外部引线,所述压料垫断面露出在所述密封材料侧面,所述层叠半导体芯片背面通过接合材料被固定在所述压料垫板厚作薄的部分上,用所述金属线连接在所述层叠半导体芯片上设置的焊盘和对应的所述内部引线。
2.根据权利要求1的半导体设备,其特征是,所述层叠半导体芯片被固定成,将所述上层半导体芯片在与半导体芯片平行的面中旋转180度,并且呈台阶状错位层叠,与所述下层半导体芯片的焊盘不重叠。
3.根据权利要求1的半导体设备,其特征是,所述层叠半导体芯片由两个分别具有不同尺寸的半导体芯片构成,使在被载放的所述下层半导体芯片的所述主面上设置的焊盘在载放的所述上层半导体芯片的外围区域上露出。
4.根据权利要求1的半导体设备,其特征是,在所述内引线前端设有薄板轧制台阶。
5.根据权利要求1、2、3或4的半导体设备,其特征是,所述金属线的一端被用球形焊接连到位于所述层叠半导体芯片的层叠厚度范围内的内部引线的一个面上,所述金属线的另一端被用缝合形焊接连到设置在所述层叠半导体芯片的所述上层半导体芯片主面上的焊盘上。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP29342/2001 | 2001-02-06 | ||
JP2001029342A JP2002231882A (ja) | 2001-02-06 | 2001-02-06 | 半導体装置 |
JP29342/01 | 2001-02-06 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1368760A CN1368760A (zh) | 2002-09-11 |
CN1197156C true CN1197156C (zh) | 2005-04-13 |
Family
ID=18893701
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB011357762A Expired - Fee Related CN1197156C (zh) | 2001-02-06 | 2001-10-17 | 半导体设备 |
Country Status (6)
Country | Link |
---|---|
US (1) | US6353265B1 (zh) |
JP (1) | JP2002231882A (zh) |
KR (1) | KR100445502B1 (zh) |
CN (1) | CN1197156C (zh) |
DE (1) | DE10136283A1 (zh) |
TW (1) | TW499722B (zh) |
Families Citing this family (61)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7157314B2 (en) * | 1998-11-16 | 2007-01-02 | Sandisk Corporation | Vertically stacked field programmable nonvolatile memory and method of fabrication |
US8575719B2 (en) | 2000-04-28 | 2013-11-05 | Sandisk 3D Llc | Silicon nitride antifuse for use in diode-antifuse memory arrays |
US6888750B2 (en) * | 2000-04-28 | 2005-05-03 | Matrix Semiconductor, Inc. | Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication |
KR100821456B1 (ko) | 2000-08-14 | 2008-04-11 | 샌디스크 쓰리디 엘엘씨 | 밀집한 어레이 및 전하 저장 장치와, 그 제조 방법 |
JP2002124626A (ja) * | 2000-10-16 | 2002-04-26 | Hitachi Ltd | 半導体装置 |
US6858922B2 (en) * | 2001-01-19 | 2005-02-22 | International Rectifier Corporation | Back-to-back connected power semiconductor device package |
US7352199B2 (en) * | 2001-02-20 | 2008-04-01 | Sandisk Corporation | Memory card with enhanced testability and methods of making and using the same |
US6897514B2 (en) * | 2001-03-28 | 2005-05-24 | Matrix Semiconductor, Inc. | Two mask floating gate EEPROM and method of making |
JP2002343932A (ja) * | 2001-05-17 | 2002-11-29 | Mitsubishi Electric Corp | 半導体装置と半導体装置の製造方法 |
US6593624B2 (en) | 2001-09-25 | 2003-07-15 | Matrix Semiconductor, Inc. | Thin film transistors with vertically offset drain regions |
US6525953B1 (en) | 2001-08-13 | 2003-02-25 | Matrix Semiconductor, Inc. | Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication |
US6843421B2 (en) | 2001-08-13 | 2005-01-18 | Matrix Semiconductor, Inc. | Molded memory module and method of making the module absent a substrate support |
US6841813B2 (en) * | 2001-08-13 | 2005-01-11 | Matrix Semiconductor, Inc. | TFT mask ROM and method for making same |
JP2003101204A (ja) * | 2001-09-25 | 2003-04-04 | Nec Kansai Ltd | 配線基板及び配線基板の製造方法並びに電子部品 |
US6624485B2 (en) | 2001-11-05 | 2003-09-23 | Matrix Semiconductor, Inc. | Three-dimensional, mask-programmed read only memory |
US7190060B1 (en) | 2002-01-09 | 2007-03-13 | Bridge Semiconductor Corporation | Three-dimensional stacked semiconductor package device with bent and flat leads and method of making same |
US6936495B1 (en) | 2002-01-09 | 2005-08-30 | Bridge Semiconductor Corporation | Method of making an optoelectronic semiconductor package device |
US6989295B1 (en) | 2002-01-09 | 2006-01-24 | Bridge Semiconductor Corporation | Method of making a semiconductor package device that includes an insulative housing with first and second housing portions |
US6891276B1 (en) | 2002-01-09 | 2005-05-10 | Bridge Semiconductor Corporation | Semiconductor package device |
US6731011B2 (en) | 2002-02-19 | 2004-05-04 | Matrix Semiconductor, Inc. | Memory module having interconnected and stacked integrated circuits |
US6509637B1 (en) * | 2002-03-08 | 2003-01-21 | Amkor Technology, Inc. | Low profile mounting of thick integrated circuit packages within low-profile circuit modules |
US6853049B2 (en) * | 2002-03-13 | 2005-02-08 | Matrix Semiconductor, Inc. | Silicide-silicon oxide-semiconductor antifuse device and method of making |
US7145223B2 (en) * | 2002-05-22 | 2006-12-05 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device |
US6737675B2 (en) | 2002-06-27 | 2004-05-18 | Matrix Semiconductor, Inc. | High density 3D rail stack arrays |
US6919620B1 (en) * | 2002-09-17 | 2005-07-19 | Amkor Technology, Inc. | Compact flash memory card with clamshell leadframe |
DE10243981B4 (de) * | 2002-09-20 | 2015-06-03 | Robert Bosch Gmbh | Elektronische Baueinheit, insbesondere Regler für Generatoren in Kraftfahrzeugen |
US20050067694A1 (en) * | 2003-09-30 | 2005-03-31 | Pon Florence R. | Spacerless die stacking |
JP2005150456A (ja) * | 2003-11-17 | 2005-06-09 | Oki Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2005150647A (ja) * | 2003-11-20 | 2005-06-09 | Renesas Technology Corp | 半導体装置及びその製造方法 |
JP3941953B2 (ja) * | 2003-12-03 | 2007-07-11 | 松下電器産業株式会社 | 半導体装置およびその製造方法 |
KR100543729B1 (ko) * | 2004-03-24 | 2006-01-20 | 아바고테크놀로지스코리아 주식회사 | 열 방출 효율이 높고 두께는 물론 크기를 감소시킨 고주파모듈 패키지 및 그 조립 방법 |
US6933223B1 (en) | 2004-04-15 | 2005-08-23 | National Semiconductor Corporation | Ultra-low loop wire bonding |
US20060027901A1 (en) * | 2004-08-09 | 2006-02-09 | Ming-Sung Tsai | Stacked chip package with exposed lead-frame bottom surface |
US7446396B2 (en) * | 2005-02-10 | 2008-11-04 | Stats Chippac Ltd. | Stacked integrated circuit leadframe package system |
JP2006278913A (ja) * | 2005-03-30 | 2006-10-12 | Toyota Motor Corp | 回路装置とその製造方法 |
JP4674113B2 (ja) * | 2005-05-06 | 2011-04-20 | Okiセミコンダクタ株式会社 | 半導体装置及びその製造方法 |
JP2007129182A (ja) | 2005-05-11 | 2007-05-24 | Toshiba Corp | 半導体装置 |
CN100411170C (zh) * | 2005-05-30 | 2008-08-13 | 矽品精密工业股份有限公司 | 多芯片堆栈结构 |
US7727816B2 (en) | 2006-07-21 | 2010-06-01 | Stats Chippac Ltd. | Integrated circuit package system with offset stacked die |
JP5110247B2 (ja) * | 2006-07-31 | 2012-12-26 | ミツミ電機株式会社 | 半導体集積回路装置 |
JP2008033724A (ja) * | 2006-07-31 | 2008-02-14 | Mitsumi Electric Co Ltd | シングル・チップ半導体集積回路装置の製造方法、プログラムデバッグ方法、マイクロコントローラの製造方法 |
US7618848B2 (en) * | 2006-08-09 | 2009-11-17 | Stats Chippac Ltd. | Integrated circuit package system with supported stacked die |
JP2008085002A (ja) * | 2006-09-27 | 2008-04-10 | Sanyo Electric Co Ltd | 半導体装置およびその製造方法 |
TW200820402A (en) * | 2006-10-26 | 2008-05-01 | Chipmos Technologies Inc | Stacked chip packaging with heat sink struct |
US7635913B2 (en) * | 2006-12-09 | 2009-12-22 | Stats Chippac Ltd. | Stacked integrated circuit package-in-package system |
US8304874B2 (en) * | 2006-12-09 | 2012-11-06 | Stats Chippac Ltd. | Stackable integrated circuit package system |
US7772683B2 (en) * | 2006-12-09 | 2010-08-10 | Stats Chippac Ltd. | Stacked integrated circuit package-in-package system |
TWI327365B (en) * | 2007-01-19 | 2010-07-11 | Chipmos Technologies Inc | Zigzag-stacked chip package structure |
JP4835449B2 (ja) * | 2007-01-29 | 2011-12-14 | 株式会社デンソー | 半導体装置 |
KR101557273B1 (ko) | 2009-03-17 | 2015-10-05 | 삼성전자주식회사 | 반도체 패키지 |
KR100881198B1 (ko) | 2007-06-20 | 2009-02-05 | 삼성전자주식회사 | 반도체 패키지 및 이를 실장한 반도체 패키지 모듈 |
US20090091009A1 (en) * | 2007-10-03 | 2009-04-09 | Corisis David J | Stackable integrated circuit package |
JP5183186B2 (ja) * | 2007-12-14 | 2013-04-17 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US8399973B2 (en) | 2007-12-20 | 2013-03-19 | Mosaid Technologies Incorporated | Data storage and stackable configurations |
JP2009252815A (ja) * | 2008-04-02 | 2009-10-29 | Toppan Printing Co Ltd | 複合リードフレーム構造体及び半導体装置 |
KR101660430B1 (ko) | 2009-08-14 | 2016-09-27 | 삼성전자 주식회사 | 반도체 패키지 |
KR101909203B1 (ko) | 2011-07-21 | 2018-10-17 | 삼성전자 주식회사 | 멀티-채널 패키지 및 그 패키지를 포함한 전자 시스템 |
US9627395B2 (en) | 2015-02-11 | 2017-04-18 | Sandisk Technologies Llc | Enhanced channel mobility three-dimensional memory structure and method of making thereof |
US9478495B1 (en) | 2015-10-26 | 2016-10-25 | Sandisk Technologies Llc | Three dimensional memory device containing aluminum source contact via structure and method of making thereof |
CN108155158A (zh) * | 2017-12-22 | 2018-06-12 | 中国电子科技集团公司第四十七研究所 | 大容量存储器电路的3d封装结构 |
CN215644456U (zh) * | 2020-03-27 | 2022-01-25 | 意法半导体有限公司 | 半导体器件 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04302164A (ja) | 1991-03-29 | 1992-10-26 | Fujitsu Ltd | 半導体装置 |
JP3203200B2 (ja) | 1997-03-10 | 2001-08-27 | 三洋電機株式会社 | 半導体装置 |
JP3359846B2 (ja) * | 1997-07-18 | 2002-12-24 | シャープ株式会社 | 半導体装置 |
JP3077668B2 (ja) * | 1998-05-01 | 2000-08-14 | 日本電気株式会社 | 半導体装置、半導体装置用リードフレームおよびその製造方法 |
KR100277438B1 (ko) * | 1998-05-28 | 2001-02-01 | 윤종용 | 멀티칩패키지 |
JP2000156464A (ja) | 1998-11-20 | 2000-06-06 | Hitachi Ltd | 半導体装置の製造方法 |
-
2001
- 2001-02-06 JP JP2001029342A patent/JP2002231882A/ja not_active Withdrawn
- 2001-06-11 US US09/877,038 patent/US6353265B1/en not_active Expired - Lifetime
- 2001-07-25 DE DE2001136283 patent/DE10136283A1/de not_active Ceased
- 2001-09-03 TW TW90121747A patent/TW499722B/zh not_active IP Right Cessation
- 2001-10-17 KR KR10-2001-0063891A patent/KR100445502B1/ko not_active IP Right Cessation
- 2001-10-17 CN CNB011357762A patent/CN1197156C/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
DE10136283A1 (de) | 2002-08-22 |
KR100445502B1 (ko) | 2004-08-21 |
JP2002231882A (ja) | 2002-08-16 |
KR20020065326A (ko) | 2002-08-13 |
CN1368760A (zh) | 2002-09-11 |
US6353265B1 (en) | 2002-03-05 |
TW499722B (en) | 2002-08-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN1197156C (zh) | 半导体设备 | |
CN1230882C (zh) | 一种半导体器件的制造方法和一种半导体器件 | |
CN1267978C (zh) | 凸点的形成方法、半导体元件与半导体装置及其制造方法、电路板以及电子机器 | |
CN1079167C (zh) | 丝焊方法、半导体器件,丝焊的毛细管及球块形成方法 | |
CN1280884C (zh) | 半导体装置及其制造方法、电路板以及电子机器 | |
CN1155084C (zh) | 引线框架及其制造方法、半导体装置及其制造方法 | |
CN1169215C (zh) | 半导体器件及其制造方法 | |
CN1779951A (zh) | 半导体器件及其制造方法 | |
CN1175497C (zh) | 光半导体装置及其装配的光半导体模块 | |
CN1132244C (zh) | 树脂封装型半导体装置及其制造方法 | |
CN1150616C (zh) | 半导体器件及其制造和装配方法 | |
JP4624170B2 (ja) | 半導体装置の製造方法 | |
CN1207585A (zh) | 半导体装置及半导体装置的引线框架 | |
CN1641873A (zh) | 多芯片封装、其中使用的半导体器件及其制造方法 | |
CN1283004C (zh) | 半导体装置及其制造方法、线路基板及电子机器 | |
CN1381886A (zh) | 半导体器件和封装及其制造方法 | |
CN1649098A (zh) | 半导体器件 | |
CN1260795C (zh) | 半导体装置及其制造方法、电路板以及电子机器 | |
CN1638111A (zh) | 半导体元件的制造方法 | |
CN1574346A (zh) | 一种制造半导体器件的方法 | |
CN1649149A (zh) | 三维半导体封装,以及用于其中的间隔芯片 | |
CN1828880A (zh) | 用于指纹识别的半导体装置 | |
CN1877824A (zh) | 半导体器件、层叠式半导体器件和半导体器件的制造方法 | |
CN1622328A (zh) | 半导体器件及其制造方法 | |
CN1344014A (zh) | 半导体器件和半导体组件 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C17 | Cessation of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20050413 Termination date: 20101017 |